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https://github.com/LibreELEC/LibreELEC.tv.git
synced 2025-07-29 13:46:49 +00:00
Add patches for drm/i915: set HDMI pixel clock in audio configuration
This commit is contained in:
Jasper Smet
parent
eaa61fd01b
commit
fba016086b
66
packages/linux/patches/3.11.5/linux-992.01.i915_pass_mode_to_write_eld.patch
vendored
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66
packages/linux/patches/3.11.5/linux-992.01.i915_pass_mode_to_write_eld.patch
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@ -0,0 +1,66 @@
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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---
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drivers/gpu/drm/i915/i915_drv.h | 3 ++-
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drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
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2 files changed, 9 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
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index 6106d3d..caee590 100644
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -379,7 +379,8 @@ struct drm_i915_display_funcs {
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void (*crtc_disable)(struct drm_crtc *crtc);
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void (*off)(struct drm_crtc *crtc);
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void (*write_eld)(struct drm_connector *connector,
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- struct drm_crtc *crtc);
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+ struct drm_crtc *crtc,
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+ struct drm_display_mode *mode);
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void (*fdi_link_train)(struct drm_crtc *crtc);
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void (*init_clock_gating)(struct drm_device *dev);
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int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index 4f1b636..55740f2 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -6752,7 +6752,8 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
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}
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static void g4x_write_eld(struct drm_connector *connector,
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- struct drm_crtc *crtc)
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+ struct drm_crtc *crtc,
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+ struct drm_display_mode *mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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uint8_t *eld = connector->eld;
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@@ -6792,7 +6793,8 @@ static void g4x_write_eld(struct drm_connector *connector,
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}
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static void haswell_write_eld(struct drm_connector *connector,
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- struct drm_crtc *crtc)
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+ struct drm_crtc *crtc,
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+ struct drm_display_mode *mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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uint8_t *eld = connector->eld;
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@@ -6879,7 +6881,8 @@ static void haswell_write_eld(struct drm_connector *connector,
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}
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static void ironlake_write_eld(struct drm_connector *connector,
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- struct drm_crtc *crtc)
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+ struct drm_crtc *crtc,
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+ struct drm_display_mode *mode)
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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uint8_t *eld = connector->eld;
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@@ -6974,7 +6977,7 @@ void intel_write_eld(struct drm_encoder *encoder,
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connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
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if (dev_priv->display.write_eld)
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- dev_priv->display.write_eld(connector, crtc);
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+ dev_priv->display.write_eld(connector, crtc, mode);
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}
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static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
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--
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1.7.9.5
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110
packages/linux/patches/3.11.5/linux-992.02-i915_set_hdmi_audio_clock.patch
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110
packages/linux/patches/3.11.5/linux-992.02-i915_set_hdmi_audio_clock.patch
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@ -0,0 +1,110 @@
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Reference: http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
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Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
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Reported-by: David Härdeman <david@hardeman.nu>
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Reported-by: Jasper Smet <josbeir@gmail.com>
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Tested-by: Jasper Smet <josbeir@gmail.com>
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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---
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drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++-
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drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++++++++++++---
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2 files changed, 55 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index 13153c3..3266819 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -4875,7 +4875,17 @@
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#define AUD_CONFIG_LOWER_N_SHIFT 4
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#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
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#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
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-#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
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+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
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#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
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/* HSW Audio */
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index 55740f2..a097f84 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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return 0;
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}
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+static struct {
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+ int clock;
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+ u32 config;
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+} hdmi_audio_clock[] = {
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+ { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
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+ { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
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+ { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
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+ { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
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+ { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
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+ { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
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+ { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
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+ { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
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+ { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
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+ { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
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+};
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+
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+/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
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+static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
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+ if (mode->clock == hdmi_audio_clock[i].clock)
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+ break;
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+ }
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+
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+ if (i == ARRAY_SIZE(hdmi_audio_clock)) {
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+ DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
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+ i = 1;
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+ }
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+
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+ DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
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+ hdmi_audio_clock[i].clock,
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+ hdmi_audio_clock[i].config);
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+
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+ return hdmi_audio_clock[i].config;
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+}
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+
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static bool intel_eld_uptodate(struct drm_connector *connector,
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int reg_eldv, uint32_t bits_eldv,
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int reg_elda, uint32_t bits_elda,
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@@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct drm_connector *connector,
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DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
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eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
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I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
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- } else
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- I915_WRITE(aud_config, 0);
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+ } else {
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+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
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+ }
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if (intel_eld_uptodate(connector,
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aud_cntrl_st2, eldv,
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@@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct drm_connector *connector,
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DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
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eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
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I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
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- } else
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- I915_WRITE(aud_config, 0);
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+ } else {
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+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
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+ }
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if (intel_eld_uptodate(connector,
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aud_cntrl_st2, eldv,
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--
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1.7.9.5
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