From 1bc59fbcc6cdca5542120a0bcd3e91d8fa26f84c Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Tue, 19 May 2020 23:06:08 +0200 Subject: [PATCH] Allwinner: Update patches for Linux 5.7 --- .../H6/patches/linux/12-ac200-nodes.patch | 4 +- .../linux/18-OrangePi-Lite2-support.patch | 176 --- projects/Allwinner/linux/linux.aarch64.conf | 185 ++- projects/Allwinner/linux/linux.arm.conf | 169 ++- .../linux/0001-backport-from-5.7.patch | 704 ---------- .../linux/0001-backport-from-5.8.patch | 1244 +++++++++++++++++ .../linux/0003-hdmi-improvements.patch | 169 --- .../linux/0005-cedrus-improvements.patch | 37 - 8 files changed, 1500 insertions(+), 1188 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0001-backport-from-5.7.patch create mode 100644 projects/Allwinner/patches/linux/0001-backport-from-5.8.patch diff --git a/projects/Allwinner/devices/H6/patches/linux/12-ac200-nodes.patch b/projects/Allwinner/devices/H6/patches/linux/12-ac200-nodes.patch index 1f24d73489..8b8b5c4e4d 100644 --- a/projects/Allwinner/devices/H6/patches/linux/12-ac200-nodes.patch +++ b/projects/Allwinner/devices/H6/patches/linux/12-ac200-nodes.patch @@ -30,8 +30,8 @@ index 8eec8685a50b..5eeb7da7a0ab 100644 #address-cells = <1>; #size-cells = <0>; @@ -218,6 +228,10 @@ - ths_calibration: thermal-sensor-calibration@14 { - reg = <0x14 0x8>; + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x4>; }; + + ephy_calib: ephy_calib@2c { diff --git a/projects/Allwinner/devices/H6/patches/linux/18-OrangePi-Lite2-support.patch b/projects/Allwinner/devices/H6/patches/linux/18-OrangePi-Lite2-support.patch index 90ed61b4ca..e3e3c95a51 100644 --- a/projects/Allwinner/devices/H6/patches/linux/18-OrangePi-Lite2-support.patch +++ b/projects/Allwinner/devices/H6/patches/linux/18-OrangePi-Lite2-support.patch @@ -1,179 +1,3 @@ -From 9b743eadc7adb8a5ffe79742ea3925d2903788f2 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 4 Apr 2020 20:42:41 +0200 -Subject: [PATCH 1/4] arm64: dts: allwinner: h6: orangepi: Add gpio power - supply - -OrangePi Lite2 and One Plus have GPIO ports powered by same power -supplies. Add them in common DT. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index 9287976c4a50..f1be3dd558ca 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -106,6 +106,12 @@ &ohci3 { - status = "okay"; - }; - -+&pio { -+ vcc-pc-supply = <®_bldo2>; -+ vcc-pd-supply = <®_cldo1>; -+ vcc-pg-supply = <®_aldo1>; -+}; -+ - &r_i2c { - status = "okay"; - -@@ -230,6 +236,10 @@ &r_ir { - status = "okay"; - }; - -+&r_pio { -+ vcc-pm-supply = <®_bldo3>; -+}; -+ - &rtc { - clocks = <&ext_osc32k>; - }; --- -2.26.0 - - -From d98355dc8de0a3075a49f6ecb103dd67e68ac0c8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 4 Apr 2020 20:55:52 +0200 -Subject: [PATCH 2/4] arm64: dts: allwinner: h6: orangepi: Disable OTG mode - -As can be seen from OrangePi Lite 2 and One Plus schematics, VBUS pin on -USB OTG port is directly connected to 5 V power supply. This mean that -OTG port can safely operate only in host mode, even though these two -boards have ID pin connected. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index f1be3dd558ca..ebc120a9232f 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -251,7 +251,12 @@ &uart0 { - }; - - &usb2otg { -- dr_mode = "otg"; -+ /* -+ * OrangePi Lite 2 and One Plus, where this DT is used, don't -+ * have a controllable VBUS even though they do have an ID pin. -+ * Using it as anything but a USB host is unsafe. -+ */ -+ dr_mode = "host"; - status = "okay"; - }; - --- -2.26.0 - - -From 0e4de8b92b2cab1e4dbeef5ef2913b745b25c39f Mon Sep 17 00:00:00 2001 -From: Sebastian Meyer -Date: Mon, 3 Feb 2020 21:06:07 +0100 -Subject: [PATCH 3/4] arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI - combo module - -OrangePi Lite2 has AP6255 BT+WIFI combo chip. Add support for it. - -Signed-off-by: Sebastian Meyer -[merged BT and WIFI patches and updated commit message] -Signed-off-by: Jernej Skrabec ---- - .../allwinner/sun50i-h6-orangepi-lite2.dts | 65 +++++++++++++++++++ - 1 file changed, 65 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts -index e7ca75c0d0f7..e8770858b5d0 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts -@@ -6,4 +6,69 @@ - / { - model = "OrangePi Lite2"; - compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; -+ -+ aliases { -+ serial1 = &uart1; /* BT-UART */ -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; -+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ -+ post-power-on-delay-ms = <200>; -+ }; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_cldo2>; -+ vqmmc-supply = <®_bldo3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ brcm: sdio-wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&r_pio>; -+ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+®_cldo2 { -+ /* -+ * This regulator is connected with CLDO3. -+ * Before the kernel can support synchronized -+ * enable of coupled regulators, keep them -+ * both always on as a ugly hack. -+ */ -+ regulator-always-on; -+}; -+ -+®_cldo3 { -+ /* -+ * This regulator is connected with CLDO2. -+ * See the comments for CLDO2. -+ */ -+ regulator-always-on; -+}; -+ -+/* There's the BT part of the AP6255 connected to that UART */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rtc 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ -+ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ -+ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ -+ max-speed = <1500000>; -+ }; - }; --- -2.26.0 - - From e087c727b23ed0665136973e24a0292c14522723 Mon Sep 17 00:00:00 2001 From: Sebastian Meyer Date: Mon, 3 Feb 2020 21:27:47 +0100 diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index bc47f81a47..7b452b22f5 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.6.12 Kernel Configuration +# Linux/arm64 5.7.0 Kernel Configuration # # @@ -8,11 +8,11 @@ # CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=90201 +CONFIG_LD_VERSION=233010000 CONFIG_CLANG_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y -CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -59,7 +59,6 @@ CONFIG_SPARSE_IRQ=y # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -90,6 +89,7 @@ CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_SCHED_AVG_IRQ=y +# CONFIG_SCHED_THERMAL_PRESSURE is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y @@ -265,6 +265,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y CONFIG_FIX_EARLYCON_MEM=y @@ -431,8 +432,18 @@ CONFIG_ARM64_CNP=y # ARMv8.3 architectural features # CONFIG_ARM64_PTR_AUTH=y +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y +CONFIG_AS_HAS_PAC=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y # end of ARMv8.3 architectural features +# +# ARMv8.4 architectural features +# +CONFIG_ARM64_AMU_EXTN=y +# end of ARMv8.4 architectural features + # # ARMv8.5 architectural features # @@ -573,8 +584,8 @@ CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m -CONFIG_CRYPTO_CHACHA20_NEON=m -# CONFIG_CRYPTO_POLY1305_NEON is not set +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_POLY1305_NEON=y # CONFIG_CRYPTO_NHPOLY1305_NEON is not set CONFIG_CRYPTO_AES_ARM64_BS=m @@ -648,6 +659,7 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_COMPILER_H=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set @@ -659,8 +671,8 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling -CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -723,6 +735,7 @@ CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y @@ -756,6 +769,7 @@ CONFIG_MEMORY_ISOLATION=y # CONFIG_MEMORY_HOTPLUG is not set CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y +# CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y @@ -768,7 +782,6 @@ CONFIG_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TRANSPARENT_HUGE_PAGECACHE=y # CONFIG_CLEANCACHE is not set # CONFIG_FRONTSWAP is not set CONFIG_CMA=y @@ -821,11 +834,11 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IP_TUNNEL=y # CONFIG_IP_MROUTE is not set # CONFIG_SYN_COOKIES is not set # CONFIG_NET_IPVTI is not set -CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_UDP_TUNNEL=y CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set @@ -833,7 +846,7 @@ CONFIG_INET_ESP=y # CONFIG_INET_ESP_OFFLOAD is not set # CONFIG_INET_ESPINTCP is not set # CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m +CONFIG_INET_TUNNEL=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_INET_UDP_DIAG is not set @@ -843,7 +856,7 @@ CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m +CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set # CONFIG_INET6_AH is not set @@ -852,7 +865,7 @@ CONFIG_IPV6=m # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set # CONFIG_IPV6_VTI is not set -CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT=y # CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_TUNNEL is not set @@ -861,6 +874,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set @@ -1259,6 +1273,7 @@ CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y @@ -1380,6 +1395,7 @@ CONFIG_SIMPLE_PM_BUS=y CONFIG_SUN50I_DE2_BUS=y CONFIG_SUNXI_RSB=y CONFIG_VEXPRESS_CONFIG=y +# CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set @@ -1464,7 +1480,6 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_SPI_CADENCE_QUADSPI is not set -# CONFIG_SPI_MTK_QUADSPI is not set # CONFIG_MTD_UBI is not set # CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y @@ -1556,6 +1571,7 @@ CONFIG_EEPROM_93CX6=m # CONFIG_ECHO is not set # CONFIG_MISC_RTSX_USB is not set +# CONFIG_UACCE is not set # end of Misc devices # @@ -1573,7 +1589,6 @@ CONFIG_SCSI_DMA=y CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y @@ -1608,7 +1623,9 @@ CONFIG_SCSI_UFSHCD_PLATFORM=m CONFIG_HAVE_PATA_PLATFORM=y CONFIG_ATA=y +CONFIG_SATA_HOST=y CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y CONFIG_SATA_PMP=y # @@ -1680,7 +1697,8 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set CONFIG_DUMMY=m -# CONFIG_WIREGUARD is not set +CONFIG_WIREGUARD=y +# CONFIG_WIREGUARD_DEBUG is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set CONFIG_MACVLAN=m @@ -1690,6 +1708,7 @@ CONFIG_IPVLAN=m # CONFIG_IPVTAP is not set CONFIG_VXLAN=m # CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set # CONFIG_GTP is not set # CONFIG_MACSEC is not set # CONFIG_NETCONSOLE is not set @@ -1803,9 +1822,12 @@ CONFIG_MDIO_BUS_MUX_MMIOREG=y # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_GPIO is not set # CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_IPQ8064 is not set # CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_MVUSB is not set # CONFIG_MDIO_OCTEON is not set # CONFIG_MDIO_SUN4I is not set +CONFIG_MDIO_XPCS=y CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y @@ -2244,12 +2266,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -# CONFIG_NULL_TTY is not set CONFIG_LDISC_AUTOLOAD=y -CONFIG_DEVMEM=y # # Serial drivers @@ -2299,16 +2316,22 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_FSL_LPUART is not set # CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -# CONFIG_HVC_DCC is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_DEVMEM=y # CONFIG_RAW_DRIVER is not set CONFIG_TCG_TPM=y # CONFIG_TCG_TIS is not set @@ -2322,6 +2345,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_XILLYBUS is not set # end of Character devices +# CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # @@ -2423,6 +2447,11 @@ CONFIG_SPI_ROCKCHIP=y # CONFIG_SPI_XILINX is not set # CONFIG_SPI_ZYNQMP_GQSPI is not set +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + # # SPI Protocol Masters # @@ -2454,6 +2483,7 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support @@ -2638,6 +2668,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set @@ -2848,6 +2879,7 @@ CONFIG_MFD_AXP20X_RSB=y CONFIG_MFD_HI6421_PMIC=y # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set @@ -2932,7 +2964,6 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ANATOP is not set CONFIG_REGULATOR_AXP20X=y # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -2955,7 +2986,9 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set # CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PFUZE100 is not set @@ -3079,7 +3112,6 @@ CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_PVRUSB2_DVB=y # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_USBVISION=m CONFIG_VIDEO_STK1160_COMMON=m CONFIG_VIDEO_STK1160=m CONFIG_VIDEO_GO7007=m @@ -3168,6 +3200,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_SH_VEU is not set CONFIG_VIDEO_SUN8I_DEINTERLACE=m +CONFIG_VIDEO_SUN8I_ROTATE=m # CONFIG_V4L_TEST_DRIVERS is not set CONFIG_DVB_PLATFORM_DRIVERS=y CONFIG_CEC_PLATFORM_DRIVERS=y @@ -3511,11 +3544,6 @@ CONFIG_DRM_I2C_SIL164=m # CONFIG_DRM_KOMEDA is not set # end of ARM devices -# -# ACP (Audio CoProcessor) Configuration -# -# end of ACP (Audio CoProcessor) Configuration - # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set # CONFIG_DRM_UDL is not set @@ -3546,6 +3574,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set @@ -3563,19 +3592,23 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set -# CONFIG_DRM_DUMB_VGA_DAC is not set +CONFIG_DRM_DISPLAY_CONNECTOR=y # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set # CONFIG_DRM_SIL_SII8620 is not set # CONFIG_DRM_SII902X is not set # CONFIG_DRM_SII9234 is not set +CONFIG_DRM_SIMPLE_BRIDGE=y # CONFIG_DRM_THINE_THC63LVD1024 is not set # CONFIG_DRM_TOSHIBA_TC358764 is not set # CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set CONFIG_DRM_ANALOGIX_ANX6345=m # CONFIG_DRM_ANALOGIX_ANX78XX is not set CONFIG_DRM_ANALOGIX_DP=m @@ -3594,6 +3627,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set # CONFIG_TINYDRM_MI0283QT is not set # CONFIG_TINYDRM_REPAPER is not set # CONFIG_TINYDRM_ST7586 is not set @@ -3601,6 +3635,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_PL111 is not set CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m +# CONFIG_DRM_TIDSS is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3739,6 +3774,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set # @@ -3887,6 +3923,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set # CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set # CONFIG_SND_SOC_TSCS454 is not set @@ -3971,6 +4008,7 @@ CONFIG_DRAGONRISE_FF=y CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +CONFIG_HID_GLORIOUS=m # CONFIG_HID_HOLTEK is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set @@ -4039,6 +4077,7 @@ CONFIG_HID_XINMO=m CONFIG_HID_ZYDACRON=m # CONFIG_HID_SENSOR_HUB is not set # CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set # end of Special HID drivers # @@ -4204,6 +4243,7 @@ CONFIG_USB_ISP1760_DUAL_ROLE=y # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set @@ -4256,10 +4296,34 @@ CONFIG_USB_BDC_UDC=y # # CONFIG_USB_NET2272 is not set # CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_MAX3420_UDC is not set # CONFIG_USB_DUMMY_HCD is not set # end of USB Peripheral Controller # CONFIG_USB_CONFIGFS is not set + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_RAW_GADGET is not set +# end of USB Gadget precomposed configurations + # CONFIG_TYPEC is not set CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=y @@ -4298,6 +4362,7 @@ CONFIG_MMC_DW_K3=y # CONFIG_MMC_USDHI6ROL0 is not set CONFIG_MMC_SUNXI=y CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set # CONFIG_MMC_MTK is not set CONFIG_MMC_SDHCI_XENON=y # CONFIG_MMC_SDHCI_OMAP is not set @@ -4489,7 +4554,6 @@ CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_SUN6I=y # CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_R7301 is not set # @@ -4535,6 +4599,7 @@ CONFIG_DMA_ENGINE_RAID=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -4546,6 +4611,9 @@ CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set # CONFIG_VIRTIO_MENU is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_DPN=y +# CONFIG_VHOST_MENU is not set # # Microsoft Hyper-V guest support @@ -4577,7 +4645,6 @@ CONFIG_RTL8723BS=m # Analog to digital converters # # CONFIG_AD7816 is not set -# CONFIG_AD7192 is not set # CONFIG_AD7280 is not set # end of Analog to digital converters @@ -4633,6 +4700,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # # soc_camera sensor drivers # +CONFIG_VIDEO_USBVISION=m # # Android @@ -4647,7 +4715,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_FB_TFT is not set # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set -# CONFIG_MOST is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set @@ -4658,9 +4725,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set -# CONFIG_USB_WUSB_CBAF is not set -# CONFIG_UWB is not set -# CONFIG_STAGING_EXFAT_FS is not set # CONFIG_WFX is not set # CONFIG_GOLDFISH is not set # CONFIG_MFD_CROS_EC is not set @@ -4729,6 +4793,7 @@ CONFIG_PLATFORM_MHU=y # CONFIG_PL320_MBOX is not set # CONFIG_ALTERA_MBOX is not set # CONFIG_MAILBOX_TEST is not set +CONFIG_SUN6I_MSGBOX=y CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -4895,6 +4960,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set # CONFIG_AD7266 is not set # CONFIG_AD7291 is not set # CONFIG_AD7292 is not set @@ -4959,6 +5025,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # Amplifiers # # CONFIG_AD8366 is not set +# CONFIG_HMC425 is not set # end of Amplifiers # @@ -4998,19 +5065,20 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD5593R is not set # CONFIG_AD5504 is not set # CONFIG_AD5624R_SPI is not set -# CONFIG_LTC1660 is not set -# CONFIG_LTC2632 is not set # CONFIG_AD5686_SPI is not set # CONFIG_AD5696_I2C is not set # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set # CONFIG_DS4424 is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set # CONFIG_M62332 is not set # CONFIG_MAX517 is not set # CONFIG_MAX5821 is not set @@ -5108,6 +5176,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # CONFIG_ADJD_S311 is not set # CONFIG_ADUX1020 is not set +# CONFIG_AL3010 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set @@ -5118,6 +5187,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set @@ -5185,6 +5255,11 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IIO_SYSFS_TRIGGER is not set # end of Triggers - standalone +# +# Linear and angular position sensors +# +# end of Linear and angular position sensors + # # Digital potentiometers # @@ -5214,6 +5289,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_DLHL60D is not set # CONFIG_DPS310 is not set # CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set @@ -5268,6 +5344,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_PWM=y CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SUN4I=y @@ -5303,7 +5380,7 @@ CONFIG_PHY_SUN4I_USB=y # CONFIG_PHY_SUN9I_USB is not set CONFIG_PHY_SUN50I_USB3=y # CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set @@ -5362,6 +5439,7 @@ CONFIG_PM_OPP=y # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set +# CONFIG_MOST is not set # end of Device Drivers # @@ -5409,6 +5487,7 @@ CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_ZSTD=y # CONFIG_FS_DAX is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -5457,7 +5536,7 @@ CONFIG_UDF_FS=y # end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y # CONFIG_MSDOS_FS is not set @@ -5465,8 +5544,9 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set -# end of DOS/FAT/NT Filesystems +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -5842,15 +5922,18 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m -# CONFIG_CRYPTO_LIB_BLAKE2S is not set -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_BLAKE2S=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ALLWINNER=y @@ -5927,7 +6010,7 @@ CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_COMPRESS=m +CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y @@ -6023,7 +6106,6 @@ CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set -CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_ARCH_WANT_FRAME_POINTERS=y @@ -6037,12 +6119,12 @@ CONFIG_FRAME_POINTER=y CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y # CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y # end of Generic Kernel Debugging Instruments CONFIG_DEBUG_KERNEL=y @@ -6088,6 +6170,7 @@ CONFIG_PANIC_TIMEOUT=0 # CONFIG_SOFTLOCKUP_DETECTOR is not set # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs # @@ -6170,7 +6253,6 @@ CONFIG_STRICT_DEVMEM=y # CONFIG_PID_IN_CONTEXTIDR is not set # CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set # CONFIG_DEBUG_WX is not set -# CONFIG_DEBUG_ALIGN_RODATA is not set # CONFIG_ARM64_RELOC_TEST is not set # CONFIG_CORESIGHT is not set # end of arm64 Debugging @@ -6187,6 +6269,7 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index 9aa33d3d7d..67510ce2b9 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,18 +1,18 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.6.0-rc7 Kernel Configuration +# Linux/arm 5.7.0 Kernel Configuration # # -# Compiler: armv7ve-libreelec-linux-gnueabihf-gcc-9.2.0 (GCC) 9.2.0 +# Compiler: armv7ve-libreelec-linux-gnueabihf-gcc-9.3.0 (GCC) 9.3.0 # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=90200 +CONFIG_GCC_VERSION=90300 +CONFIG_LD_VERSION=234000000 CONFIG_CLANG_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_INLINE=y -CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y @@ -64,7 +64,6 @@ CONFIG_SPARSE_IRQ=y # end of IRQ subsystem CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y @@ -92,6 +91,7 @@ CONFIG_PREEMPT_NONE=y CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_SCHED_THERMAL_PRESSURE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_PSI is not set @@ -592,8 +592,7 @@ CONFIG_CRYPTO_SHA256_ARM=y CONFIG_CRYPTO_SHA512_ARM=y CONFIG_CRYPTO_AES_ARM=y # CONFIG_CRYPTO_CHACHA20_NEON is not set -# CONFIG_CRYPTO_POLY1305_ARM is not set -# CONFIG_VIRTUALIZATION is not set +CONFIG_CRYPTO_POLY1305_ARM=y # # General architecture-dependent options @@ -660,8 +659,8 @@ CONFIG_ARCH_HAS_PHYS_TO_DMA=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling -CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -740,6 +739,7 @@ CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_FREEZER=y # @@ -766,6 +766,7 @@ CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y +# CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y @@ -819,14 +820,14 @@ CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IP_TUNNEL=y CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y # CONFIG_IP_PIMSM_V1 is not set # CONFIG_IP_PIMSM_V2 is not set # CONFIG_SYN_COOKIES is not set # CONFIG_NET_IPVTI is not set -CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_UDP_TUNNEL=y CONFIG_NET_FOU=m # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_INET_AH is not set @@ -834,7 +835,7 @@ CONFIG_INET_ESP=m # CONFIG_INET_ESP_OFFLOAD is not set # CONFIG_INET_ESPINTCP is not set # CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=m +CONFIG_INET_TUNNEL=y # CONFIG_INET_DIAG is not set # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y @@ -849,7 +850,7 @@ CONFIG_IPV6=y # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set # CONFIG_IPV6_VTI is not set -CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT=y # CONFIG_IPV6_SIT_6RD is not set CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_TUNNEL is not set @@ -858,6 +859,7 @@ CONFIG_IPV6_FOU=m # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set # CONFIG_MPTCP is not set # CONFIG_NETWORK_SECMARK is not set CONFIG_NET_PTP_CLASSIFY=y @@ -1270,6 +1272,7 @@ CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y @@ -1388,6 +1391,7 @@ CONFIG_ARM_CCI400_PORT_CTRL=y CONFIG_SUN50I_DE2_BUS=y CONFIG_SUNXI_RSB=y # CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set @@ -1500,7 +1504,6 @@ CONFIG_SCSI_PROC_FS=y CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y @@ -1527,7 +1530,9 @@ CONFIG_SCSI_LOWLEVEL=y # end of SCSI device support CONFIG_ATA=y +CONFIG_SATA_HOST=y CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y CONFIG_SATA_PMP=y # @@ -1597,7 +1602,8 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set CONFIG_DUMMY=m -# CONFIG_WIREGUARD is not set +CONFIG_WIREGUARD=y +# CONFIG_WIREGUARD_DEBUG is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_TEAM is not set CONFIG_MACVLAN=m @@ -1607,6 +1613,7 @@ CONFIG_IPVLAN=m # CONFIG_IPVTAP is not set CONFIG_VXLAN=m # CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set # CONFIG_GTP is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -1648,7 +1655,6 @@ CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HIX5HD2_GMAC is not set # CONFIG_HISI_FEMAC is not set # CONFIG_HIP04_ETH is not set -# CONFIG_HNS is not set # CONFIG_HNS_DSAF is not set # CONFIG_HNS_ENET is not set # CONFIG_NET_VENDOR_HUAWEI is not set @@ -1698,8 +1704,11 @@ CONFIG_MDIO_BUS_MUX=y # CONFIG_MDIO_BUS_MUX_MMIOREG is not set # CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set # CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_IPQ8064 is not set # CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_MVUSB is not set CONFIG_MDIO_SUN4I=y +CONFIG_MDIO_XPCS=y CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y @@ -2090,13 +2099,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -# CONFIG_NULL_TTY is not set CONFIG_LDISC_AUTOLOAD=y -CONFIG_DEVMEM=y -CONFIG_DEVKMEM=y # # Serial drivers @@ -2141,15 +2144,22 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_SPRD is not set # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_TTY_PRINTK is not set -# CONFIG_HVC_DCC is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set @@ -2250,6 +2260,11 @@ CONFIG_SPI_SUN6I=y # CONFIG_SPI_XILINX is not set # CONFIG_SPI_ZYNQMP_GQSPI is not set +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + # # SPI Protocol Masters # @@ -2281,6 +2296,7 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support @@ -2446,6 +2462,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DRIVETEMP is not set @@ -2661,6 +2678,7 @@ CONFIG_MFD_AXP20X_RSB=y # CONFIG_MFD_HI6421_PMIC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set @@ -2748,7 +2766,6 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ANATOP is not set CONFIG_REGULATOR_AXP20X=y # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -2768,7 +2785,9 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set # CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MP5416 is not set # CONFIG_REGULATOR_MP8859 is not set +# CONFIG_REGULATOR_MP886X is not set # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PFUZE100 is not set @@ -2887,7 +2906,6 @@ CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_PVRUSB2_DVB=y # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_USBVISION=m CONFIG_VIDEO_STK1160_COMMON=m CONFIG_VIDEO_STK1160=m CONFIG_VIDEO_GO7007=m @@ -2969,6 +2987,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_SH_VEU is not set CONFIG_VIDEO_SUN8I_DEINTERLACE=m +CONFIG_VIDEO_SUN8I_ROTATE=m # CONFIG_V4L_TEST_DRIVERS is not set # CONFIG_DVB_PLATFORM_DRIVERS is not set # CONFIG_CEC_PLATFORM_DRIVERS is not set @@ -3084,6 +3103,7 @@ CONFIG_VIDEO_THS8200=m # # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set @@ -3434,11 +3454,6 @@ CONFIG_DRM_SCHED=m # CONFIG_DRM_KOMEDA is not set # end of ARM devices -# -# ACP (Audio CoProcessor) Configuration -# -# end of ACP (Audio CoProcessor) Configuration - # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set # CONFIG_DRM_EXYNOS is not set @@ -3472,6 +3487,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set @@ -3485,19 +3501,23 @@ CONFIG_DRM_PANEL_BRIDGE=y # Display Interface Bridges # # CONFIG_DRM_CDNS_DSI is not set -# CONFIG_DRM_DUMB_VGA_DAC is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set # CONFIG_DRM_NXP_PTN3460 is not set # CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_PARADE_PS8640 is not set # CONFIG_DRM_SIL_SII8620 is not set # CONFIG_DRM_SII902X is not set # CONFIG_DRM_SII9234 is not set +CONFIG_DRM_SIMPLE_BRIDGE=m # CONFIG_DRM_THINE_THC63LVD1024 is not set # CONFIG_DRM_TOSHIBA_TC358764 is not set # CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set # CONFIG_DRM_I2C_ADV7511 is not set @@ -3515,6 +3535,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_TINYDRM_HX8357D is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set +# CONFIG_TINYDRM_ILI9486 is not set # CONFIG_TINYDRM_MI0283QT is not set # CONFIG_TINYDRM_REPAPER is not set # CONFIG_TINYDRM_ST7586 is not set @@ -3524,6 +3545,7 @@ CONFIG_DRM_DW_HDMI_CEC=y CONFIG_DRM_LIMA=m # CONFIG_DRM_PANFROST is not set # CONFIG_DRM_MCDE is not set +# CONFIG_DRM_TIDSS is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3635,6 +3657,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set # @@ -3782,6 +3805,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set # CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set # CONFIG_SND_SOC_TS3A227E is not set # CONFIG_SND_SOC_TSCS42XX is not set # CONFIG_SND_SOC_TSCS454 is not set @@ -3866,6 +3890,7 @@ CONFIG_DRAGONRISE_FF=y CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +CONFIG_HID_GLORIOUS=m # CONFIG_HID_HOLTEK is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set @@ -3933,6 +3958,7 @@ CONFIG_HID_XINMO=m CONFIG_HID_ZYDACRON=m # CONFIG_HID_SENSOR_HUB is not set # CONFIG_HID_ALPS is not set +# CONFIG_HID_MCP2221 is not set # end of Special HID drivers # @@ -4123,6 +4149,7 @@ CONFIG_USB_SERIAL=m # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set @@ -4170,10 +4197,34 @@ CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 # CONFIG_USB_BDC_UDC is not set # CONFIG_USB_NET2272 is not set # CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_MAX3420_UDC is not set # CONFIG_USB_DUMMY_HCD is not set # end of USB Peripheral Controller # CONFIG_USB_CONFIGFS is not set + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_RAW_GADGET is not set +# end of USB Gadget precomposed configurations + # CONFIG_TYPEC is not set # CONFIG_USB_ROLE_SWITCH is not set CONFIG_MMC=y @@ -4197,6 +4248,7 @@ CONFIG_MMC_BLOCK_MINORS=8 # CONFIG_MMC_USDHI6ROL0 is not set CONFIG_MMC_SUNXI=y # CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_HSQ is not set # CONFIG_MMC_MTK is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y @@ -4380,7 +4432,6 @@ CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_SUNXI=y # CONFIG_RTC_DRV_CADENCE is not set # CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_SNVS is not set # CONFIG_RTC_DRV_R7301 is not set # @@ -4420,6 +4471,7 @@ CONFIG_DMA_SUN6I=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set # CONFIG_DMABUF_SELFTESTS is not set CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_HEAPS_SYSTEM=y @@ -4430,6 +4482,9 @@ CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_UIO is not set # CONFIG_VIRT_DRIVERS is not set # CONFIG_VIRTIO_MENU is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_DPN=y +# CONFIG_VHOST_MENU is not set # # Microsoft Hyper-V guest support @@ -4461,7 +4516,6 @@ CONFIG_STAGING=y # Analog to digital converters # # CONFIG_AD7816 is not set -# CONFIG_AD7192 is not set # CONFIG_AD7280 is not set # end of Analog to digital converters @@ -4517,6 +4571,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # # soc_camera sensor drivers # +CONFIG_VIDEO_USBVISION=m # # Android @@ -4531,7 +4586,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_FB_TFT is not set # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set -# CONFIG_MOST is not set # CONFIG_KS7010 is not set # CONFIG_PI433 is not set @@ -4542,9 +4596,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set -# CONFIG_USB_WUSB_CBAF is not set -# CONFIG_UWB is not set -# CONFIG_STAGING_EXFAT_FS is not set # CONFIG_WFX is not set # CONFIG_GOLDFISH is not set # CONFIG_MFD_CROS_EC is not set @@ -4746,6 +4797,7 @@ CONFIG_IIO_SW_TRIGGER=y # # CONFIG_AD7091R5 is not set # CONFIG_AD7124 is not set +# CONFIG_AD7192 is not set # CONFIG_AD7266 is not set # CONFIG_AD7291 is not set # CONFIG_AD7292 is not set @@ -4811,6 +4863,7 @@ CONFIG_SUN4I_GPADC=y # Amplifiers # # CONFIG_AD8366 is not set +# CONFIG_HMC425 is not set # end of Amplifiers # @@ -4850,19 +4903,20 @@ CONFIG_SUN4I_GPADC=y # CONFIG_AD5593R is not set # CONFIG_AD5504 is not set # CONFIG_AD5624R_SPI is not set -# CONFIG_LTC1660 is not set -# CONFIG_LTC2632 is not set # CONFIG_AD5686_SPI is not set # CONFIG_AD5696_I2C is not set # CONFIG_AD5755 is not set # CONFIG_AD5758 is not set # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set +# CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set # CONFIG_DS4424 is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set # CONFIG_M62332 is not set # CONFIG_MAX517 is not set # CONFIG_MAX5821 is not set @@ -4960,6 +5014,7 @@ CONFIG_SUN4I_GPADC=y # # CONFIG_ADJD_S311 is not set # CONFIG_ADUX1020 is not set +# CONFIG_AL3010 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set @@ -4970,6 +5025,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_CM3323 is not set # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set +# CONFIG_GP2AP002 is not set # CONFIG_GP2AP020A00F is not set # CONFIG_SENSORS_ISL29018 is not set # CONFIG_SENSORS_ISL29028 is not set @@ -5030,6 +5086,11 @@ CONFIG_SUN4I_GPADC=y # # end of Inclinometer sensors +# +# Linear and angular position sensors +# +# end of Linear and angular position sensors + # # Digital potentiometers # @@ -5059,6 +5120,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_DLHL60D is not set # CONFIG_DPS310 is not set # CONFIG_HP03 is not set +# CONFIG_ICP10100 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set # CONFIG_MPL3115 is not set @@ -5113,6 +5175,7 @@ CONFIG_SUN4I_GPADC=y CONFIG_PWM=y CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SUN4I=y @@ -5145,7 +5208,7 @@ CONFIG_PHY_SUN6I_MIPI_DPHY=y CONFIG_PHY_SUN9I_USB=y CONFIG_PHY_SUN50I_USB3=y # CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set @@ -5197,6 +5260,7 @@ CONFIG_PM_OPP=y # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set +# CONFIG_MOST is not set # end of Device Drivers # @@ -5251,6 +5315,7 @@ CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_ZSTD=y CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -5290,7 +5355,7 @@ CONFIG_UDF_FS=y # end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y # CONFIG_MSDOS_FS is not set @@ -5298,8 +5363,9 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set -# end of DOS/FAT/NT Filesystems +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -5636,13 +5702,17 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m -# CONFIG_CRYPTO_LIB_BLAKE2S is not set -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_BLAKE2S=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y CONFIG_CRYPTO_LIB_SHA256=m CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ALLWINNER=y @@ -5713,7 +5783,7 @@ CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=y CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_COMPRESS=m +CONFIG_ZSTD_COMPRESS=y CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y @@ -5798,7 +5868,6 @@ CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set -CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set @@ -5810,11 +5879,11 @@ CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y # end of Generic Kernel Debugging Instruments CONFIG_DEBUG_KERNEL=y @@ -5856,6 +5925,7 @@ CONFIG_PANIC_TIMEOUT=0 # CONFIG_SOFTLOCKUP_DETECTOR is not set # CONFIG_DETECT_HUNG_TASK is not set # CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs # @@ -5956,6 +6026,7 @@ CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_SORT is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set diff --git a/projects/Allwinner/patches/linux/0001-backport-from-5.7.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.7.patch deleted file mode 100644 index 27d2b126d1..0000000000 --- a/projects/Allwinner/patches/linux/0001-backport-from-5.7.patch +++ /dev/null @@ -1,704 +0,0 @@ -From 3abe422fdc65ba08054659b0d27c71e24346021d Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 23 Feb 2020 11:40:19 +0100 -Subject: [PATCH] arm64: dts: sun50i-h5-orange-pi-pc2: Add CPUX voltage - regulator - -Orange Pi PC2 features sy8106a regulator just like Orange Pi PC. - -Signed-off-by: Ondrej Jirman -Reviewed-by: Samuel Holland -Signed-off-by: Maxime Ripard ---- - .../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 20 +++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -index c4f89c312f42..7d7aad18f078 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -@@ -94,6 +94,10 @@ &codec { - status = "okay"; - }; - -+&cpu0 { -+ cpu-supply = <®_vdd_cpux>; -+}; -+ - &de { - status = "okay"; - }; -@@ -169,6 +173,22 @@ &ohci3 { - status = "okay"; - }; - -+&r_i2c { -+ status = "okay"; -+ -+ reg_vdd_cpux: regulator@65 { -+ compatible = "silergy,sy8106a"; -+ reg = <0x65>; -+ regulator-name = "vdd-cpux"; -+ silergy,fixed-microvolt = <1100000>; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-ramp-delay = <200>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ - &spi0 { - status = "okay"; - --- -2.25.1 - -From 30bd02bd634f4a483e965fb41a076e47ea9681ef Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Thu, 16 Jan 2020 23:11:46 +0000 -Subject: [PATCH] arm64: dts: sun50i: H6: Add SPI controllers nodes and - pinmuxes - -The Allwinner H6 SoC contains two SPI controllers similar to the H3/A64, -but with the added capability of 3-wire and 4-wire operation modes. -For now the driver does not support those, but the SPI registers are -fully backwards-compatible, just adding bits and registers which were -formerly reserved. So we can use the existing driver in "legacy" SPI -modes, for instance to access the SPI NOR flash soldered on the PineH64 -board. -We use an H6 specific compatible string in addition to the existing H3 -string, so when the driver later gains QSPI support, it should work -automatically without any DT changes. - -Tested by accessing the SPI flash on a Pine H64 board (SPI0), also -connecting another SPI flash to the SPI1 header pins. - -Signed-off-by: Andre Przywara -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 55 ++++++++++++++++++++ - 1 file changed, 55 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 3329283e38ab..41b58ffa8596 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -338,6 +338,31 @@ mmc2_pins: mmc2-pins { - bias-pull-up; - }; - -+ /omit-if-no-ref/ -+ spi0_pins: spi0-pins { -+ pins = "PC0", "PC2", "PC3"; -+ function = "spi0"; -+ }; -+ -+ /* pin shared with MMC2-CMD (eMMC) */ -+ /omit-if-no-ref/ -+ spi0_cs_pin: spi0-cs-pin { -+ pins = "PC5"; -+ function = "spi0"; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1_pins: spi1-pins { -+ pins = "PH4", "PH5", "PH6"; -+ function = "spi1"; -+ }; -+ -+ /omit-if-no-ref/ -+ spi1_cs_pin: spi1-cs-pin { -+ pins = "PH3"; -+ function = "spi1"; -+ }; -+ - spdif_tx_pin: spdif-tx-pin { - pins = "PH7"; - function = "spdif"; -@@ -504,6 +529,36 @@ i2c2: i2c@5002800 { - #size-cells = <0>; - }; - -+ spi0: spi@5010000 { -+ compatible = "allwinner,sun50i-h6-spi", -+ "allwinner,sun8i-h3-spi"; -+ reg = <0x05010000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; -+ clock-names = "ahb", "mod"; -+ dmas = <&dma 22>, <&dma 22>; -+ dma-names = "rx", "tx"; -+ resets = <&ccu RST_BUS_SPI0>; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ spi1: spi@5011000 { -+ compatible = "allwinner,sun50i-h6-spi", -+ "allwinner,sun8i-h3-spi"; -+ reg = <0x05011000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; -+ clock-names = "ahb", "mod"; -+ dmas = <&dma 23>, <&dma 23>; -+ dma-names = "rx", "tx"; -+ resets = <&ccu RST_BUS_SPI1>; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ - emac: ethernet@5020000 { - compatible = "allwinner,sun50i-h6-emac", - "allwinner,sun50i-a64-emac"; --- -2.26.0 - -From e757bdd01780d0ea3e6774247b735caf2d1a9e92 Mon Sep 17 00:00:00 2001 -From: Andre Przywara -Date: Thu, 16 Jan 2020 23:11:47 +0000 -Subject: [PATCH] arm64: dts: allwinner: h6: Pine H64: Add SPI flash node - -The Pine H64 board comes with SPI flash soldered on the board, connected -to the SPI0 pins (so it can also boot from there). - -Add the required SPI flash DT node to describe this. - -Unfortunately the SPI CS0 pin collides with the eMMC CMD pin, so we can't -use both eMMC and SPI flash at the same time (the first to claim the pin -would win, the other's probe routine would then fail). - -To avoid losing the more useful eMMC device by chance, mark the SPI -device as "disabled" for now. A user or some U-Boot code could fix this -up if needed, for instance if no eMMC has been detected (it's socketed). - -Signed-off-by: Andre Przywara -Signed-off-by: Maxime Ripard ---- - .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -index d1c2aa5b3a20..3c9dd0d69754 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -@@ -14,6 +14,7 @@ / { - aliases { - ethernet0 = &emac; - serial0 = &uart0; -+ spi0 = &spi0; - }; - - chosen { -@@ -278,6 +279,24 @@ &r_pio { - vcc-pm-supply = <®_aldo1>; - }; - -+/* -+ * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI -+ * flash and eMMC at the same time, as one of them would fail probing. -+ * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can -+ * fix this up in no eMMC is connected. -+ */ -+&spi0 { -+ pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ -+ flash@0 { -+ compatible = "winbond,w25q128", "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <4000000>; -+ }; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; --- -2.26.0 - -From ec98a87509f40324807dc179a7e3163d40709eba Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 8 Mar 2020 14:58:48 +0100 -Subject: [PATCH] rtc: sun6i: Make external 32k oscillator optional - -Some boards, like OrangePi PC2 (H5), OrangePi Plus 2E (H3) and Tanix TX6 -(H6) don't have external 32kHz oscillator. Till H6, it didn't really -matter if external oscillator was enabled because HW detected error and -fall back to internal one. H6 has same functionality but it's the first -SoC which have "auto switch bypass" bit documented and always enabled in -driver. This prevents RTC to work correctly if external crystal is not -present on board. There are other side effects - all peripherals which -depends on this clock also don't work (HDMI CEC for example). - -Make clocks property optional. If it is present, select external -oscillator. If not, stay on internal. - -Signed-off-by: Jernej Skrabec -Acked-by: Maxime Ripard -Link: https://lore.kernel.org/r/20200308135849.106333-2-jernej.skrabec@siol.net -Signed-off-by: Alexandre Belloni ---- - drivers/rtc/rtc-sun6i.c | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - -diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c -index 852f5f3b3592..415a20a936e4 100644 ---- a/drivers/rtc/rtc-sun6i.c -+++ b/drivers/rtc/rtc-sun6i.c -@@ -250,19 +250,17 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, - writel(reg, rtc->base + SUN6I_LOSC_CTRL); - } - -- /* Switch to the external, more precise, oscillator */ -- reg |= SUN6I_LOSC_CTRL_EXT_OSC; -- if (rtc->data->has_losc_en) -- reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; -+ /* Switch to the external, more precise, oscillator, if present */ -+ if (of_get_property(node, "clocks", NULL)) { -+ reg |= SUN6I_LOSC_CTRL_EXT_OSC; -+ if (rtc->data->has_losc_en) -+ reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; -+ } - writel(reg, rtc->base + SUN6I_LOSC_CTRL); - - /* Yes, I know, this is ugly. */ - sun6i_rtc = rtc; - -- /* Deal with old DTs */ -- if (!of_get_property(node, "clocks", NULL)) -- goto err; -- - /* Only read IOSC name from device tree if it is exported */ - if (rtc->data->export_iosc) - of_property_read_string_index(node, "clock-output-names", 2, -@@ -279,11 +277,13 @@ static void __init sun6i_rtc_clk_init(struct device_node *node, - } - - parents[0] = clk_hw_get_name(rtc->int_osc); -+ /* If there is no external oscillator, this will be NULL and ... */ - parents[1] = of_clk_get_parent_name(node, 0); - - rtc->hw.init = &init; - - init.parent_names = parents; -+ /* ... number of clock parents will be 1. */ - init.num_parents = of_clk_get_parent_count(node) + 1; - of_property_read_string_index(node, "clock-output-names", 0, - &init.name); --- -2.26.0 - -From 32507b8681198c987fad8ac66e55ad4e15dfae4a Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 8 Mar 2020 14:58:49 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: Move ext. oscillator to board DTs - -It turns out that not all H6 boards have external 32kHz oscillator. -Currently the only one known such H6 board is Tanix TX6. - -Move external oscillator node from common H6 dtsi to board specific dts -files where present. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - .../boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 11 +++++++++++ - .../arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 11 +++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 11 +++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 11 +++++++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 -------- - 5 files changed, 44 insertions(+), 8 deletions(-) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index df6d872c34e2..8f09d209359b 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -32,6 +32,13 @@ hdmi_con_in: endpoint { - }; - }; - -+ ext_osc32k: ext_osc32k_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "ext_osc32k"; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -275,6 +282,10 @@ &r_pio { - vcc-pm-supply = <®_aldo1>; - }; - -+&rtc { -+ clocks = <&ext_osc32k>; -+}; -+ - &spdif { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index 1e0abd9d047f..47f579610dcc 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -32,6 +32,13 @@ hdmi_con_in: endpoint { - }; - }; - -+ ext_osc32k: ext_osc32k_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "ext_osc32k"; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -285,6 +292,10 @@ &r_ir { - status = "okay"; - }; - -+&rtc { -+ clocks = <&ext_osc32k>; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index 37f4c57597d4..37fc3f3697f7 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -20,6 +20,13 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - -+ ext_osc32k: ext_osc32k_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "ext_osc32k"; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -197,6 +204,10 @@ &r_ir { - status = "okay"; - }; - -+&rtc { -+ clocks = <&ext_osc32k>; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -index 3c9dd0d69754..b0642d841933 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -@@ -21,6 +21,13 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - -+ ext_osc32k: ext_osc32k_clk { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "ext_osc32k"; -+ }; -+ - hdmi_connector: connector { - compatible = "hdmi-connector"; - type = "a"; -@@ -279,6 +286,10 @@ &r_pio { - vcc-pm-supply = <®_aldo1>; - }; - -+&rtc { -+ clocks = <&ext_osc32k>; -+}; -+ - /* - * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI - * flash and eMMC at the same time, as one of them would fail probing. -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 967249e58811..b9ab7d8fa8af 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -62,13 +62,6 @@ osc24M: osc24M_clk { - clock-output-names = "osc24M"; - }; - -- ext_osc32k: ext_osc32k_clk { -- #clock-cells = <0>; -- compatible = "fixed-clock"; -- clock-frequency = <32768>; -- clock-output-names = "ext_osc32k"; -- }; -- - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , -@@ -854,7 +847,6 @@ rtc: rtc@7000000 { - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; -- clocks = <&ext_osc32k>; - #clock-cells = <1>; - }; - --- -2.26.0 - -From 221a690420fdad808eb0b39eebb19d4eda95568c Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 10 Feb 2020 18:40:07 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: orangepi-3: Add eMMC node - -OrangePi 3 can optionally have 8 GiB eMMC (soldered on board). Because -those pins are dedicated to eMMC exclusively, node can be added for both -variants (with and without eMMC). Kernel will then scan bus for presence -of eMMC and act accordingly. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index c311eee52a35..1e0abd9d047f 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -144,6 +144,15 @@ brcm: sdio-wifi@1 { - }; - }; - -+&mmc2 { -+ vmmc-supply = <®_cldo1>; -+ vqmmc-supply = <®_bldo2>; -+ cap-mmc-hw-reset; -+ non-removable; -+ bus-width = <8>; -+ status = "okay"; -+}; -+ - &ohci0 { - status = "okay"; - }; --- -2.26.0 - -From 7ee32a17e0d65fbaa55b032f3bb52232b09fb447 Mon Sep 17 00:00:00 2001 -From: Marcus Cooper -Date: Sun, 8 Mar 2020 17:48:39 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: orangepi-one-plus: Enable ethernet - -OrangePi One Plus has gigabit ethernet. Add nodes for it. - -Signed-off-by: Marcus Cooper -[patch split and commit message] -Signed-off-by: Jernej Skrabec -Reviewed-by: Christopher Obbard -Tested-by: Christopher Obbard -Signed-off-by: Maxime Ripard ---- - .../allwinner/sun50i-h6-orangepi-one-plus.dts | 33 +++++++++++++++++++ - 1 file changed, 33 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -index 83aab7368889..fceb298bfd53 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -@@ -7,4 +7,37 @@ - / { - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; -+ -+ aliases { -+ ethernet0 = &emac; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ -+ vin-supply = <®_aldo2>; -+ }; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ext_rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-supply = <®_gmac_3v3>; -+ allwinner,rx-delay-ps = <200>; -+ allwinner,tx-delay-ps = <200>; -+ status = "okay"; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; - }; --- -2.26.0 - -From 2345b744f4f911713dcada64ea16a614f5be9328 Mon Sep 17 00:00:00 2001 -From: Marcus Cooper -Date: Sun, 8 Mar 2020 17:48:40 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: orangepi: Enable HDMI - -Both, OrangePi One Plus and OrangePi Lite 2 have HDMI output. Enable it -in common DTSI. - -Signed-off-by: Marcus Cooper -[patch split and commit message] -Signed-off-by: Jernej Skrabec -Reviewed-by: Christopher Obbard -Tested-by: Christopher Obbard -Signed-off-by: Maxime Ripard ---- - .../dts/allwinner/sun50i-h6-orangepi.dtsi | 26 +++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index 37fc3f3697f7..9287976c4a50 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -20,6 +20,18 @@ chosen { - stdout-path = "serial0:115200n8"; - }; - -+ connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; -@@ -52,6 +64,10 @@ reg_vcc5v: vcc5v { - }; - }; - -+&de { -+ status = "okay"; -+}; -+ - &ehci0 { - status = "okay"; - }; -@@ -65,6 +81,16 @@ &gpu { - status = "okay"; - }; - -+&hdmi { -+ status = "okay"; -+}; -+ -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; -+}; -+ - &mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; --- -2.26.0 - -From 7ad9f3d0cb2f2b886c068f99e791bd41ceb0677a Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Mon, 24 Feb 2020 17:54:46 +0100 -Subject: [PATCH] ARM: dts: sun8i-h3: Add thermal trip points/cooling maps -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This enables passive cooling by down-regulating CPU voltage -and frequency. - -For trip points, I used a slightly lowered values from the BSP -code. The critical temperature of 110°C from BSP code seemed -like a lot, so I rounded it off to 100°C. - -The critical trip point value is 30°C above the maximum recommended -ambient temperature (70°C) for the SoC from the datasheet, so there's -some headroom even at such a high ambient temperature. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sun8i-h3.dtsi | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi -index 20217e2ca4d3..e83aa6866e7e 100644 ---- a/arch/arm/boot/dts/sun8i-h3.dtsi -+++ b/arch/arm/boot/dts/sun8i-h3.dtsi -@@ -41,6 +41,7 @@ - */ - - #include "sunxi-h3-h5.dtsi" -+#include - - / { - cpu0_opp_table: opp_table0 { -@@ -227,6 +228,30 @@ cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; -+ -+ trips { -+ cpu_hot_trip: cpu-hot { -+ temperature = <80000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_very_hot_trip: cpu-very-hot { -+ temperature = <100000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ cpu-hot-limit { -+ trip = <&cpu_hot_trip>; -+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; - }; - }; - }; --- -2.26.0 - diff --git a/projects/Allwinner/patches/linux/0001-backport-from-5.8.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.8.patch new file mode 100644 index 0000000000..28c294e667 --- /dev/null +++ b/projects/Allwinner/patches/linux/0001-backport-from-5.8.patch @@ -0,0 +1,1244 @@ +From b928fd4674fe339374aa0aead9a82d9d6e476f88 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 13 Apr 2020 08:24:31 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: orangepi: Add gpio power supply + +OrangePi Lite2 and One Plus have GPIO ports powered by same power +supplies. Add them in common DT. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index 9287976c4a50..f1be3dd558ca 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -106,6 +106,12 @@ &ohci3 { + status = "okay"; + }; + ++&pio { ++ vcc-pc-supply = <®_bldo2>; ++ vcc-pd-supply = <®_cldo1>; ++ vcc-pg-supply = <®_aldo1>; ++}; ++ + &r_i2c { + status = "okay"; + +@@ -230,6 +236,10 @@ &r_ir { + status = "okay"; + }; + ++&r_pio { ++ vcc-pm-supply = <®_bldo3>; ++}; ++ + &rtc { + clocks = <&ext_osc32k>; + }; +-- +2.26.2 + +From 27c9f2a0c5125727f0a9f7a19366d044b841e873 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 13 Apr 2020 08:24:32 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: orangepi: Disable OTG mode + +As can be seen from OrangePi Lite 2 and One Plus schematics, VBUS pin on +USB OTG port is directly connected to 5 V power supply. This mean that +OTG port can safely operate only in host mode, even though these two +boards have ID pin connected. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index f1be3dd558ca..ebc120a9232f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -251,7 +251,12 @@ &uart0 { + }; + + &usb2otg { +- dr_mode = "otg"; ++ /* ++ * OrangePi Lite 2 and One Plus, where this DT is used, don't ++ * have a controllable VBUS even though they do have an ID pin. ++ * Using it as anything but a USB host is unsafe. ++ */ ++ dr_mode = "host"; + status = "okay"; + }; + +-- +2.26.2 + +From 3d478d211b8e40deb609594f0676be205e8d89c1 Mon Sep 17 00:00:00 2001 +From: Sebastian Meyer +Date: Mon, 13 Apr 2020 08:24:33 +0200 +Subject: [PATCH] arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI combo + module + +OrangePi Lite2 has AP6255 BT+WIFI combo chip. Add support for it. + +Signed-off-by: Sebastian Meyer +[merged BT and WIFI patches and updated commit message] +Signed-off-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + .../allwinner/sun50i-h6-orangepi-lite2.dts | 65 +++++++++++++++++++ + 1 file changed, 65 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +index e7ca75c0d0f7..e8770858b5d0 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +@@ -6,4 +6,69 @@ + / { + model = "OrangePi Lite2"; + compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; ++ ++ aliases { ++ serial1 = &uart1; /* BT-UART */ ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rtc 1>; ++ clock-names = "ext_clock"; ++ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ ++ post-power-on-delay-ms = <200>; ++ }; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_cldo2>; ++ vqmmc-supply = <®_bldo3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcm: sdio-wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++®_cldo2 { ++ /* ++ * This regulator is connected with CLDO3. ++ * Before the kernel can support synchronized ++ * enable of coupled regulators, keep them ++ * both always on as a ugly hack. ++ */ ++ regulator-always-on; ++}; ++ ++®_cldo3 { ++ /* ++ * This regulator is connected with CLDO2. ++ * See the comments for CLDO2. ++ */ ++ regulator-always-on; ++}; ++ ++/* There's the BT part of the AP6255 connected to that UART */ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rtc 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ ++ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ ++ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ ++ max-speed = <1500000>; ++ }; + }; +-- +2.26.2 + +From 8a3a9535189d908f7e325238c9f09069d4fe9b8f Mon Sep 17 00:00:00 2001 +From: Yangtao Li +Date: Mon, 20 Apr 2020 15:00:13 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Add clock to CPU cores +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The ARM CPU cores are fed by the CPU clock from the CCU. Add a +reference to the clock for each CPU core, along with the clock +transition latency. + +Signed-off-by: Yangtao Li +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index a5ee68388bd3..370e77b86fe1 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -25,6 +25,8 @@ cpu0: cpu@0 { + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu1: cpu@1 { +@@ -32,6 +34,8 @@ cpu1: cpu@1 { + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu2: cpu@2 { +@@ -39,6 +43,8 @@ cpu2: cpu@2 { + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + cpu3: cpu@3 { +@@ -46,6 +52,8 @@ cpu3: cpu@3 { + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; ++ clocks = <&ccu CLK_CPUX>; ++ clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + +-- +2.26.2 + +From 9f8a93b742e99dd93ca888161909e7245f1c7269 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Mon, 20 Apr 2020 15:00:14 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Add thermal trip points/cooling + map +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This enables passive cooling by down-regulating CPU voltage +and frequency. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 28 ++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 370e77b86fe1..7cd10e4a5e2e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -27,6 +27,7 @@ cpu0: cpu@0 { + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu1: cpu@1 { +@@ -36,6 +37,7 @@ cpu1: cpu@1 { + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu2: cpu@2 { +@@ -45,6 +47,7 @@ cpu2: cpu@2 { + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + + cpu3: cpu@3 { +@@ -54,6 +57,7 @@ cpu3: cpu@3 { + enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ ++ #cooling-cells = <2>; + }; + }; + +@@ -964,6 +968,30 @@ cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; ++ ++ trips { ++ cpu_alert: cpu-alert { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu-crit { ++ temperature = <100000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; + }; + + gpu-thermal { +-- +2.26.2 + +From 905434e0b544ee220bcce6da16a6857c0274b8ba Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Mon, 20 Apr 2020 15:00:15 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Add CPU Operating Performance + Points table +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add an Operating Performance Points table for the CPU cores to +enable Dynamic Voltage & Frequency Scaling on the H6. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 117 ++++++++++++++++++ + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 + + 2 files changed, 121 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi +new file mode 100644 +index 000000000000..dcb789519797 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi +@@ -0,0 +1,117 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (C) 2020 Ondrej Jirman ++// Copyright (C) 2020 Clément Péron ++ ++/ { ++ cpu_opp_table: cpu-opp-table { ++ compatible = "allwinner,sun50i-h6-operating-points"; ++ nvmem-cells = <&cpu_speed_grade>; ++ opp-shared; ++ ++ opp@480000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <480000000>; ++ ++ opp-microvolt-speed0 = <880000>; ++ opp-microvolt-speed1 = <820000>; ++ opp-microvolt-speed2 = <820000>; ++ }; ++ ++ opp@720000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <720000000>; ++ ++ opp-microvolt-speed0 = <880000>; ++ opp-microvolt-speed1 = <820000>; ++ opp-microvolt-speed2 = <820000>; ++ }; ++ ++ opp@816000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <816000000>; ++ ++ opp-microvolt-speed0 = <880000>; ++ opp-microvolt-speed1 = <820000>; ++ opp-microvolt-speed2 = <820000>; ++ }; ++ ++ opp@888000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <888000000>; ++ ++ opp-microvolt-speed0 = <880000>; ++ opp-microvolt-speed1 = <820000>; ++ opp-microvolt-speed2 = <820000>; ++ }; ++ ++ opp@1080000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1080000000>; ++ ++ opp-microvolt-speed0 = <940000>; ++ opp-microvolt-speed1 = <880000>; ++ opp-microvolt-speed2 = <880000>; ++ }; ++ ++ opp@1320000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1320000000>; ++ ++ opp-microvolt-speed0 = <1000000>; ++ opp-microvolt-speed1 = <940000>; ++ opp-microvolt-speed2 = <940000>; ++ }; ++ ++ opp@1488000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1488000000>; ++ ++ opp-microvolt-speed0 = <1060000>; ++ opp-microvolt-speed1 = <1000000>; ++ opp-microvolt-speed2 = <1000000>; ++ }; ++ ++ opp@1608000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1608000000>; ++ ++ opp-microvolt-speed0 = <1090000>; ++ opp-microvolt-speed1 = <1030000>; ++ opp-microvolt-speed2 = <1030000>; ++ }; ++ ++ opp@1704000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1704000000>; ++ ++ opp-microvolt-speed0 = <1120000>; ++ opp-microvolt-speed1 = <1060000>; ++ opp-microvolt-speed2 = <1060000>; ++ }; ++ ++ opp@1800000000 { ++ clock-latency-ns = <244144>; /* 8 32k periods */ ++ opp-hz = /bits/ 64 <1800000000>; ++ ++ opp-microvolt-speed0 = <1160000>; ++ opp-microvolt-speed1 = <1100000>; ++ opp-microvolt-speed2 = <1100000>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu1 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu2 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; ++ ++&cpu3 { ++ operating-points-v2 = <&cpu_opp_table>; ++}; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 7cd10e4a5e2e..2e31632c6ca8 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -262,6 +262,10 @@ sid: efuse@3006000 { + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; + }; ++ ++ cpu_speed_grade: cpu-speed-grade@1c { ++ reg = <0x1c 0x4>; ++ }; + }; + + watchdog: watchdog@30090a0 { +-- +2.26.2 + +From 67533f873ad7e2a4af1a1ed47f03f501d6c770df Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Mon, 20 Apr 2020 15:00:17 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink + GS1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enable CPU opp tables for Beelink GS1. + +This needs to change the CPU regulator max voltage to fit +the OPP table. + +Also add the ramp-delay information to avoid any out of spec +running as the regulator is slower at reaching the voltage +requested compare to the PLL reaching the frequency. + +There is no such information for AXP805 but similar PMIC (AXP813) +has a DVM (Dynamic Voltage scaling Management) ramp rate equal +to 2500uV/us. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +index 8f09d209359b..3f7ceeb1a767 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +@@ -4,6 +4,7 @@ + /dts-v1/; + + #include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" + + #include + +@@ -77,6 +78,10 @@ spdif_out: spdif-out { + }; + }; + ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ + &de { + status = "okay"; + }; +@@ -234,7 +239,8 @@ reg_cldo3: cldo3 { + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; + }; + +@@ -242,6 +248,7 @@ reg_dcdcc: dcdcc { + regulator-enable-ramp-delay = <32000>; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-gpu"; + }; + +-- +2.26.2 + +From ebae33c3f6cee978f60ad48371258a03f9440691 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Mon, 20 Apr 2020 15:00:18 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Enable CPU opp tables for Orange + Pi 3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enable CPU opp tables for Orange Pi 3. + +This needs to change the CPU regulator max voltage to fit +the OPP table. + +Also add the ramp-delay information to avoid any out of spec +running as the regulator is slower at reaching the voltage +requested compare to the PLL reaching the frequency. + +There is no such information for AXP805 but similar PMIC (AXP813) +has a DVM (Dynamic Voltage scaling Management) ramp rate equal +to 2500uV/us. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +index 47f579610dcc..15c9dd8c4479 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +@@ -4,6 +4,7 @@ + /dts-v1/; + + #include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" + + #include + +@@ -257,6 +258,7 @@ reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1160000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; + }; + +@@ -264,6 +266,7 @@ reg_dcdcc: dcdcc { + regulator-enable-ramp-delay = <32000>; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-gpu"; + }; + +-- +2.26.2 + +From d8e2b7e11b50c332e03fae05a68d40a48d4646ed Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Mon, 20 Apr 2020 15:00:20 +0200 +Subject: [PATCH] arm64: dts: allwinner: Sort Pine H64 device-tree nodes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Pine H64 device-tree have some nodes not properly sorted. + +Fix this. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 34 +++++++++---------- + 1 file changed, 17 insertions(+), 17 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +index b0642d841933..63a785b534e1 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +@@ -80,6 +80,18 @@ reg_usb_vbus: vbus { + }; + }; + ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ + &emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; +@@ -91,17 +103,6 @@ &emac { + status = "okay"; + }; + +-&mdio { +- ext_rgmii_phy: ethernet-phy@1 { +- compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <1>; +- }; +-}; +- +-&de { +- status = "okay"; +-}; +- + &gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +@@ -117,12 +118,11 @@ hdmi_out_con: endpoint { + }; + }; + +-&ehci0 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; + }; + + &mmc0 { +-- +2.26.2 + +From fe79ea577be81e1e71642826ab00e676dc59c194 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Mon, 20 Apr 2020 15:00:21 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enable CPU and GPU opp tables for Pine H64. + +This needs to change the CPU regulator max voltage to fit +the OPP table. + +Also add the ramp-delay information to avoid any out of spec +running as the regulator is slower at reaching the voltage +requested compare to the PLL reaching the frequency. + +There is no such information for AXP805 but similar PMIC (AXP813) +has a DVM (Dynamic Voltage scaling Management) ramp rate equal +to 2500uV/us. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +index 63a785b534e1..af85b2074867 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +@@ -4,6 +4,7 @@ + /dts-v1/; + + #include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" + + #include + +@@ -80,6 +81,10 @@ reg_usb_vbus: vbus { + }; + }; + ++&cpu0 { ++ cpu-supply = <®_dcdca>; ++}; ++ + &de { + status = "okay"; + }; +@@ -238,7 +243,8 @@ reg_cldo3: cldo3 { + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; +- regulator-max-microvolt = <1080000>; ++ regulator-max-microvolt = <1160000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; + }; + +@@ -246,6 +252,7 @@ reg_dcdcc: dcdcc { + regulator-enable-ramp-delay = <32000>; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; ++ regulator-ramp-delay = <2500>; + regulator-name = "vdd-gpu"; + }; + +-- +2.26.2 + +From c83e24e7bf1cfa7486165f066f2bc1335703e1fd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Fri, 8 May 2020 21:10:34 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: add voltage range to OPP table +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some boards have a fixed regulator and can't reach the voltage set +by the OPP table. + +Add a range where the minimal voltage is the target and the maximal +voltage is 1.2V. + +Suggested-by: Ondřej Jirman +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 60 +++++++++---------- + 1 file changed, 30 insertions(+), 30 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi +index dcb789519797..1a5eddc5a40f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi +@@ -12,90 +12,90 @@ opp@480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + +- opp-microvolt-speed0 = <880000>; +- opp-microvolt-speed1 = <820000>; +- opp-microvolt-speed2 = <820000>; ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + +- opp-microvolt-speed0 = <880000>; +- opp-microvolt-speed1 = <820000>; +- opp-microvolt-speed2 = <820000>; ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + +- opp-microvolt-speed0 = <880000>; +- opp-microvolt-speed1 = <820000>; +- opp-microvolt-speed2 = <820000>; ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + +- opp-microvolt-speed0 = <880000>; +- opp-microvolt-speed1 = <820000>; +- opp-microvolt-speed2 = <820000>; ++ opp-microvolt-speed0 = <880000 880000 1200000>; ++ opp-microvolt-speed1 = <820000 820000 1200000>; ++ opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + +- opp-microvolt-speed0 = <940000>; +- opp-microvolt-speed1 = <880000>; +- opp-microvolt-speed2 = <880000>; ++ opp-microvolt-speed0 = <940000 940000 1200000>; ++ opp-microvolt-speed1 = <880000 880000 1200000>; ++ opp-microvolt-speed2 = <880000 880000 1200000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + +- opp-microvolt-speed0 = <1000000>; +- opp-microvolt-speed1 = <940000>; +- opp-microvolt-speed2 = <940000>; ++ opp-microvolt-speed0 = <1000000 1000000 1200000>; ++ opp-microvolt-speed1 = <940000 940000 1200000>; ++ opp-microvolt-speed2 = <940000 940000 1200000>; + }; + + opp@1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + +- opp-microvolt-speed0 = <1060000>; +- opp-microvolt-speed1 = <1000000>; +- opp-microvolt-speed2 = <1000000>; ++ opp-microvolt-speed0 = <1060000 1060000 1200000>; ++ opp-microvolt-speed1 = <1000000 1000000 1200000>; ++ opp-microvolt-speed2 = <1000000 1000000 1200000>; + }; + + opp@1608000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1608000000>; + +- opp-microvolt-speed0 = <1090000>; +- opp-microvolt-speed1 = <1030000>; +- opp-microvolt-speed2 = <1030000>; ++ opp-microvolt-speed0 = <1090000 1090000 1200000>; ++ opp-microvolt-speed1 = <1030000 1030000 1200000>; ++ opp-microvolt-speed2 = <1030000 1030000 1200000>; + }; + + opp@1704000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1704000000>; + +- opp-microvolt-speed0 = <1120000>; +- opp-microvolt-speed1 = <1060000>; +- opp-microvolt-speed2 = <1060000>; ++ opp-microvolt-speed0 = <1120000 1120000 1200000>; ++ opp-microvolt-speed1 = <1060000 1060000 1200000>; ++ opp-microvolt-speed2 = <1060000 1060000 1200000>; + }; + + opp@1800000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1800000000>; + +- opp-microvolt-speed0 = <1160000>; +- opp-microvolt-speed1 = <1100000>; +- opp-microvolt-speed2 = <1100000>; ++ opp-microvolt-speed0 = <1160000 1160000 1200000>; ++ opp-microvolt-speed1 = <1100000 1100000 1200000>; ++ opp-microvolt-speed2 = <1100000 1100000 1200000>; + }; + }; + }; +-- +2.26.2 + +From 5961bdf2dfe5d7fa9e9e6cc3cc67d02f122a46bd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Fri, 8 May 2020 21:10:35 +0200 +Subject: [PATCH] arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix + TX6 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Enable CPU opp tables for Tanix TX6. + +Also add the fixed regulator that provided vdd-cpu-gpu required for +CPU opp tables. + +This voltage has been found using a voltmeter and could be wrong. + +Tested-by: Jernej Škrabec +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + .../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +index 83e6cb0e59ce..be81330db14f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +@@ -4,6 +4,7 @@ + /dts-v1/; + + #include "sun50i-h6.dtsi" ++#include "sun50i-h6-cpu-opp.dtsi" + + #include + +@@ -37,6 +38,17 @@ reg_vcc3v3: vcc3v3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; ++ ++ reg_vdd_cpu_gpu: vdd-cpu-gpu { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd-cpu-gpu"; ++ regulator-min-microvolt = <1135000>; ++ regulator-max-microvolt = <1135000>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_vdd_cpu_gpu>; + }; + + &de { +@@ -56,6 +68,7 @@ &ehci3 { + }; + + &gpu { ++ mali-supply = <®_vdd_cpu_gpu>; + status = "okay"; + }; + +-- +2.26.2 + +From 6b633e3efbb45b574bdd803ebdddc8e010758a95 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Thu, 5 Mar 2020 00:25:10 +0100 +Subject: [PATCH] drm/bridge: dw-hdmi: do not force "none" scan mode + +Setting scan mode to "none" confuses some TVs like LG B8, which randomly +change overscan percentage over time. Digital outputs like HDMI and DVI, +handled by this controller, don't really need overscan, so we can always +set scan mode to underscan. Actually, this is exactly what +drm_hdmi_avi_infoframe_from_display_mode() already does, so we can just +remove offending line. + +Reviewed-by: Neil Armstrong +Acked-by: Laurent Pinchart +Signed-off-by: Jonas Karlman +[updated commit message] +Signed-off-by: Jernej Skrabec +Link: https://patchwork.freedesktop.org/patch/msgid/20200304232512.51616-3-jernej.skrabec@siol.net +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index f85c15ad8486..6e95bcbb2413 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1648,8 +1648,6 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + break; + } + +- frame.scan_mode = HDMI_SCAN_MODE_NONE; +- + /* + * The Designware IP uses a different byte format from standard + * AVI info frames, though generally the bits are in the correct +-- +2.26.2 + +From 86af379ebca2ef0b01d998a49e531cd495dcf9a3 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 5 Mar 2020 00:25:11 +0100 +Subject: [PATCH] drm/bridge: dw-hdmi: Add support for RGB limited range + +CEA 861 standard requestis that RGB quantization range is "limited" for +CEA modes. Support that by adding CSC matrix which downscales values. + +This allows proper color reproduction on TV and PC monitor at the same +time. In future, override property can be added, like "Broadcast RGB" +in i915 driver. + +Reviewed-by: Laurent Pinchart +Signed-off-by: Jernej Skrabec +Link: https://patchwork.freedesktop.org/patch/msgid/20200304232512.51616-4-jernej.skrabec@siol.net +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 63 +++++++++++++++++------ + 1 file changed, 46 insertions(+), 17 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 6e95bcbb2413..43c763ee8307 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -92,6 +92,12 @@ static const u16 csc_coeff_rgb_in_eitu709[3][4] = { + { 0x6756, 0x78ab, 0x2000, 0x0200 } + }; + ++static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { ++ { 0x1b7c, 0x0000, 0x0000, 0x0020 }, ++ { 0x0000, 0x1b7c, 0x0000, 0x0020 }, ++ { 0x0000, 0x0000, 0x1b7c, 0x0020 } ++}; ++ + struct hdmi_vmode { + bool mdataenablepolarity; + +@@ -109,6 +115,7 @@ struct hdmi_data_info { + unsigned int pix_repet_factor; + unsigned int hdcp_enable; + struct hdmi_vmode video_mode; ++ bool rgb_limited_range; + }; + + struct dw_hdmi_i2c { +@@ -956,7 +963,11 @@ static void hdmi_video_sample(struct dw_hdmi *hdmi) + + static int is_color_space_conversion(struct dw_hdmi *hdmi) + { +- return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; ++ return (hdmi->hdmi_data.enc_in_bus_format != ++ hdmi->hdmi_data.enc_out_bus_format) || ++ (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) && ++ hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) && ++ hdmi->hdmi_data.rgb_limited_range); + } + + static int is_color_space_decimation(struct dw_hdmi *hdmi) +@@ -986,25 +997,27 @@ static int is_color_space_interpolation(struct dw_hdmi *hdmi) + static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) + { + const u16 (*csc_coeff)[3][4] = &csc_coeff_default; ++ bool is_input_rgb, is_output_rgb; + unsigned i; + u32 csc_scale = 1; + +- if (is_color_space_conversion(hdmi)) { +- if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { +- if (hdmi->hdmi_data.enc_out_encoding == +- V4L2_YCBCR_ENC_601) +- csc_coeff = &csc_coeff_rgb_out_eitu601; +- else +- csc_coeff = &csc_coeff_rgb_out_eitu709; +- } else if (hdmi_bus_fmt_is_rgb( +- hdmi->hdmi_data.enc_in_bus_format)) { +- if (hdmi->hdmi_data.enc_out_encoding == +- V4L2_YCBCR_ENC_601) +- csc_coeff = &csc_coeff_rgb_in_eitu601; +- else +- csc_coeff = &csc_coeff_rgb_in_eitu709; +- csc_scale = 0; +- } ++ is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); ++ is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); ++ ++ if (!is_input_rgb && is_output_rgb) { ++ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) ++ csc_coeff = &csc_coeff_rgb_out_eitu601; ++ else ++ csc_coeff = &csc_coeff_rgb_out_eitu709; ++ } else if (is_input_rgb && !is_output_rgb) { ++ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) ++ csc_coeff = &csc_coeff_rgb_in_eitu601; ++ else ++ csc_coeff = &csc_coeff_rgb_in_eitu709; ++ csc_scale = 0; ++ } else if (is_input_rgb && is_output_rgb && ++ hdmi->hdmi_data.rgb_limited_range) { ++ csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; + } + + /* The CSC registers are sequential, alternating MSB then LSB */ +@@ -1614,6 +1627,18 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + drm_hdmi_avi_infoframe_from_display_mode(&frame, + &hdmi->connector, mode); + ++ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { ++ drm_hdmi_avi_infoframe_quant_range(&frame, &hdmi->connector, ++ mode, ++ hdmi->hdmi_data.rgb_limited_range ? ++ HDMI_QUANTIZATION_RANGE_LIMITED : ++ HDMI_QUANTIZATION_RANGE_FULL); ++ } else { ++ frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; ++ frame.ycc_quantization_range = ++ HDMI_YCC_QUANTIZATION_RANGE_LIMITED; ++ } ++ + if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) + frame.colorspace = HDMI_COLORSPACE_YUV444; + else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) +@@ -2111,6 +2136,10 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) + hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; + ++ hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && ++ drm_default_rgb_quant_range(mode) == ++ HDMI_QUANTIZATION_RANGE_LIMITED; ++ + hdmi->hdmi_data.pix_repet_factor = 0; + hdmi->hdmi_data.hdcp_enable = 0; + hdmi->hdmi_data.video_mode.mdataenablepolarity = true; +-- +2.26.2 + +From 0e8003076aca7b29c868e923e73f332cca12ed8b Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 5 Mar 2020 00:25:12 +0100 +Subject: [PATCH] drm/bridge: dw-hdmi: rework csc related functions + +is_color_space_conversion() is a misnomer. It checks not only if color +space conversion is needed, but also if format conversion is needed. +This is actually desired behaviour because result of this function +determines if CSC block should be enabled or not (CSC block can also do +format conversion). + +In order to clear misunderstandings, let's rework +is_color_space_conversion() to do exactly what is supposed to do and add +another function which will determine if CSC block must be enabled or +not. + +Reviewed-by: Laurent Pinchart +Signed-off-by: Jernej Skrabec +Link: https://patchwork.freedesktop.org/patch/msgid/20200304232512.51616-5-jernej.skrabec@siol.net +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 31 +++++++++++++++-------- + 1 file changed, 21 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 43c763ee8307..ec3b06433d98 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -963,11 +963,14 @@ static void hdmi_video_sample(struct dw_hdmi *hdmi) + + static int is_color_space_conversion(struct dw_hdmi *hdmi) + { +- return (hdmi->hdmi_data.enc_in_bus_format != +- hdmi->hdmi_data.enc_out_bus_format) || +- (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) && +- hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) && +- hdmi->hdmi_data.rgb_limited_range); ++ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; ++ bool is_input_rgb, is_output_rgb; ++ ++ is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); ++ is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); ++ ++ return (is_input_rgb != is_output_rgb) || ++ (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); + } + + static int is_color_space_decimation(struct dw_hdmi *hdmi) +@@ -994,6 +997,13 @@ static int is_color_space_interpolation(struct dw_hdmi *hdmi) + return 0; + } + ++static bool is_csc_needed(struct dw_hdmi *hdmi) ++{ ++ return is_color_space_conversion(hdmi) || ++ is_color_space_decimation(hdmi) || ++ is_color_space_interpolation(hdmi); ++} ++ + static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) + { + const u16 (*csc_coeff)[3][4] = &csc_coeff_default; +@@ -2027,18 +2037,19 @@ static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) + hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); + + /* Enable csc path */ +- if (is_color_space_conversion(hdmi)) { ++ if (is_csc_needed(hdmi)) { + hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; + hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); +- } + +- /* Enable color space conversion if needed */ +- if (is_color_space_conversion(hdmi)) + hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, + HDMI_MC_FLOWCTRL); +- else ++ } else { ++ hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; ++ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); ++ + hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, + HDMI_MC_FLOWCTRL); ++ } + } + + /* Workaround to clear the overflow condition */ +-- +2.26.2 + diff --git a/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch b/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch index 35c4dcefa4..ebc1d39664 100644 --- a/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch +++ b/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch @@ -555,172 +555,3 @@ index dff27934287c..c922639e25eb 100644 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); -From cb6130315f4ae856051725b2de4e208ed90eb740 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 8 Dec 2019 23:41:44 +0000 -Subject: [PATCH v2 2/4] drm/bridge: dw-hdmi: do not force "none" scan mode - -Setting scan mode to "none" confuses some TVs like LG B8, which randomly -change overscan percentage over time. Digital outputs like HDMI and DVI, -handled by this controller, don't really need overscan, so we can always -set scan mode to underscan. Actually, this is exactly what -drm_hdmi_avi_infoframe_from_display_mode() already does, so we can just -remove offending line. - -Reviewed-by: Neil Armstrong -Acked-by: Laurent Pinchart -Signed-off-by: Jonas Karlman -[updated commit message] -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 24965e53d351..de2c7ec887c8 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1654,8 +1654,6 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) - HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; - } - -- frame.scan_mode = HDMI_SCAN_MODE_NONE; -- - /* - * The Designware IP uses a different byte format from standard - * AVI info frames, though generally the bits are in the correct --- -2.25.1 - -From 3043a1caa3f6d26128c746b991d086bbb85d50c2 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 29 Feb 2020 16:23:38 +0100 -Subject: [PATCH v2 3/4] drm/bridge: dw-hdmi: Add support for RGB limited range - -CEA 861 standard requestis that RGB quantization range is "limited" for -CEA modes. Support that by adding CSC matrix which downscales values. - -This allows proper color reproduction on TV and PC monitor at the same -time. In future, override property can be added, like "Broadcast RGB" -in i915 driver. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 63 +++++++++++++++++------ - 1 file changed, 46 insertions(+), 17 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index de2c7ec887c8..c8a02e5b5e1b 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -92,6 +92,12 @@ static const u16 csc_coeff_rgb_in_eitu709[3][4] = { - { 0x6756, 0x78ab, 0x2000, 0x0200 } - }; - -+static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { -+ { 0x1b7c, 0x0000, 0x0000, 0x0020 }, -+ { 0x0000, 0x1b7c, 0x0000, 0x0020 }, -+ { 0x0000, 0x0000, 0x1b7c, 0x0020 } -+}; -+ - struct hdmi_vmode { - bool mdataenablepolarity; - -@@ -109,6 +115,7 @@ struct hdmi_data_info { - unsigned int pix_repet_factor; - unsigned int hdcp_enable; - struct hdmi_vmode video_mode; -+ bool rgb_limited_range; - }; - - struct dw_hdmi_i2c { -@@ -956,7 +963,11 @@ static void hdmi_video_sample(struct dw_hdmi *hdmi) - - static int is_color_space_conversion(struct dw_hdmi *hdmi) - { -- return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; -+ return (hdmi->hdmi_data.enc_in_bus_format != -+ hdmi->hdmi_data.enc_out_bus_format) || -+ (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) && -+ hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) && -+ hdmi->hdmi_data.rgb_limited_range); - } - - static int is_color_space_decimation(struct dw_hdmi *hdmi) -@@ -986,25 +997,27 @@ static int is_color_space_interpolation(struct dw_hdmi *hdmi) - static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) - { - const u16 (*csc_coeff)[3][4] = &csc_coeff_default; -+ bool is_input_rgb, is_output_rgb; - unsigned i; - u32 csc_scale = 1; - -- if (is_color_space_conversion(hdmi)) { -- if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { -- if (hdmi->hdmi_data.enc_out_encoding == -- V4L2_YCBCR_ENC_601) -- csc_coeff = &csc_coeff_rgb_out_eitu601; -- else -- csc_coeff = &csc_coeff_rgb_out_eitu709; -- } else if (hdmi_bus_fmt_is_rgb( -- hdmi->hdmi_data.enc_in_bus_format)) { -- if (hdmi->hdmi_data.enc_out_encoding == -- V4L2_YCBCR_ENC_601) -- csc_coeff = &csc_coeff_rgb_in_eitu601; -- else -- csc_coeff = &csc_coeff_rgb_in_eitu709; -- csc_scale = 0; -- } -+ is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); -+ is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); -+ -+ if (!is_input_rgb && is_output_rgb) { -+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) -+ csc_coeff = &csc_coeff_rgb_out_eitu601; -+ else -+ csc_coeff = &csc_coeff_rgb_out_eitu709; -+ } else if (is_input_rgb && !is_output_rgb) { -+ if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) -+ csc_coeff = &csc_coeff_rgb_in_eitu601; -+ else -+ csc_coeff = &csc_coeff_rgb_in_eitu709; -+ csc_scale = 0; -+ } else if (is_input_rgb && is_output_rgb && -+ hdmi->hdmi_data.rgb_limited_range) { -+ csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; - } - - /* The CSC registers are sequential, alternating MSB then LSB */ -@@ -1614,6 +1627,18 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) - drm_hdmi_avi_infoframe_from_display_mode(&frame, - &hdmi->connector, mode); - -+ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { -+ drm_hdmi_avi_infoframe_quant_range(&frame, &hdmi->connector, -+ mode, -+ hdmi->hdmi_data.rgb_limited_range ? -+ HDMI_QUANTIZATION_RANGE_LIMITED : -+ HDMI_QUANTIZATION_RANGE_FULL); -+ } else { -+ frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; -+ frame.ycc_quantization_range = -+ HDMI_YCC_QUANTIZATION_RANGE_LIMITED; -+ } -+ - if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) - frame.colorspace = HDMI_COLORSPACE_YUV444; - else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) -@@ -2099,6 +2124,10 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) - /* TOFIX: Default to RGB888 output format */ - hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; - -+ hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && -+ drm_default_rgb_quant_range(mode) == -+ HDMI_QUANTIZATION_RANGE_LIMITED; -+ - hdmi->hdmi_data.pix_repet_factor = 0; - hdmi->hdmi_data.hdcp_enable = 0; - hdmi->hdmi_data.video_mode.mdataenablepolarity = true; --- -2.25.1 - diff --git a/projects/Allwinner/patches/linux/0005-cedrus-improvements.patch b/projects/Allwinner/patches/linux/0005-cedrus-improvements.patch index f905b0c8d6..462c9d831c 100644 --- a/projects/Allwinner/patches/linux/0005-cedrus-improvements.patch +++ b/projects/Allwinner/patches/linux/0005-cedrus-improvements.patch @@ -1,40 +1,3 @@ -From d36b4160d693a3640be95ebc3aef1dfc9e69ba68 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 15 Mar 2020 09:26:28 +0100 -Subject: [PATCH 01/11] media: cedrus: h264: Fix 4K decoding on H6 - -Due to unknown reason, H6 needs larger intraprediction buffer for 4K -videos than other SoCs. This was discovered by playing 4096x2304 video, -which is maximum what H6 VPU is supposed to support. - -Fixes: 03e612e701a6 ("media: cedrus: Fix H264 4k support") -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index bfb4a4820a67..54ee2aa423e2 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -610,8 +610,12 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) - goto err_mv_col_buf; - } - -+ /* -+ * NOTE: Multiplying by two deviates from CedarX logic, but it -+ * is for some unknown reason needed for H264 4K decoding on H6. -+ */ - ctx->codec.h264.intra_pred_buf_size = -- ALIGN(ctx->src_fmt.width, 64) * 5; -+ ALIGN(ctx->src_fmt.width, 64) * 5 * 2; - ctx->codec.h264.intra_pred_buf = - dma_alloc_coherent(dev->dev, - ctx->codec.h264.intra_pred_buf_size, --- -2.25.1 - - From 51af8e7381275e9b047857bb1269544fa4751ba7 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 26 Oct 2019 13:55:15 +0200