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linux (Allwinner): drop upstream patches included in 6.1.2-rc1
This commit is contained in:
Rudi Heitbaum
parent
0405d900a5
commit
ff1506bb4e
@ -1,91 +0,0 @@
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From e85edafea5122a1357c884559db1a00046102807 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Tue, 4 Oct 2022 20:28:44 +0200
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Subject: [PATCH] media: cedrus: hevc: Fix offset adjustments
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As it turns out, current padding size check works fine in theory but it
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doesn't in practice. Most probable reason are caching issues.
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Let's rework reading data from bitstream using Cedrus engine instead of
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CPU. That way we avoid all cache issues and make sure that we're reading
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same data as Cedrus.
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Fixes: e7060d9a78c2 ("media: uapi: Change data_bit_offset definition")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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.../staging/media/sunxi/cedrus/cedrus_h265.c | 24 ++++++++++++++-----
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.../staging/media/sunxi/cedrus/cedrus_regs.h | 2 ++
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2 files changed, 20 insertions(+), 6 deletions(-)
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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index 82e2e510e62509..400a7bc1670df3 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
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@@ -281,6 +281,17 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
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}
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}
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+static u32 cedrus_h265_show_bits(struct cedrus_dev *dev, int num)
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+{
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+ cedrus_write(dev, VE_DEC_H265_TRIGGER,
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+ VE_DEC_H265_TRIGGER_SHOW_BITS |
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+ VE_DEC_H265_TRIGGER_TYPE_N_BITS(num));
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+ while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY)
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+ udelay(1);
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+
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+ return cedrus_read(dev, VE_DEC_H265_READED_BITS);
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+}
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+
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static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
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struct cedrus_run *run)
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{
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@@ -445,7 +456,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
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u32 num_entry_point_offsets;
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u32 output_pic_list_index;
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u32 pic_order_cnt[2];
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- u8 *padding;
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+ u8 padding;
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int count;
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u32 reg;
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@@ -529,21 +540,22 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run)
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if (slice_params->data_byte_offset == 0)
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return -EOPNOTSUPP;
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- padding = (u8 *)vb2_plane_vaddr(&run->src->vb2_buf, 0) +
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- slice_params->data_byte_offset - 1;
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+ cedrus_h265_skip_bits(dev, (slice_params->data_byte_offset - 1) * 8);
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+
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+ padding = cedrus_h265_show_bits(dev, 8);
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/* at least one bit must be set in that byte */
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- if (*padding == 0)
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+ if (padding == 0)
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return -EINVAL;
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for (count = 0; count < 8; count++)
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- if (*padding & (1 << count))
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+ if (padding & (1 << count))
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break;
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/* Include the one bit. */
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count++;
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- cedrus_h265_skip_bits(dev, slice_params->data_byte_offset * 8 - count);
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+ cedrus_h265_skip_bits(dev, 8 - count);
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/* Bitstream parameters. */
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diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
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index 2f7dbd8b8896e9..424049f567c465 100644
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--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
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+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
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@@ -509,6 +509,8 @@
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#define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \
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SHIFT_AND_MASK_BITS(a, 7, 0)
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+#define VE_DEC_H265_READED_BITS (VE_ENGINE_DEC_H265 + 0xdc)
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+
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#define VE_DEC_H265_SRAM_OFFSET (VE_ENGINE_DEC_H265 + 0xe0)
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#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00
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@ -1,44 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Wed, 12 Oct 2022 21:10:47 +0200
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Subject: [PATCH] iommu/sun50i: Fix reset release
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Reset signal is asserted by writing 0 to the corresponding locations of
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masters we want to reset. So in order to deassert all reset signals, we
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should write 1's to all locations.
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Current code writes 1's to locations of masters which were just reset
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which is good. However, at the same time it also writes 0's to other
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locations and thus asserts reset signals of remaining masters. Fix code
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by writing all 1's when we want to deassert all reset signals.
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This bug was discovered when working with Cedrus (video decoder). When
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it faulted, display went blank due to reset signal assertion.
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Fixes: 4100b8c229b3 ("iommu: Add Allwinner H6 IOMMU driver")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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drivers/iommu/sun50i-iommu.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
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index a84c63518773..c777882d0ec2 100644
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--- a/drivers/iommu/sun50i-iommu.c
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+++ b/drivers/iommu/sun50i-iommu.c
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@@ -27,6 +27,7 @@
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#include <linux/types.h>
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#define IOMMU_RESET_REG 0x010
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+#define IOMMU_RESET_RELEASE_ALL 0xffffffff
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#define IOMMU_ENABLE_REG 0x020
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#define IOMMU_ENABLE_ENABLE BIT(0)
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@@ -893,7 +894,7 @@ static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id)
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iommu_write(iommu, IOMMU_INT_CLR_REG, status);
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iommu_write(iommu, IOMMU_RESET_REG, ~status);
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- iommu_write(iommu, IOMMU_RESET_REG, status);
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+ iommu_write(iommu, IOMMU_RESET_REG, IOMMU_RESET_RELEASE_ALL);
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spin_unlock(&iommu->iommu_lock);
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@ -1,50 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Wed, 12 Oct 2022 22:46:32 +0200
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Subject: [PATCH] iommu/sun50i: Consider all fault sources for reset
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We have to reset masters for all faults - permissions, L1 fault or L2
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fault. Currently it's done only for permissions. If other type of fault
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happens, master is in locked up state. Fix that by really considering
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all fault sources.
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Fixes: 4100b8c229b3 ("iommu: Add Allwinner H6 IOMMU driver")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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drivers/iommu/sun50i-iommu.c | 8 ++++++--
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1 file changed, 6 insertions(+), 2 deletions(-)
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diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
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index c777882d0ec2..38d1069cf383 100644
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--- a/drivers/iommu/sun50i-iommu.c
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+++ b/drivers/iommu/sun50i-iommu.c
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@@ -869,8 +869,8 @@ static phys_addr_t sun50i_iommu_handle_perm_irq(struct sun50i_iommu *iommu)
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static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id)
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{
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+ u32 status, l1_status, l2_status, resets;
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struct sun50i_iommu *iommu = dev_id;
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- u32 status;
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spin_lock(&iommu->iommu_lock);
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@@ -880,6 +880,9 @@ static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id)
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return IRQ_NONE;
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}
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+ l1_status = iommu_read(iommu, IOMMU_L1PG_INT_REG);
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+ l2_status = iommu_read(iommu, IOMMU_L2PG_INT_REG);
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+
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if (status & IOMMU_INT_INVALID_L2PG)
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sun50i_iommu_handle_pt_irq(iommu,
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IOMMU_INT_ERR_ADDR_L2_REG,
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@@ -893,7 +896,8 @@ static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id)
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iommu_write(iommu, IOMMU_INT_CLR_REG, status);
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- iommu_write(iommu, IOMMU_RESET_REG, ~status);
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+ resets = (status | l1_status | l2_status) & IOMMU_INT_MASTER_MASK;
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+ iommu_write(iommu, IOMMU_RESET_REG, ~resets);
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iommu_write(iommu, IOMMU_RESET_REG, IOMMU_RESET_RELEASE_ALL);
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spin_unlock(&iommu->iommu_lock);
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@ -1,33 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Wed, 12 Oct 2022 21:24:03 +0200
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Subject: [PATCH] iommu/sun50i: Fix R/W permission check
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Because driver has enum type permissions and iommu subsystem has bitmap
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type, we have to be careful how check for combined read and write
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permissions is done. In such case, we have to mask both permissions and
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check that both are set at the same time.
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Current code just masks both flags but doesn't check that both are set.
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In short, it always sets R/W permission, regardles if requested
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permissions were RO, WO or RW. Fix that.
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Fixes: 4100b8c229b3 ("iommu: Add Allwinner H6 IOMMU driver")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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drivers/iommu/sun50i-iommu.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
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index 38d1069cf383..135df6934a9e 100644
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--- a/drivers/iommu/sun50i-iommu.c
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+++ b/drivers/iommu/sun50i-iommu.c
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@@ -271,7 +271,7 @@ static u32 sun50i_mk_pte(phys_addr_t page, int prot)
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enum sun50i_iommu_aci aci;
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u32 flags = 0;
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- if (prot & (IOMMU_READ | IOMMU_WRITE))
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+ if ((prot & (IOMMU_READ | IOMMU_WRITE)) == (IOMMU_READ | IOMMU_WRITE))
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aci = SUN50I_IOMMU_ACI_RD_WR;
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else if (prot & IOMMU_READ)
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aci = SUN50I_IOMMU_ACI_RD;
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@ -1,27 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Wed, 12 Oct 2022 21:35:53 +0200
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Subject: [PATCH] iommu/sun50i: Fix flush size
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Function sun50i_table_flush() takes number of entries as an argument,
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not number of bytes. Fix that mistake in sun50i_dte_get_page_table().
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Fixes: 4100b8c229b3 ("iommu: Add Allwinner H6 IOMMU driver")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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drivers/iommu/sun50i-iommu.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
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index 135df6934a9e..7c3b2ac552da 100644
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--- a/drivers/iommu/sun50i-iommu.c
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+++ b/drivers/iommu/sun50i-iommu.c
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@@ -512,7 +512,7 @@ static u32 *sun50i_dte_get_page_table(struct sun50i_iommu_domain *sun50i_domain,
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sun50i_iommu_free_page_table(iommu, drop_pt);
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}
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- sun50i_table_flush(sun50i_domain, page_table, PT_SIZE);
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+ sun50i_table_flush(sun50i_domain, page_table, NUM_PT_ENTRIES);
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sun50i_table_flush(sun50i_domain, dte_addr, 1);
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return page_table;
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@ -1,133 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Wed, 12 Oct 2022 21:55:27 +0200
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Subject: [PATCH] iommu/sun50i: Implement .iotlb_sync_map
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Allocated iova ranges need to be invalidated immediately or otherwise
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they might or might not work when used by master or CPU. This was
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discovered when running video decoder conformity test with Cedrus. Some
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videos were now and then decoded incorrectly and generated page faults.
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According to vendor driver, it's enough to invalidate just start and end
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TLB and PTW cache lines. Documentation says that neighbouring lines must
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be invalidated too. Finally, when page fault occurs, that iova must be
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invalidated the same way, according to documentation.
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Fixes: 4100b8c229b3 ("iommu: Add Allwinner H6 IOMMU driver")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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drivers/iommu/sun50i-iommu.c | 73 ++++++++++++++++++++++++++++++++++++
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1 file changed, 73 insertions(+)
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diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
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index 7c3b2ac552da..d7c5e9b1a087 100644
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--- a/drivers/iommu/sun50i-iommu.c
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+++ b/drivers/iommu/sun50i-iommu.c
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@@ -93,6 +93,8 @@
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#define NUM_PT_ENTRIES 256
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#define PT_SIZE (NUM_PT_ENTRIES * PT_ENTRY_SIZE)
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+#define SPAGE_SIZE 4096
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+
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struct sun50i_iommu {
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struct iommu_device iommu;
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@@ -295,6 +297,62 @@ static void sun50i_table_flush(struct sun50i_iommu_domain *sun50i_domain,
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dma_sync_single_for_device(iommu->dev, dma, size, DMA_TO_DEVICE);
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}
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+static void sun50i_iommu_zap_iova(struct sun50i_iommu *iommu,
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+ unsigned long iova)
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+{
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+ u32 reg;
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+ int ret;
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+
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+ iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_REG, iova);
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+ iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_MASK_REG, GENMASK(31, 12));
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+ iommu_write(iommu, IOMMU_TLB_IVLD_ENABLE_REG,
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+ IOMMU_TLB_IVLD_ENABLE_ENABLE);
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+
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+ ret = readl_poll_timeout_atomic(iommu->base + IOMMU_TLB_IVLD_ENABLE_REG,
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+ reg, !reg, 1, 2000);
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+ if (ret)
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+ dev_warn(iommu->dev, "TLB invalidation timed out!\n");
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+}
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+
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+static void sun50i_iommu_zap_ptw_cache(struct sun50i_iommu *iommu,
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+ unsigned long iova)
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+{
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+ u32 reg;
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+ int ret;
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+
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+ iommu_write(iommu, IOMMU_PC_IVLD_ADDR_REG, iova);
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+ iommu_write(iommu, IOMMU_PC_IVLD_ENABLE_REG,
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+ IOMMU_PC_IVLD_ENABLE_ENABLE);
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+
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+ ret = readl_poll_timeout_atomic(iommu->base + IOMMU_PC_IVLD_ENABLE_REG,
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+ reg, !reg, 1, 2000);
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+ if (ret)
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+ dev_warn(iommu->dev, "PTW cache invalidation timed out!\n");
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+}
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+
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+static void sun50i_iommu_zap_range(struct sun50i_iommu *iommu,
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+ unsigned long iova, size_t size)
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+{
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+ assert_spin_locked(&iommu->iommu_lock);
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+
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+ iommu_write(iommu, IOMMU_AUTO_GATING_REG, 0);
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+
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+ sun50i_iommu_zap_iova(iommu, iova);
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+ sun50i_iommu_zap_iova(iommu, iova + SPAGE_SIZE);
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+ if (size > SPAGE_SIZE) {
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+ sun50i_iommu_zap_iova(iommu, iova + size);
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+ sun50i_iommu_zap_iova(iommu, iova + size + SPAGE_SIZE);
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+ }
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+ sun50i_iommu_zap_ptw_cache(iommu, iova);
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+ sun50i_iommu_zap_ptw_cache(iommu, iova + SZ_1M);
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+ if (size > SZ_1M) {
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+ sun50i_iommu_zap_ptw_cache(iommu, iova + size);
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+ sun50i_iommu_zap_ptw_cache(iommu, iova + size + SZ_1M);
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+ }
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+
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+ iommu_write(iommu, IOMMU_AUTO_GATING_REG, IOMMU_AUTO_GATING_ENABLE);
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+}
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+
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static int sun50i_iommu_flush_all_tlb(struct sun50i_iommu *iommu)
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{
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u32 reg;
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@@ -344,6 +402,18 @@ static void sun50i_iommu_flush_iotlb_all(struct iommu_domain *domain)
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spin_unlock_irqrestore(&iommu->iommu_lock, flags);
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}
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+static void sun50i_iommu_iotlb_sync_map(struct iommu_domain *domain,
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+ unsigned long iova, size_t size)
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+{
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+ struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
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+ struct sun50i_iommu *iommu = sun50i_domain->iommu;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&iommu->iommu_lock, flags);
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+ sun50i_iommu_zap_range(iommu, iova, size);
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+ spin_unlock_irqrestore(&iommu->iommu_lock, flags);
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+}
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+
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static void sun50i_iommu_iotlb_sync(struct iommu_domain *domain,
|
||||
struct iommu_iotlb_gather *gather)
|
||||
{
|
||||
@@ -767,6 +837,7 @@ static const struct iommu_ops sun50i_iommu_ops = {
|
||||
.attach_dev = sun50i_iommu_attach_device,
|
||||
.detach_dev = sun50i_iommu_detach_device,
|
||||
.flush_iotlb_all = sun50i_iommu_flush_iotlb_all,
|
||||
+ .iotlb_sync_map = sun50i_iommu_iotlb_sync_map,
|
||||
.iotlb_sync = sun50i_iommu_iotlb_sync,
|
||||
.iova_to_phys = sun50i_iommu_iova_to_phys,
|
||||
.map = sun50i_iommu_map,
|
||||
@@ -786,6 +857,8 @@ static void sun50i_iommu_report_fault(struct sun50i_iommu *iommu,
|
||||
report_iommu_fault(iommu->domain, iommu->dev, iova, prot);
|
||||
else
|
||||
dev_err(iommu->dev, "Page fault while iommu not attached to any domain?\n");
|
||||
+
|
||||
+ sun50i_iommu_zap_range(iommu, iova, SPAGE_SIZE);
|
||||
}
|
||||
|
||||
static phys_addr_t sun50i_iommu_handle_pt_irq(struct sun50i_iommu *iommu,
|
||||
@ -1,61 +0,0 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@gmail.com>
|
||||
Date: Sat, 15 Oct 2022 10:43:41 +0200
|
||||
Subject: [PATCH] media: Unify YCbCr/YUV terms in format descriptions
|
||||
|
||||
Format descriptions use YCbCr and YUV terms interchangeably. Let's unify
|
||||
them so they all use YUV. While YCbCr is actually correct term here, YUV
|
||||
is shorter and thus it also fixes too long description of P010 tiled
|
||||
format.
|
||||
|
||||
Fixes: 3c8e19d3d3f9 ("media: Add P010 tiled format")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
|
||||
---
|
||||
drivers/media/v4l2-core/v4l2-ioctl.c | 34 ++++++++++++++--------------
|
||||
1 file changed, 17 insertions(+), 17 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
index e6fd355a2e92..de83714f0d40 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
@@ -1347,23 +1347,23 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
|
||||
case V4L2_PIX_FMT_YUV420: descr = "Planar YUV 4:2:0"; break;
|
||||
case V4L2_PIX_FMT_HI240: descr = "8-bit Dithered RGB (BTTV)"; break;
|
||||
case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break;
|
||||
- case V4L2_PIX_FMT_NV12: descr = "Y/CbCr 4:2:0"; break;
|
||||
- case V4L2_PIX_FMT_NV21: descr = "Y/CrCb 4:2:0"; break;
|
||||
- case V4L2_PIX_FMT_NV16: descr = "Y/CbCr 4:2:2"; break;
|
||||
- case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break;
|
||||
- case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break;
|
||||
- case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break;
|
||||
- case V4L2_PIX_FMT_P010: descr = "10-bit Y/CbCr 4:2:0"; break;
|
||||
- case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break;
|
||||
- case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break;
|
||||
- case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break;
|
||||
- case V4L2_PIX_FMT_P010_4L4: descr = "10-bit Y/CbCr 4:2:0 (4x4 Linear)"; break;
|
||||
- case V4L2_PIX_FMT_NV12M: descr = "Y/CbCr 4:2:0 (N-C)"; break;
|
||||
- case V4L2_PIX_FMT_NV21M: descr = "Y/CrCb 4:2:0 (N-C)"; break;
|
||||
- case V4L2_PIX_FMT_NV16M: descr = "Y/CbCr 4:2:2 (N-C)"; break;
|
||||
- case V4L2_PIX_FMT_NV61M: descr = "Y/CrCb 4:2:2 (N-C)"; break;
|
||||
- case V4L2_PIX_FMT_NV12MT: descr = "Y/CbCr 4:2:0 (64x32 MB, N-C)"; break;
|
||||
- case V4L2_PIX_FMT_NV12MT_16X16: descr = "Y/CbCr 4:2:0 (16x16 MB, N-C)"; break;
|
||||
+ case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break;
|
||||
+ case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break;
|
||||
+ case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break;
|
||||
+ case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break;
|
||||
+ case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
|
||||
+ case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break;
|
||||
+ case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break;
|
||||
+ case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break;
|
||||
+ case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break;
|
||||
+ case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break;
|
||||
+ case V4L2_PIX_FMT_P010_4L4: descr = "10-bit Y/UV 4:2:0 (4x4 Linear)"; break;
|
||||
+ case V4L2_PIX_FMT_NV12M: descr = "Y/UV 4:2:0 (N-C)"; break;
|
||||
+ case V4L2_PIX_FMT_NV21M: descr = "Y/VU 4:2:0 (N-C)"; break;
|
||||
+ case V4L2_PIX_FMT_NV16M: descr = "Y/UV 4:2:2 (N-C)"; break;
|
||||
+ case V4L2_PIX_FMT_NV61M: descr = "Y/VU 4:2:2 (N-C)"; break;
|
||||
+ case V4L2_PIX_FMT_NV12MT: descr = "Y/UV 4:2:0 (64x32 MB, N-C)"; break;
|
||||
+ case V4L2_PIX_FMT_NV12MT_16X16: descr = "Y/UV 4:2:0 (16x16 MB, N-C)"; break;
|
||||
case V4L2_PIX_FMT_YUV420M: descr = "Planar YUV 4:2:0 (N-C)"; break;
|
||||
case V4L2_PIX_FMT_YVU420M: descr = "Planar YVU 4:2:0 (N-C)"; break;
|
||||
case V4L2_PIX_FMT_YUV422M: descr = "Planar YUV 4:2:2 (N-C)"; break;
|
||||
Loading…
x
Reference in New Issue
Block a user