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u-boot: bump to latest for Python3 build fixes

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This commit is contained in:
MilhouseVH 2019-11-07 18:41:12 +00:00
parent 6eb226b1fb
commit ffea0c3b5d
3 changed files with 4 additions and 318 deletions
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8
packages/tools/u-boot/package.mk
View File

@ -6,7 +6,7 @@ PKG_NAME="u-boot"
PKG_ARCH="arm aarch64"
PKG_LICENSE="GPL"
PKG_SITE="https://www.denx.de/wiki/U-Boot"
PKG_DEPENDS_TARGET="toolchain swig:host"
PKG_DEPENDS_TARGET="toolchain Python3:host swig:host"
PKG_LONGDESC="Das U-Boot is a cross-platform bootloader for embedded systems."
PKG_IS_KERNEL_PKG="yes"
@ -28,9 +28,9 @@ case "$PROJECT" in
PKG_PATCH_DIRS="rockchip"
;;
*)
PKG_VERSION="2019.10"
PKG_SHA256="8d6d6070739522dd236cba7055b8736bfe92b4fac0ea18ad809829ca79667014"
PKG_URL="http://ftp.denx.de/pub/u-boot/u-boot-$PKG_VERSION.tar.bz2"
PKG_VERSION="d9110878895634cd9e8bf891c832d2a58b36863c"
PKG_SHA256="4d89dc15e5fa3bc9379c097d3315aba08ff6812b892b8900f4bef3fabb8ca1f5"
PKG_URL="https://github.com/u-boot/u-boot/archive/$PKG_VERSION.tar.gz"
;;
esac

129
projects/Allwinner/devices/H6/patches/u-boot/005-beelink-gs1-rsync-kernel.patch
View File

@ -1,129 +0,0 @@
From 70035a8599a28775de8850b0c88099f9b0428e94 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= <peron.clem@gmail.com>
Date: Sun, 11 Aug 2019 19:23:31 +0200
Subject: [PATCH] arm: dts: beelink gs1 rsync with kernel
---
arch/arm/dts/sun50i-h6-beelink-gs1.dts | 76 ++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
index 54b0882bed..0dc33c90dd 100644
--- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
@@ -14,6 +14,7 @@
compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -21,6 +22,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -41,6 +53,40 @@
};
};
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <&reg_aldo2>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@@ -57,6 +103,15 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pd-supply = <&reg_cldo1>;
+ vcc-pg-supply = <&reg_aldo1>;
+};
+
&r_i2c {
status = "okay";
@@ -177,8 +232,29 @@
};
};
+&r_pio {
+ /*
+ * PL0 and PL1 are used for PMIC I2C
+ * don't enable the pl-supply else
+ * it will fail at boot
+ *
+ * vcc-pl-supply = <&reg_aldo1>;
+ */
+ vcc-pm-supply = <&reg_aldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_vbus-supply = <&reg_vcc5v>;
+ status = "okay";
+};
--
2.20.1

185
projects/Allwinner/devices/H6/patches/u-boot/006-DDR3.patch
View File

@ -179,188 +179,3 @@ index 0000000000..d471a24dd5
--
2.22.0
From 0229ee3784c97944165f7469d5e45b8ee3f6b226 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Sat, 29 Jun 2019 17:30:40 +0200
Subject: [PATCH] sunxi: h6: dram: Add support for half DQ
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../include/asm/arch-sunxi/dram_sun50i_h6.h | 1 +
arch/arm/mach-sunxi/dram_sun50i_h6.c | 74 ++++++++++++-------
2 files changed, 50 insertions(+), 25 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index 8b8085611f..4812ee4eeb 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -315,6 +315,7 @@ struct dram_para {
u8 cols;
u8 rows;
u8 ranks;
+ u8 bus_full_width;
const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 5fe53bf463..bdb227fcc3 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -201,6 +201,9 @@ static void mctl_set_addrmap(struct dram_para *para)
u8 rows = para->rows;
u8 ranks = para->ranks;
+ if (!para->bus_full_width)
+ cols -= 1;
+
/* Ranks */
if (ranks == 2)
mctl_ctl->addrmap[0] = rows + cols - 3;
@@ -213,6 +216,10 @@ static void mctl_set_addrmap(struct dram_para *para)
/* Columns */
mctl_ctl->addrmap[2] = 0;
switch (cols) {
+ case 7:
+ mctl_ctl->addrmap[3] = 0x1F1F1F00;
+ mctl_ctl->addrmap[4] = 0x1F1F;
+ break;
case 8:
mctl_ctl->addrmap[3] = 0x1F1F0000;
mctl_ctl->addrmap[4] = 0x1F1F;
@@ -303,13 +310,16 @@ static void mctl_com_init(struct dram_para *para)
reg_val = 0x3f00;
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
- /* TODO: half DQ, DDR4 */
- reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
- MSTR_ACTIVE_RANKS(para->ranks);
+ /* TODO: DDR4 */
+ reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
reg_val |= MSTR_DEVICETYPE_LPDDR3;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
+ if (para->bus_full_width)
+ reg_val |= MSTR_BUSWIDTH_FULL;
+ else
+ reg_val |= MSTR_BUSWIDTH_HALF;
writel(reg_val | BIT(31), &mctl_ctl->mstr);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
@@ -336,7 +346,10 @@ static void mctl_com_init(struct dram_para *para)
}
writel(reg_val, &mctl_ctl->odtcfg);
- /* TODO: half DQ */
+ if (!para->bus_full_width) {
+ writel(0x0, &mctl_phy->dx[2].gcr[0]);
+ writel(0x0, &mctl_phy->dx[3].gcr[0]);
+ }
}
static void mctl_bit_delay_set(struct dram_para *para)
@@ -517,22 +530,31 @@ static void mctl_channel_init(struct dram_para *para)
if (readl(&mctl_phy->pgsr[0]) & 0x400000)
{
- /*
- * Detect single rank.
- * TODO: also detect half DQ.
- */
+ /* Check for single rank and optionally half DQ. */
if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
+ (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
para->ranks = 1;
+
+ if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
+ (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
+ para->bus_full_width = 0;
+
/* Restart DRAM initialization from scratch. */
mctl_core_init(para);
return;
}
- else {
- panic("This DRAM setup is currently not supported.\n");
+
+ /* Check for dual rank and half DQ */
+ if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
+ (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
+ para->bus_full_width = 0;
+
+ /* Restart DRAM initialization from scratch. */
+ mctl_core_init(para);
+ return;
}
+
+ panic("This DRAM setup is currently not supported.\n");
}
if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
@@ -560,11 +582,8 @@ static void mctl_channel_init(struct dram_para *para)
static void mctl_auto_detect_dram_size(struct dram_para *para)
{
- /* TODO: non-LPDDR3, half DQ */
- /*
- * Detect rank number by the code in mctl_channel_init. Furtherly
- * when DQ detection is available it will also be executed there.
- */
+ /* TODO: non-(LP)DDR3 */
+ /* Detect rank number and half DQ by the code in mctl_channel_init. */
mctl_core_init(para);
/* detect row address bits */
@@ -573,8 +592,9 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
mctl_core_init(para);
for (para->rows = 13; para->rows < 18; para->rows++) {
- /* 8 banks, 8 bit per byte and 32 bit width */
- if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
+ /* 8 banks, 8 bit per byte and 16/32 bit width */
+ if (mctl_mem_matches((1 << (para->rows + para->cols +
+ 4 + para->bus_full_width))))
break;
}
@@ -583,18 +603,21 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
mctl_core_init(para);
for (para->cols = 8; para->cols < 11; para->cols++) {
- /* 8 bits per byte and 32 bit width */
- if (mctl_mem_matches(1 << (para->cols + 2)))
+ /* 8 bits per byte and 16/32 bit width */
+ if (mctl_mem_matches(1 << (para->cols + 1 +
+ para->bus_full_width)))
break;
}
}
unsigned long mctl_calc_size(struct dram_para *para)
{
- /* TODO: non-LPDDR3, half DQ */
+ u8 width = para->bus_full_width ? 4 : 2;
+
+ /* TODO: non-(LP)DDR3 */
- /* 8 banks, 32-bit (4 byte) data width */
- return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
+ /* 8 banks */
+ return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
}
#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
@@ -628,6 +651,7 @@ unsigned long sunxi_dram_init(void)
.ranks = 2,
.cols = 11,
.rows = 14,
+ .bus_full_width = 1,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
.type = SUNXI_DRAM_TYPE_LPDDR3,
.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
--
2.22.0