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final version for PR
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@ -97,11 +97,9 @@
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#define FTC532_IDLE (FTC532_BIT * 10)
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#define FTC532_MAX (FTC532_BIT * 58)
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#define DEBUG_FTC532 //@@@@@@@@@@@@@@@@
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struct FTC532 {
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volatile uint32_t rxtime; // ISR timer memory
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volatile uint16_t tsmp = 0xF0F0; // buffer for bit-coded time samples
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volatile uint16_t tsmp = 0; // buffer for bit-coded time samples
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volatile uint16_t sample = 0xF0F0; // valid samples
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volatile uint16_t rxbit; // ISR bit counter
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volatile uint16_t state; // ISR state
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@ -152,7 +150,7 @@ void ICACHE_RAM_ATTR ftc532_ISR(void) { // Hardware interrupt routine, trigger
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}
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if (time_diff > FTC532_SHORT + FTC532_BIT) {
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Ftc532.tsmp |= (1 << Ftc532.rxbit); // LONG
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} else if (time_diff < FTC532_NOISE) { // NOISE
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} else if (time_diff < FTC532_NOISE) { // NOISE (SHORT now implicitly default)
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#ifdef DEBUG_FTC532
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++Ftc532.e_noise;
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#endif // DEBUG_FTC532
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