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Consolidate esp32 hardware info
This commit is contained in:
Theo Arends
parent
343618411c
commit
d5b12c8718
@ -887,29 +887,34 @@ typedef struct {
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*/
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esp_chip_info_t chip_info;
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esp_chip_info(&chip_info);
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uint32_t chip_model = chip_info.model;
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uint32_t chip_revision = chip_info.revision;
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// uint32_t chip_revision = ESP.getChipRevision();
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// idf5 efuse_hal_chip_revision(void)
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if (chip_revision >= 100) { chip_revision /= 100; }
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bool rev3 = (3 == chip_revision);
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if (chip_revision < 100) { chip_revision *= 100; } // Make <idf5 idf5
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bool rev3 = (chip_revision >= 300);
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// bool single_core = (1 == ESP.getChipCores());
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bool single_core = (1 == chip_info.cores);
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if (chip_model < 2) { // ESP32
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/*
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ESP32 Series
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- 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE
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- Two or one CPU core(s) with adjustable clock frequency, ranging from 80 MHz to 240 MHz
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- +19.5 dBm output power ensures a good physical range
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- Classic Bluetooth for legacy connections, also supporting L2CAP, SDP, GAP, SMP, AVDTP, AVCTP, A2DP (SNK) and AVRCP (CT)
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- Support for Bluetooth Low Energy (Bluetooth LE) profiles including L2CAP, GAP, GATT, SMP, and GATT-based profiles like BluFi, SPP-like, etc
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- Bluetooth Low Energy (Bluetooth LE) connects to smart phones, broadcasting low-energy beacons for easy detection
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- Sleep current is less than 5 μA, making it suitable for battery-powered and wearable-electronics applications
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- Peripherals include capacitive touch sensors, Hall sensor, SD card interface, Ethernet, high-speed SPI, UART, I2S and I2C
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*/
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uint32_t pkg_version = 0;
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#if (ESP_IDF_VERSION_MAJOR >= 5)
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pkg_version = bootloader_common_get_chip_ver_pkg();
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#endif
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switch (chip_model) {
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case 0:
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case 1: { // ESP32
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/*
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ESP32 Series
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- 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE
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- Two or one CPU core(s) with adjustable clock frequency, ranging from 80 MHz to 240 MHz
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- +19.5 dBm output power ensures a good physical range
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- Classic Bluetooth for legacy connections, also supporting L2CAP, SDP, GAP, SMP, AVDTP, AVCTP, A2DP (SNK) and AVRCP (CT)
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- Support for Bluetooth Low Energy (Bluetooth LE) profiles including L2CAP, GAP, GATT, SMP, and GATT-based profiles like BluFi, SPP-like, etc
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- Bluetooth Low Energy (Bluetooth LE) connects to smart phones, broadcasting low-energy beacons for easy detection
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- Sleep current is less than 5 μA, making it suitable for battery-powered and wearable-electronics applications
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- Peripherals include capacitive touch sensors, Hall sensor, SD card interface, Ethernet, high-speed SPI, UART, I2S and I2C
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32
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/* esptool:
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def get_pkg_version(self):
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@ -918,50 +923,47 @@ typedef struct {
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pkg_version += ((word3 >> 2) & 0x1) << 3
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return pkg_version
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*/
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#if (ESP_IDF_VERSION_MAJOR >= 5)
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uint32_t pkg_version = bootloader_common_get_chip_ver_pkg();
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#else
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_version = chip_ver & 0x7;
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#if (ESP_IDF_VERSION_MAJOR < 5)
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pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG) & 0x7;
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#endif
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// AddLog(LOG_LEVEL_DEBUG_MORE, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d, Package %d"), chip_info.model, chip_revision, chip_info.cores, chip_ver);
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// AddLog(LOG_LEVEL_DEBUG_MORE, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d"), chip_info.model, chip_revision, chip_info.cores);
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switch (pkg_version) {
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case 0:
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if (single_core) { return F("ESP32-S0WDQ6"); } // Max 240MHz, Single core, QFN 6*6
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else if (rev3) { return F("ESP32-D0WDQ6-V3"); } // Max 240MHz, Dual core, QFN 6*6
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else { return F("ESP32-D0WDQ6"); } // Max 240MHz, Dual core, QFN 6*6
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case 1:
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if (single_core) { return F("ESP32-S0WD"); } // Max 160MHz, Single core, QFN 5*5, ESP32-SOLO-1, ESP32-DevKitC
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else if (rev3) { return F("ESP32-D0WD-V3"); } // Max 240MHz, Dual core, QFN 5*5, ESP32-WROOM-32E, ESP32_WROVER-E, ESP32-DevKitC
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else { return F("ESP32-D0WD"); } // Max 240MHz, Dual core, QFN 5*5, ESP32-WROOM-32D, ESP32_WROVER-B, ESP32-DevKitC
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case 2: return F("ESP32-D2WD"); // Max 160MHz, Dual core, QFN 5*5, 2MB embedded flash
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case 3:
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if (single_core) { return F("ESP32-S0WD-OEM"); } // Max 160MHz, Single core, QFN 5*5, Xiaomi Yeelight
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else { return F("ESP32-D0WD-OEM"); } // Max 240MHz, Dual core, QFN 5*5
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case 4:
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if (single_core) { return F("ESP32-U4WDH-S"); } // Max 160MHz, Single core, QFN 5*5, 4MB embedded flash, ESP32-MINI-1, ESP32-DevKitM-1
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else { return F("ESP32-U4WDH-D"); } // Max 240MHz, Dual core, QFN 5*5, 4MB embedded flash
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case 5:
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if (rev3) { return F("ESP32-PICO-V3"); } // Max 240MHz, Dual core, LGA 7*7, ESP32-PICO-V3-ZERO, ESP32-PICO-V3-ZERO-DevKit
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else { return F("ESP32-PICO-D4"); } // Max 240MHz, Dual core, LGA 7*7, 4MB embedded flash, ESP32-PICO-KIT
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case 6: return F("ESP32-PICO-V3-02"); // Max 240MHz, Dual core, LGA 7*7, 8MB embedded flash, 2MB embedded PSRAM, ESP32-PICO-MINI-02, ESP32-PICO-DevKitM-2
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case 7: return F("ESP32-D0WDR2-V3"); // Max 240MHz, Dual core, QFN 5*5, ESP32-WROOM-32E, ESP32_WROVER-E, ESP32-DevKitC
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}
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switch (pkg_version) {
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case 0:
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if (single_core) { return F("ESP32-S0WDQ6"); } // Max 240MHz, Single core, QFN 6*6
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else if (rev3) { return F("ESP32-D0WDQ6-V3"); } // Max 240MHz, Dual core, QFN 6*6
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else { return F("ESP32-D0WDQ6"); } // Max 240MHz, Dual core, QFN 6*6
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case 1:
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if (single_core) { return F("ESP32-S0WD"); } // Max 160MHz, Single core, QFN 5*5, ESP32-SOLO-1, ESP32-DevKitC
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else if (rev3) { return F("ESP32-D0WD-V3"); } // Max 240MHz, Dual core, QFN 5*5, ESP32-WROOM-32E, ESP32_WROVER-E, ESP32-DevKitC
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else { return F("ESP32-D0WD"); } // Max 240MHz, Dual core, QFN 5*5, ESP32-WROOM-32D, ESP32_WROVER-B, ESP32-DevKitC
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case 2: return F("ESP32-D2WD"); // Max 160MHz, Dual core, QFN 5*5, 2MB embedded flash
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case 3:
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if (single_core) { return F("ESP32-S0WD-OEM"); } // Max 160MHz, Single core, QFN 5*5, Xiaomi Yeelight
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else { return F("ESP32-D0WD-OEM"); } // Max 240MHz, Dual core, QFN 5*5
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case 4:
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if (single_core) { return F("ESP32-U4WDH-S"); } // Max 160MHz, Single core, QFN 5*5, 4MB embedded flash, ESP32-MINI-1, ESP32-DevKitM-1
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else { return F("ESP32-U4WDH-D"); } // Max 240MHz, Dual core, QFN 5*5, 4MB embedded flash
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case 5:
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if (rev3) { return F("ESP32-PICO-V3"); } // Max 240MHz, Dual core, LGA 7*7, ESP32-PICO-V3-ZERO, ESP32-PICO-V3-ZERO-DevKit
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else { return F("ESP32-PICO-D4"); } // Max 240MHz, Dual core, LGA 7*7, 4MB embedded flash, ESP32-PICO-KIT
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case 6: return F("ESP32-PICO-V3-02"); // Max 240MHz, Dual core, LGA 7*7, 8MB embedded flash, 2MB embedded PSRAM, ESP32-PICO-MINI-02, ESP32-PICO-DevKitM-2
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case 7: return F("ESP32-D0WDR2-V3"); // Max 240MHz, Dual core, QFN 5*5, ESP32-WROOM-32E, ESP32_WROVER-E, ESP32-DevKitC
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}
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#endif // CONFIG_IDF_TARGET_ESP32
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return F("ESP32");
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}
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else if (2 == chip_model) { // ESP32-S2
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/*
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ESP32-S2 Series
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- 32-bit MCU & 2.4 GHz Wi-Fi
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- High-performance 240 MHz single-core CPU
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- Ultra-low-power performance: fine-grained clock gating, dynamic voltage and frequency scaling
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- Security features: eFuse、flash encryption, secure boot, signature verification, integrated AES, SHA and RSA algorithms
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- Peripherals include 43 GPIOs, 1 full-speed USB OTG interface, SPI, I2S, UART, I2C, LED PWM, LCD interface, camera interface, ADC, DAC, touch sensor, temperature sensor
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- Availability of common cloud connectivity agents and common product features shortens the time to market
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*/
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return F("ESP32");
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}
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case 2: { // ESP32-S2
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/*
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ESP32-S2 Series
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- 32-bit MCU & 2.4 GHz Wi-Fi
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- High-performance 240 MHz single-core CPU
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- Ultra-low-power performance: fine-grained clock gating, dynamic voltage and frequency scaling
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- Security features: eFuse、flash encryption, secure boot, signature verification, integrated AES, SHA and RSA algorithms
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- Peripherals include 43 GPIOs, 1 full-speed USB OTG interface, SPI, I2S, UART, I2C, LED PWM, LCD interface, camera interface, ADC, DAC, touch sensor, temperature sensor
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- Availability of common cloud connectivity agents and common product features shortens the time to market
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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/* esptool:
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def get_flash_version(self):
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@ -978,138 +980,133 @@ typedef struct {
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pkg_version = (word3 >> 28) & 0x0F
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return pkg_version
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*/
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_FLASH_VERSION);
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uint32_t psram_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PSRAM_VERSION);
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uint32_t pkg_version = (chip_ver & 0xF) + ((psram_ver & 0xF) * 100);
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#if (ESP_IDF_VERSION_MAJOR < 5)
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pkg_version = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_FLASH_VERSION) & 0xF;
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#endif
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uint32_t psram_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PSRAM_VERSION);
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pkg_version += ((psram_ver & 0xF) * 100);
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// AddLog(LOG_LEVEL_DEBUG_MORE, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d, Package %d"), chip_info.model, chip_revision, chip_info.cores, chip_ver);
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// AddLog(LOG_LEVEL_DEBUG_MORE, PSTR("HDW: ESP32 Model %d, Revision %d, Core %d, Package %d"), chip_info.model, chip_revision, chip_info.cores, chip_ver);
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switch (pkg_version) {
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case 0: return F("ESP32-S2"); // Max 240MHz, Single core, QFN 7*7, ESP32-S2-WROOM, ESP32-S2-WROVER, ESP32-S2-Saola-1, ESP32-S2-Kaluga-1
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case 1: return F("ESP32-S2FH2"); // Max 240MHz, Single core, QFN 7*7, 2MB embedded flash, ESP32-S2-MINI-1, ESP32-S2-DevKitM-1
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case 2: return F("ESP32-S2FH4"); // Max 240MHz, Single core, QFN 7*7, 4MB embedded flash
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case 3: return F("ESP32-S2FN4R2"); // Max 240MHz, Single core, QFN 7*7, 4MB embedded flash, 2MB embedded PSRAM, , ESP32-S2-MINI-1U, ESP32-S2-DevKitM-1U
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case 100: return F("ESP32-S2R2");
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case 102: return F("ESP32-S2FNR2"); // Max 240MHz, Single core, QFN 7*7, 4MB embedded flash, 2MB embedded PSRAM, , Lolin S2 mini
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}
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switch (pkg_version) {
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case 0: return F("ESP32-S2"); // Max 240MHz, Single core, QFN 7*7, ESP32-S2-WROOM, ESP32-S2-WROVER, ESP32-S2-Saola-1, ESP32-S2-Kaluga-1
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case 1: return F("ESP32-S2FH2"); // Max 240MHz, Single core, QFN 7*7, 2MB embedded flash, ESP32-S2-MINI-1, ESP32-S2-DevKitM-1
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case 2: return F("ESP32-S2FH4"); // Max 240MHz, Single core, QFN 7*7, 4MB embedded flash
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case 3: return F("ESP32-S2FN4R2"); // Max 240MHz, Single core, QFN 7*7, 4MB embedded flash, 2MB embedded PSRAM, , ESP32-S2-MINI-1U, ESP32-S2-DevKitM-1U
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case 100: return F("ESP32-S2R2");
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case 102: return F("ESP32-S2FNR2"); // Max 240MHz, Single core, QFN 7*7, 4MB embedded flash, 2MB embedded PSRAM, , Lolin S2 mini
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}
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#endif // CONFIG_IDF_TARGET_ESP32S2
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return F("ESP32-S2");
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}
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else if (4 == chip_model) { // ESP32-S3(beta2)
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return F("ESP32-S3");
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}
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else if (5 == chip_model) { // ESP32-C3 = ESP8685
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/*
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ESP32-C3 Series
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- 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
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- 32-bit RISC-V single-core processor with a four-stage pipeline that operates at up to 160 MHz
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- State-of-the-art power and RF performance
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- 400 KB of SRAM and 384 KB of ROM on the chip, and SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to flash
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- Reliable security features ensured by RSA-3072-based secure boot, AES-128-XTS-based flash encryption, the innovative digital signature and the HMAC peripheral, hardware acceleration support for cryptographic algorithms
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- Rich set of peripheral interfaces and GPIOs, ideal for various scenarios and complex applications
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*/
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return F("ESP32-S2");
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}
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case 5: { // ESP32-C3 = ESP8685 if embedded flash
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/*
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ESP32-C3 Series
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- 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
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- 32-bit RISC-V single-core processor with a four-stage pipeline that operates at up to 160 MHz
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- State-of-the-art power and RF performance
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- 400 KB of SRAM and 384 KB of ROM on the chip, and SPI, Dual SPI, Quad SPI, and QPI interfaces that allow connection to flash
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- Reliable security features ensured by RSA-3072-based secure boot, AES-128-XTS-based flash encryption, the innovative digital signature and the HMAC peripheral, hardware acceleration support for cryptographic algorithms
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- Rich set of peripheral interfaces and GPIOs, ideal for various scenarios and complex applications
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32C3
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
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uint32_t pkg_version = chip_ver & 0x7;
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switch (pkg_version) {
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case 0: return F("ESP32-C3"); // Max 160MHz, Single core, QFN 5*5, ESP32-C3-WROOM-02, ESP32-C3-DevKitC-02
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case 1: return F("ESP32-C3FH4"); // Max 160MHz, Single core, QFN 5*5, 4MB embedded flash, ESP32-C3-MINI-1, ESP32-C3-DevKitM-1
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}
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#if (ESP_IDF_VERSION_MAJOR < 5)
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pkg_version = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION) & 0x7;
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#endif
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switch (pkg_version) {
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case 0: return F("ESP32-C3"); // Max 160MHz, Single core, QFN 5*5, ESP32-C3-WROOM-02, ESP32-C3-DevKitC-02
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// case 1: return F("ESP32-C3FH4"); // Max 160MHz, Single core, QFN 5*5, 4MB embedded flash, ESP32-C3-MINI-1, ESP32-C3-DevKitM-1
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case 1: return F("ESP8685"); // Max 160MHz, Single core, QFN 5*5, 4MB embedded flash, ESP32-C3-MINI-1, ESP32-C3-DevKitM-1
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case 2: return F("ESP32-C3 AZ"); // QFN32
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case 3: return F("ESP8686"); // QFN24
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}
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#endif // CONFIG_IDF_TARGET_ESP32C3
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return F("ESP32-C3");
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}
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else if (6 == chip_model) { // ESP32-S3(beta3)
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return F("ESP32-S3");
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}
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else if (7 == chip_model) { // ESP32-C6(beta)
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return F("ESP32-C6");
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}
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else if (9 == chip_model) { // ESP32-S3
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/*
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ESP32-S3 Series
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- 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
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- Xtensa® 32-bit LX7 dual-core processor that operates at up to 240 MHz
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- 512 KB of SRAM and 384 KB of ROM on the chip, and SPI, Dual SPI, Quad SPI, Octal SPI, QPI, and OPI interfaces that allow connection to flash and external RAM
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- Additional support for vector instructions in the MCU, which provides acceleration for neural network computing and signal processing workloads
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- Peripherals include 45 programmable GPIOs, SPI, I2S, I2C, PWM, RMT, ADC and UART, SD/MMC host and TWAITM
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- Reliable security features ensured by RSA-based secure boot, AES-XTS-based flash encryption, the innovative digital signature and the HMAC peripheral, “World Controller”
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32S3
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#if (ESP_ARDUINO_VERSION_MAJOR > 2)
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// chip-debug-report.cpp
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
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uint32_t pkg_version = chip_ver & 0x7;
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switch (pkg_version) {
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case 0: return F("ESP32-S3");
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return F("ESP32-C3");
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}
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case 4: // ESP32-S3(beta2)
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case 6: // ESP32-S3(beta3)
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case 9: { // ESP32-S3
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/*
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ESP32-S3 Series
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- 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
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- Xtensa® 32-bit LX7 dual-core processor that operates at up to 240 MHz
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- 512 KB of SRAM and 384 KB of ROM on the chip, and SPI, Dual SPI, Quad SPI, Octal SPI, QPI, and OPI interfaces that allow connection to flash and external RAM
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- Additional support for vector instructions in the MCU, which provides acceleration for neural network computing and signal processing workloads
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- Peripherals include 45 programmable GPIOs, SPI, I2S, I2C, PWM, RMT, ADC and UART, SD/MMC host and TWAITM
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- Reliable security features ensured by RSA-based secure boot, AES-XTS-based flash encryption, the innovative digital signature and the HMAC peripheral, “World Controller”
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*/
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#ifdef CONFIG_IDF_TARGET_ESP32S3
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#if (ESP_IDF_VERSION_MAJOR >= 5)
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// chip-debug-report.cpp
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// pkg_version = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION) & 0x7;
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switch (pkg_version) {
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case 0: return F("ESP32-S3"); // QFN56
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case 1: return F("ESP32-S3-PICO-1"); // LGA56
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}
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#endif
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#endif // CONFIG_IDF_TARGET_ESP32S3
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return F("ESP32-S3"); // Max 240MHz, Dual core, QFN 7*7, ESP32-S3-WROOM-1, ESP32-S3-DevKitC-1
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}
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else if (10 == chip_model) { // ESP32-H2(beta1)
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return F("ESP32-H2");
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}
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else if (12 == chip_model) { // ESP32-C2 = ESP8684
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/*
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ESP32-C2 Series
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- 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
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- 32-bit RISC-V single-core processor that operates at up to 120 MHz
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- State-of-the-art power and RF performance
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- 576 KB ROM, 272 KB SRAM (16 KB for cache) on the chip
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- 14 programmable GPIOs: SPI, UART, I2C, LED PWM controller, General DMA controller (GDMA), SAR ADC, Temperature sensor
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*/
|
||||
return F("ESP32-S3"); // Max 240MHz, Dual core, QFN 7*7, ESP32-S3-WROOM-1, ESP32-S3-DevKitC-1
|
||||
}
|
||||
case 12: { // ESP32-C2 = ESP8684 if embedded flash
|
||||
/*
|
||||
ESP32-C2 Series
|
||||
- 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
|
||||
- 32-bit RISC-V single-core processor that operates at up to 120 MHz
|
||||
- State-of-the-art power and RF performance
|
||||
- 576 KB ROM, 272 KB SRAM (16 KB for cache) on the chip
|
||||
- 14 programmable GPIOs: SPI, UART, I2C, LED PWM controller, General DMA controller (GDMA), SAR ADC, Temperature sensor
|
||||
*/
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32C2
|
||||
// chip-debug-report.cpp
|
||||
uint32_t chip_ver = REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_PKG_VERSION);
|
||||
uint32_t pkg_version = chip_ver & 0x7;
|
||||
|
||||
switch (pkg_version) {
|
||||
case 0: return F("ESP32-C2");
|
||||
}
|
||||
// chip-debug-report.cpp
|
||||
// pkg_version = REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_PKG_VERSION) & 0x7;
|
||||
switch (pkg_version) {
|
||||
case 0: return F("ESP32-C2");
|
||||
case 1: return F("ESP32-C2");
|
||||
}
|
||||
#endif // CONFIG_IDF_TARGET_ESP32C2
|
||||
return F("ESP32-C2");
|
||||
}
|
||||
else if (13 == chip_model) { // ESP32-C6
|
||||
/*
|
||||
ESP32-C6 Series
|
||||
- 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4
|
||||
- 32-bit RISC-V single-core processor that operates at up to 160 MHz
|
||||
- State-of-the-art power and RF performance
|
||||
- 320 KB ROM, 512 KB SRAM, 16 KB Low-power SRAM on the chip, and works with external flash
|
||||
- 30 (QFN40) or 22 (QFN32) programmable GPIOs, with support for SPI, UART, I2C, I2S, RMT, TWAI and PWM
|
||||
*/
|
||||
return F("ESP32-C2");
|
||||
}
|
||||
case 7: // ESP32-C6(beta)
|
||||
case 13: { // ESP32-C6
|
||||
/*
|
||||
ESP32-C6 Series
|
||||
- 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4
|
||||
- 32-bit RISC-V single-core processor that operates at up to 160 MHz
|
||||
- State-of-the-art power and RF performance
|
||||
- 320 KB ROM, 512 KB SRAM, 16 KB Low-power SRAM on the chip, and works with external flash
|
||||
- 30 (QFN40) or 22 (QFN32) programmable GPIOs, with support for SPI, UART, I2C, I2S, RMT, TWAI and PWM
|
||||
*/
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32C6
|
||||
// chip-debug-report.cpp
|
||||
uint32_t chip_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
|
||||
uint32_t pkg_version = chip_ver & 0x7;
|
||||
switch (pkg_version) {
|
||||
case 0: return F("ESP32-C6");
|
||||
}
|
||||
// chip-debug-report.cpp
|
||||
// pkg_version = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION) & 0x7;
|
||||
switch (pkg_version) {
|
||||
case 0: return F("ESP32-C6");
|
||||
case 1: return F("ESP32-C6FH4");
|
||||
}
|
||||
#endif // CONFIG_IDF_TARGET_ESP32C6
|
||||
return F("ESP32-C6");
|
||||
}
|
||||
else if (14 == chip_model) { // ESP32-H2(beta2)
|
||||
return F("ESP32-H2");
|
||||
}
|
||||
else if (16 == chip_model) { // ESP32-H2
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32H2
|
||||
// chip-debug-report.cpp
|
||||
uint32_t chip_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_4_REG, EFUSE_PKG_VERSION);
|
||||
uint32_t pkg_version = chip_ver & 0x7;
|
||||
switch (pkg_version) {
|
||||
case 0: return F("ESP32-H2");
|
||||
return F("ESP32-C6");
|
||||
}
|
||||
case 10: // ESP32-H2(beta1)
|
||||
case 14: // ESP32-H2(beta2)
|
||||
case 16: { // ESP32-H2
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32H2
|
||||
// chip-debug-report.cpp
|
||||
// pkg_version = REG_GET_FIELD(EFUSE_RD_MAC_SYS_4_REG, EFUSE_PKG_VERSION) & 0x7;
|
||||
switch (pkg_version) {
|
||||
case 0: return F("ESP32-H2");
|
||||
}
|
||||
#endif // CONFIG_IDF_TARGET_ESP32H2
|
||||
return F("ESP32-H2");
|
||||
return F("ESP32-H2");
|
||||
}
|
||||
}
|
||||
return F("ESP32");
|
||||
}
|
||||
|
||||
String GetDeviceHardwareRevision(void) {
|
||||
// ESP32-S2
|
||||
// ESP32-D0WDQ6 rev.1
|
||||
// ESP32-C3 rev.2
|
||||
// ESP32-C3 rev.3
|
||||
// ESP32-D0WDQ6 v1.0
|
||||
// ESP32-C3 v2.0
|
||||
// ESP32-C3 v3.0
|
||||
String result = GetDeviceHardware(); // ESP32-C3
|
||||
|
||||
esp_chip_info_t chip_info;
|
||||
@ -1119,8 +1116,8 @@ String GetDeviceHardwareRevision(void) {
|
||||
uint32_t chip_revision = chip_info.revision;
|
||||
if (chip_revision < 100) { chip_revision *= 100; } // Make <idf5 idf5
|
||||
char revision[16];
|
||||
snprintf_P(revision, sizeof(revision), PSTR(" rev %d.%d"), chip_revision / 100, chip_revision % 100);
|
||||
result += revision; // ESP32-C3 rev 3.0
|
||||
snprintf_P(revision, sizeof(revision), PSTR(" v%d.%d"), chip_revision / 100, chip_revision % 100);
|
||||
result += revision; // ESP32-C3 v3.0
|
||||
}
|
||||
|
||||
return result;
|
||||
@ -1152,13 +1149,12 @@ bool CanUsePSRAM(void) {
|
||||
esp_chip_info(&chip_info);
|
||||
uint32_t chip_revision = chip_info.revision;
|
||||
// idf5 efuse_hal_chip_revision(void)
|
||||
if (chip_revision >= 100) { chip_revision /= 100; }
|
||||
if ((CHIP_ESP32 == chip_info.model) && (chip_revision < 3)) {
|
||||
if (chip_revision < 100) { chip_revision *= 100; } // Make <idf5 idf5
|
||||
if ((CHIP_ESP32 == chip_info.model) && (chip_revision < 300)) {
|
||||
return false;
|
||||
}
|
||||
#if ESP_IDF_VERSION_MAJOR < 4
|
||||
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
|
||||
uint32_t pkg_version = chip_ver & 0x7;
|
||||
uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG) & 0x7;
|
||||
if ((CHIP_ESP32 == chip_info.model) && (pkg_version >= 6)) {
|
||||
return false; // support for embedded PSRAM of ESP32-PICO-V3-02 requires esp-idf 4.4
|
||||
}
|
||||
|
||||
@ -124,7 +124,8 @@ static void IRAM_ATTR RotaryIsrArgMiDesk(void *arg) {
|
||||
encoder->state = (state >> 2);
|
||||
}
|
||||
|
||||
void IRAM_ATTR RotaryIsrArg(void *arg) {
|
||||
void IRAM_ATTR RotaryIsrArg(void *arg);
|
||||
void RotaryIsrArg(void *arg) {
|
||||
tEncoder* encoder = static_cast<tEncoder*>(arg);
|
||||
|
||||
// Theo Arends
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user