From a488c8cd5c0f9cdfc1f61efdb2354287a8d8332c Mon Sep 17 00:00:00 2001 From: Clyde Stubbs <2366188+clydebarrow@users.noreply.github.com> Date: Wed, 11 Jun 2025 19:45:26 +1000 Subject: [PATCH] [spi] Restrict octal spi to S3/S2/P4 (#9041) --- esphome/components/spi/__init__.py | 12 +++++-- tests/components/spi/test.esp32-p4-idf.yaml | 38 +++++++++++++++++++++ 2 files changed, 48 insertions(+), 2 deletions(-) create mode 100644 tests/components/spi/test.esp32-p4-idf.yaml diff --git a/esphome/components/spi/__init__.py b/esphome/components/spi/__init__.py index 5b28b3546b..ffb5e11f79 100644 --- a/esphome/components/spi/__init__.py +++ b/esphome/components/spi/__init__.py @@ -2,12 +2,14 @@ import re from esphome import pins import esphome.codegen as cg +from esphome.components.esp32 import only_on_variant from esphome.components.esp32.const import ( KEY_ESP32, VARIANT_ESP32C2, VARIANT_ESP32C3, VARIANT_ESP32C6, VARIANT_ESP32H2, + VARIANT_ESP32P4, VARIANT_ESP32S2, VARIANT_ESP32S3, ) @@ -287,7 +289,15 @@ def spi_mode_schema(mode): if mode == TYPE_SINGLE: return SPI_SINGLE_SCHEMA pin_count = 4 if mode == TYPE_QUAD else 8 + onlys = [cv.only_on([PLATFORM_ESP32]), cv.only_with_esp_idf] + if pin_count == 8: + onlys.append( + only_on_variant( + supported=[VARIANT_ESP32S3, VARIANT_ESP32S2, VARIANT_ESP32P4] + ) + ) return cv.All( + *onlys, cv.Schema( { cv.GenerateID(): cv.declare_id(TYPE_CLASS[mode]), @@ -308,8 +318,6 @@ def spi_mode_schema(mode): ), } ), - cv.only_on([PLATFORM_ESP32]), - cv.only_with_esp_idf, ) diff --git a/tests/components/spi/test.esp32-p4-idf.yaml b/tests/components/spi/test.esp32-p4-idf.yaml new file mode 100644 index 0000000000..061e3dd44a --- /dev/null +++ b/tests/components/spi/test.esp32-p4-idf.yaml @@ -0,0 +1,38 @@ +spi: + - id: quad_spi + type: quad + interface: spi3 + clk_pin: + number: 47 + data_pins: + - allow_other_uses: true + number: 40 + - allow_other_uses: true + number: 41 + - allow_other_uses: true + number: 42 + - allow_other_uses: true + number: 43 + - id: octal_spi + type: octal + interface: hardware + clk_pin: + number: 0 + data_pins: + - 36 + - 37 + - 38 + - 39 + - allow_other_uses: true + number: 40 + - allow_other_uses: true + number: 41 + - allow_other_uses: true + number: 42 + - allow_other_uses: true + number: 43 + - id: spi_id_3 + interface: any + clk_pin: 8 + mosi_pin: 9 +