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arch/mips: add support for MIPS NaN
MIPS supports two different NaN encodings, legacy and 2008. Information about MIPS NaN encodings can be found here: https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html NaN legacy is the only option available for R2 cores and older. NaN 2008 is the only option available for R6 cores. R5 cores can have either NaN legacy or NaN 2008, depending on the implementation. So, if the user selects a generic R5 target architecture variant, we show a choice menu with both options available. For well known R5 cores we directly select the NaN enconding they use. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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@ -264,6 +264,9 @@ config BR2_GCC_TARGET_ARCH
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config BR2_GCC_TARGET_ABI
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config BR2_GCC_TARGET_ABI
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string
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string
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config BR2_GCC_TARGET_NAN
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string
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config BR2_GCC_TARGET_CPU
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config BR2_GCC_TARGET_CPU
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string
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string
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@ -1,20 +1,26 @@
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# mips default CPU ISAs
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# mips default CPU ISAs
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config BR2_MIPS_CPU_MIPS32
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config BR2_MIPS_CPU_MIPS32
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bool
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bool
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select BR2_MIPS_NAN_LEGACY
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config BR2_MIPS_CPU_MIPS32R2
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config BR2_MIPS_CPU_MIPS32R2
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bool
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bool
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select BR2_MIPS_NAN_LEGACY
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config BR2_MIPS_CPU_MIPS32R5
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config BR2_MIPS_CPU_MIPS32R5
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bool
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bool
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config BR2_MIPS_CPU_MIPS32R6
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config BR2_MIPS_CPU_MIPS32R6
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bool
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bool
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select BR2_MIPS_NAN_2008
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config BR2_MIPS_CPU_MIPS64
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config BR2_MIPS_CPU_MIPS64
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bool
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bool
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select BR2_MIPS_NAN_LEGACY
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config BR2_MIPS_CPU_MIPS64R2
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config BR2_MIPS_CPU_MIPS64R2
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bool
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bool
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select BR2_MIPS_NAN_LEGACY
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config BR2_MIPS_CPU_MIPS64R5
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config BR2_MIPS_CPU_MIPS64R5
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bool
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bool
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config BR2_MIPS_CPU_MIPS64R6
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config BR2_MIPS_CPU_MIPS64R6
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bool
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bool
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select BR2_MIPS_NAN_2008
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choice
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choice
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prompt "Target Architecture Variant"
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prompt "Target Architecture Variant"
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@ -51,6 +57,7 @@ config BR2_mips_m5150
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bool "M5150"
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bool "M5150"
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depends on !BR2_ARCH_IS_64
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depends on !BR2_ARCH_IS_64
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select BR2_MIPS_CPU_MIPS32R5
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select BR2_MIPS_CPU_MIPS32R5
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select BR2_MIPS_NAN_2008
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config BR2_mips_m6250
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config BR2_mips_m6250
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bool "M6250"
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bool "M6250"
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depends on !BR2_ARCH_IS_64
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depends on !BR2_ARCH_IS_64
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@ -59,6 +66,7 @@ config BR2_mips_p5600
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bool "P5600"
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bool "P5600"
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depends on !BR2_ARCH_IS_64
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depends on !BR2_ARCH_IS_64
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select BR2_MIPS_CPU_MIPS32R5
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select BR2_MIPS_CPU_MIPS32R5
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select BR2_MIPS_NAN_2008
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config BR2_mips_xburst
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config BR2_mips_xburst
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bool "XBurst"
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bool "XBurst"
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depends on !BR2_ARCH_IS_64
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depends on !BR2_ARCH_IS_64
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@ -126,6 +134,33 @@ config BR2_MIPS_SOFT_FLOAT
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floating point functions, then everything will need to be
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floating point functions, then everything will need to be
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compiled with soft floating point support (-msoft-float).
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compiled with soft floating point support (-msoft-float).
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config BR2_MIPS_NAN_LEGACY
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bool
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config BR2_MIPS_NAN_2008
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bool
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choice
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prompt "Target NaN"
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depends on BR2_mips_32r5 || BR2_mips_64r5
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default BR2_MIPS_ENABLE_NAN_2008
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help
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NaN encoding to be used
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config BR2_MIPS_ENABLE_NAN_LEGACY
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bool "legacy"
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select BR2_MIPS_NAN_LEGACY
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config BR2_MIPS_ENABLE_NAN_2008
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bool "2008"
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depends on !BR2_MIPS_SOFT_FLOAT
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select BR2_MIPS_NAN_2008
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endchoice
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config BR2_GCC_TARGET_NAN
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default "legacy" if BR2_MIPS_NAN_LEGACY
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default "2008" if BR2_MIPS_NAN_2008
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config BR2_ARCH
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config BR2_ARCH
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default "mips" if BR2_mips
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default "mips" if BR2_mips
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default "mipsel" if BR2_mipsel
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default "mipsel" if BR2_mipsel
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@ -210,6 +210,9 @@ endif
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ifneq ($(call qstrip,$(BR2_GCC_TARGET_ABI)),)
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ifneq ($(call qstrip,$(BR2_GCC_TARGET_ABI)),)
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HOST_GCC_COMMON_CONF_OPTS += --with-abi=$(BR2_GCC_TARGET_ABI)
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HOST_GCC_COMMON_CONF_OPTS += --with-abi=$(BR2_GCC_TARGET_ABI)
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endif
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endif
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ifneq ($(call qstrip,$(BR2_GCC_TARGET_NAN)),)
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HOST_GCC_COMMON_CONF_OPTS += --with-nan=$(BR2_GCC_TARGET_NAN)
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endif
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ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),)
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ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),)
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ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),)
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ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),)
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HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION))
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HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION))
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@ -260,6 +263,7 @@ HOST_GCC_COMMON_WRAPPER_TARGET_CPU := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_
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endif
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endif
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HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
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HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
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HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
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HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI))
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HOST_GCC_COMMON_WRAPPER_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN))
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HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
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HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU))
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HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
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HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
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HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
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HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE))
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@ -273,6 +277,9 @@ endif
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ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_ABI),)
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ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_ABI),)
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HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(HOST_GCC_COMMON_WRAPPER_TARGET_ABI)"'
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HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(HOST_GCC_COMMON_WRAPPER_TARGET_ABI)"'
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endif
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endif
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ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_NAN),)
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HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(HOST_GCC_COMMON_WRAPPER_TARGET_NAN)"'
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endif
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ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),)
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ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),)
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HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"'
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HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"'
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endif
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endif
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@ -123,8 +123,8 @@ config BR2_UCLIBC_MIPS_ABI
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config BR2_UCLIBC_MIPS_NAN
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config BR2_UCLIBC_MIPS_NAN
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string
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string
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default "LEGACY" if BR2_MIPS_CPU_MIPS32 || BR2_MIPS_CPU_MIPS64
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default "LEGACY" if BR2_MIPS_NAN_LEGACY
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default "2008" if BR2_MIPS_CPU_MIPS32R6 || BR2_MIPS_CPU_MIPS64R6
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default "2008" if BR2_MIPS_NAN_2008
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depends on BR2_UCLIBC_TARGET_ARCH = "mips"
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depends on BR2_UCLIBC_TARGET_ARCH = "mips"
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config BR2_UCLIBC_SH_TYPE
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config BR2_UCLIBC_SH_TYPE
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@ -154,6 +154,7 @@ CC_TARGET_CPU_ := $(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVIS
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endif
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endif
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CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
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CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH))
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CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
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CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI))
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CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN))
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CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
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CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU))
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CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
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CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI))
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CC_TARGET_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_MODE))
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CC_TARGET_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_MODE))
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@ -176,6 +177,10 @@ ifneq ($(CC_TARGET_ABI_),)
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TOOLCHAIN_EXTERNAL_CFLAGS += -mabi=$(CC_TARGET_ABI_)
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TOOLCHAIN_EXTERNAL_CFLAGS += -mabi=$(CC_TARGET_ABI_)
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TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(CC_TARGET_ABI_)"'
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TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_ABI='"$(CC_TARGET_ABI_)"'
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endif
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endif
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ifneq ($(CC_TARGET_NAN_),)
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TOOLCHAIN_EXTERNAL_CFLAGS += -mnan=$(CC_TARGET_NAN_)
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TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(CC_TARGET_NAN_)"'
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endif
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ifneq ($(CC_TARGET_FPU_),)
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ifneq ($(CC_TARGET_FPU_),)
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TOOLCHAIN_EXTERNAL_CFLAGS += -mfpu=$(CC_TARGET_FPU_)
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TOOLCHAIN_EXTERNAL_CFLAGS += -mfpu=$(CC_TARGET_FPU_)
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TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(CC_TARGET_FPU_)"'
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TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(CC_TARGET_FPU_)"'
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@ -51,6 +51,9 @@ static char *predef_args[] = {
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#ifdef BR_ABI
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#ifdef BR_ABI
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"-mabi=" BR_ABI,
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"-mabi=" BR_ABI,
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#endif
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#endif
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#ifdef BR_NAN
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"-mnan=" BR_NAN,
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#endif
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#ifdef BR_FPU
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#ifdef BR_FPU
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"-mfpu=" BR_FPU,
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"-mfpu=" BR_FPU,
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#endif
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#endif
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