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311af5e8c2
Initially we had a port only for ARCv2 cores but then with a simple change ARCompact cores got supported as well. So we generalize from BR2_archs to BR2_arcle as we haven't tried to get glibc working on big-endian ARCs yet. Also we never bothered to check avaialbility of atomic instructions in the core but in case of Glibc for ARC this is really a must, so we add this check here. Note in case of uClibc we may have system w/o HW atomics but: 1. Only single-core systems are allowed 2. Atomic instructions are emulated via arc_usr_cmpxchg syscall Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>