mirror of
https://github.com/HASwitchPlate/openHASP.git
synced 2025-07-24 11:46:34 +00:00
Merge branch '0.1.0-fsmc' of https://github.com/arovak/hasp-lvgl into 0.1.0-fsmc
This commit is contained in:
fvanroie
commit
ffc3ef05de
@ -0,0 +1,278 @@
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// created by Jean-Marc Zingg to be the GxIO_STM32F407ZGM4_FSMC io class for the GxTFT library
|
||||
// adapted by NetWize to work on STM32F407ZGT6 board
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//
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// License: GNU GENERAL PUBLIC LICENSE V3, see LICENSE
|
||||
//
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||||
// this is the io class for STM32F407ZGM4 board with FMSC TFT connector, e.g. for
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// https://www.aliexpress.com/item/STM32-ARM-Cortex-M4-STM32F407ZGT6-development-board-STM32F4-core-board/32827402179.html?spm=a2g0s.9042311.0.0.49b14c4dUViVg4
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// and the matching TFTs of the same offer
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//
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// and e.g. for direct matching display
|
||||
// https://www.aliexpress.com/item/STM32F407ZET6-development-board-M4-STM32F4-core-board-arm-development-board-cortex-M4/32689262341.html?spm=a2g0s.9042311.0.0.49b14c4dUViVg4
|
||||
// https://www.aliexpress.com/item/32662835059.html?spm=a2g0o.cart.0.0.56f03c00mB9alZ&mp=1
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//
|
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// for pin information see the backside of the TFT, for the data pin to port pin mapping see FSMC pin table STM32F407V doc.
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//
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// this io class can be used with or adapted to other STM32F407V/Z processor boards with FSMC TFT connector.
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#if defined(ARDUINO_ARCH_STM32) && (defined(STM32F407VE) || defined(STM32F407ZE) || defined(STM32F407ZG))
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#include "GxIO_STM32F407ZGx_FSMC.h"
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// TFT connector uses FSMC pins
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// D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
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// PD14 PD15 PD0 PD1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 PD9 PD10
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// connector pins
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// 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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// GND RST D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RD WR RS CS SCK SCS SI SO INT BLK SET GND 3.3 GND
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// D10 D9 D8 E15 E14 E13 E12 E11 E10 E9 E8 E7 D1 D0 D15 D14 D4 D5 F12 G12 B15
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// D used : 15,14,..,..,..,10, 9, 8,..,.., 5, 4,..,.., 1, 0, // 9
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// D data : 15,14,..,..,..,10, 9, 8,..,..,..,..,..,.., 1, 0, // 7
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// | | | | |
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// E used : 15,14,13,12,11,10, 9, 8, 7,..,..,..,..,..,..,.., // 9
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// E data : 15,14,13,12,11,10, 9, 8, 7,..,..,..,..,..,..,.., // 9
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// | | | // Ruler on 8 & 16
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#define PD_DATA_BITS 0b1100011100000011
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#define PD_CTRL_BITS 0b0000000000110000 // PD5(FSMC_NWE),PD4(FSMC_NOE)
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#define PD_FSMC_BITS 0b1100011100110011
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#define PD_AFR0_MASK 0x00FF00FF
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#define PD_AFR0_FSMC 0x00CC00CC
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#define PD_AFR1_MASK 0xFF000FFF
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#define PD_AFR1_FSMC 0xCC000CCC
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// | | |
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#define PD_MODE_MASK 0xF03F0F0F // all FMSC MODE bits
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#define PD_MODE_FSMC 0xA02A0A0A // FMSC MODE values 10 alternate function
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#define PD_OSPD_FSMC 0x50150505 // FMSC OSPEED values 01 10MHz
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// | | |
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#define PE_DATA_BITS 0b1111111110000000
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#define PE_AFR0_MASK 0xF0000000
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#define PE_AFR0_FSMC 0xC0000000
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#define PE_AFR1_MASK 0xFFFFFFFF
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#define PE_AFR1_FSMC 0xCCCCCCCC
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// | | |
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#define PE_MODE_MASK 0xFFFFC000 // all FMSC MODE bits
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#define PE_MODE_FSMC 0xAAAA8000 // FMSC MODE values 10 alternate function
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#define PE_OSPD_FSMC 0x55554000 // FMSC OSPEED values 01 10MHz
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// | | |
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#define PF_CTRL_BITS 0b0001000000000000 // PF12(FSMC_A6)
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#define PF_AFR0_MASK 0x00000000
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#define PF_AFR0_FSMC 0x00000000
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#define PF_AFR1_MASK 0x000F0000
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#define PF_AFR1_FSMC 0x000C0000
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// | | |
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#define PF_MODE_MASK 0x03000000 // all FMSC MODE bits
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#define PF_MODE_FSMC 0x02000000 // FMSC MODE values 10 alternate function
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//#define PF_OSPD_FSMC 0x01000000 // FMSC OSPEED values 01 10MHz
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#define PF_OSPD_FSMC 0x02000000 // FMSC OSPEED values 10 100MHz
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// | | |
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#define PG_CTRL_BITS 0b0001000000000000 // PG12(FSMC_NE4)
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#define PG_AFR0_MASK 0x00000000
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#define PG_AFR0_FSMC 0x00000000
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#define PG_AFR1_MASK 0x000F0000
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#define PG_AFR1_FSMC 0x000C0000
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// | | |
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#define PG_MODE_MASK 0x03000000 // all FMSC MODE bits
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#define PG_MODE_FSMC 0x02000000 // FMSC MODE values 10 alternate function
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//#define PG_OSPD_FSMC 0x01000000 // FMSC OSPEED values 01 10MHz
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#define PG_OSPD_FSMC 0x02000000 // FMSC OSPEED values 10 100MHz
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//#define ADDSET 15 // (ADDSET+1)*6ns = CS to RW
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//#define DATAST 30 // (DATAST+1)*6ns = RW length
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#define ADDSET 5 // (ADDSET+1)*6ns = CS to RW
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#define DATAST 4 // (DATAST+1)*6ns = RW length
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// these are defined for STM32F103V in
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// ...\Arduino\hardware\STM32GENERIC\STM32\system\STM32F1\CMSIS_Inc\stm32f103xe.h
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// but not for STM32F407V/Z, maybe because relocatable
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#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
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#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
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#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
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#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
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#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
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#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
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#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
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#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
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#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
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// The memory address depends on the actual values of NEx and Ax pins used for RS and CS
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#define FSMC_A 6 // FSMC_A6
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// #define CommandAccess FSMC_BANK1_1 // FSMC_NE1
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// #define CommandAccess FSMC_BANK1_2 // FSMC_NE2
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// #define CommandAccess FSMC_BANK1_3 // FSMC_NE3
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#define CommandAccess FSMC_BANK1_4 // FSMC_NE4
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#define DataAccess (CommandAccess + (0x1 << FSMC_A)*2) // FSMC_A_OFFSET
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GxIO_STM32F407ZGx_FSMC::GxIO_STM32F407ZGx_FSMC(bool bl_active_high)
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{
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_cs = PG12; // FSMC_NE4
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_rs = PF12; // FSMC_A6
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_rst = 0; //
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_wr = PD5; // FSMC_NWE
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_rd = PD4; // FSMC_NOE
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_bl = PB15;
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_bl_active_high = bl_active_high;
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}
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void GxIO_STM32F407ZGx_FSMC::reset()
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{
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// _rst pin not available
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}
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void GxIO_STM32F407ZGx_FSMC::init()
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{
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RCC->AHB1ENR |= 0x00000078; // enable GPIOD, GPIOE, GPIOF and GPIOG interface clock
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volatile uint32_t t = RCC->AHB1ENR; // delay
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GPIOD->AFR[0] = ( GPIOD->AFR[0] & ~PD_AFR0_MASK) | PD_AFR0_FSMC;
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GPIOD->AFR[1] = ( GPIOD->AFR[1] & ~PD_AFR1_MASK) | PD_AFR1_FSMC;
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GPIOD->MODER = ( GPIOD->MODER & ~PD_MODE_MASK) | PD_MODE_FSMC;
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GPIOD->OSPEEDR = ( GPIOD->OSPEEDR & ~PD_MODE_MASK) | PD_OSPD_FSMC;
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GPIOD->OTYPER &= ~PD_MODE_MASK;
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GPIOD->PUPDR &= ~PD_MODE_MASK;
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GPIOE->AFR[0] = (GPIOE->AFR[0] & ~PE_AFR0_MASK) | PE_AFR0_FSMC;
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GPIOE->AFR[1] = (GPIOE->AFR[1] & ~PE_AFR1_MASK) | PE_AFR1_FSMC;
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GPIOE->MODER = (GPIOE->MODER & ~PE_MODE_MASK) | PE_MODE_FSMC;
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GPIOE->OSPEEDR = (GPIOE->OSPEEDR & ~PE_MODE_MASK) | PE_OSPD_FSMC;
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GPIOE->OTYPER &= ~PE_MODE_MASK;
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GPIOE->PUPDR &= ~PE_MODE_MASK;
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GPIOF->AFR[0] = (GPIOF->AFR[0] & ~PF_AFR0_MASK) | PF_AFR0_FSMC;
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GPIOF->AFR[1] = (GPIOF->AFR[1] & ~PF_AFR1_MASK) | PF_AFR1_FSMC;
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GPIOF->MODER = (GPIOF->MODER & ~PF_MODE_MASK) | PF_MODE_FSMC;
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GPIOF->OSPEEDR = (GPIOF->OSPEEDR & ~PF_MODE_MASK) | PF_OSPD_FSMC;
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GPIOF->OTYPER &= ~PF_MODE_MASK;
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GPIOF->PUPDR &= ~PF_MODE_MASK;
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GPIOG->AFR[0] = (GPIOG->AFR[0] & ~PG_AFR0_MASK) | PG_AFR0_FSMC;
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GPIOG->AFR[1] = (GPIOG->AFR[1] & ~PG_AFR1_MASK) | PG_AFR1_FSMC;
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GPIOG->MODER = (GPIOG->MODER & ~PG_MODE_MASK) | PG_MODE_FSMC;
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GPIOG->OSPEEDR = (GPIOG->OSPEEDR & ~PG_MODE_MASK) | PG_OSPD_FSMC;
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GPIOG->OTYPER &= ~PG_MODE_MASK;
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GPIOG->PUPDR &= ~PG_MODE_MASK;
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RCC->AHB3ENR |= 0x00000001;
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t = RCC->AHB1ENR; // delay
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(void)(t);
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FSMC_Bank1->BTCR[6] = 0x000010D9;
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FSMC_Bank1->BTCR[7] = (DATAST << 8) | ADDSET;
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digitalWrite(_rst, HIGH);
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pinMode(_rst, OUTPUT);
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digitalWrite(_bl, LOW);
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pinMode(_bl, OUTPUT);
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reset();
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}
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uint8_t GxIO_STM32F407ZGx_FSMC::readDataTransaction()
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{
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return *(uint8_t*)DataAccess;
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}
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uint16_t GxIO_STM32F407ZGx_FSMC::readData16Transaction()
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{
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return *(uint16_t*)DataAccess;
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}
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uint8_t GxIO_STM32F407ZGx_FSMC::readData()
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{
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return *(uint8_t*)DataAccess;
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}
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uint16_t GxIO_STM32F407ZGx_FSMC::readData16()
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{
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return *(uint16_t*)DataAccess;
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}
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uint32_t GxIO_STM32F407ZGx_FSMC::readRawData32(uint8_t part)
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{
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return *(uint16_t*)DataAccess;
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}
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void GxIO_STM32F407ZGx_FSMC::writeCommandTransaction(uint8_t c)
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{
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*(uint8_t*)CommandAccess = c;
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}
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void GxIO_STM32F407ZGx_FSMC::writeCommand16Transaction(uint16_t c)
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{
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*(uint16_t*)CommandAccess = c;
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}
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void GxIO_STM32F407ZGx_FSMC::writeDataTransaction(uint8_t d)
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{
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*(uint8_t*)DataAccess = d;
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}
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void GxIO_STM32F407ZGx_FSMC::writeData16Transaction(uint16_t d, uint32_t num)
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{
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while (num > 0)
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{
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*(uint16_t*)DataAccess = d;
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num--;
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}
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}
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void GxIO_STM32F407ZGx_FSMC::writeCommand(uint8_t c)
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{
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*(uint8_t*)CommandAccess = c;
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}
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void GxIO_STM32F407ZGx_FSMC::writeCommand16(uint16_t c)
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{
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*(uint16_t*)CommandAccess = c;
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}
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void GxIO_STM32F407ZGx_FSMC::writeData(uint8_t d)
|
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{
|
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*(uint8_t*)DataAccess = d;
|
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}
|
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void GxIO_STM32F407ZGx_FSMC::writeData(uint8_t* d, uint32_t num)
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{
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while (num > 0)
|
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{
|
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*(uint8_t*)DataAccess = *d;
|
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d++;
|
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num--;
|
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}
|
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}
|
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|
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void GxIO_STM32F407ZGx_FSMC::writeData16(uint16_t d, uint32_t num)
|
||||
{
|
||||
while (num > 0)
|
||||
{
|
||||
*(uint16_t*)DataAccess = d;
|
||||
num--;
|
||||
}
|
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}
|
||||
|
||||
void GxIO_STM32F407ZGx_FSMC::writeAddrMSBfirst(uint16_t d)
|
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{
|
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writeData16(d >> 8);
|
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writeData16(d & 0xFF);
|
||||
}
|
||||
|
||||
void GxIO_STM32F407ZGx_FSMC::startTransaction()
|
||||
{
|
||||
}
|
||||
|
||||
void GxIO_STM32F407ZGx_FSMC::endTransaction()
|
||||
{
|
||||
}
|
||||
|
||||
void GxIO_STM32F407ZGx_FSMC::selectRegister(bool rs_low)
|
||||
{
|
||||
}
|
||||
|
||||
void GxIO_STM32F407ZGx_FSMC::setBackLight(bool lit)
|
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{
|
||||
digitalWrite(_bl, (lit == _bl_active_high));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
// created by Jean-Marc Zingg to be the GxIO_STM32F407ZGM4_FSMC io class for the GxTFT library
|
||||
// adapted by fvanroie to work on STM32F407ZGT6 board
|
||||
//
|
||||
// License: GNU GENERAL PUBLIC LICENSE V3, see LICENSE
|
||||
//
|
||||
// this is the io class for STM32F407ZGM4 board with FMSC TFT connector, e.g. for
|
||||
// https://www.aliexpress.com/item/STM32-ARM-Cortex-M4-STM32F407ZGT6-development-board-STM32F4-core-board/32827402179.html?spm=a2g0s.9042311.0.0.49b14c4dUViVg4
|
||||
// and the matching TFTs of the same offer
|
||||
//
|
||||
// and e.g. for direct matching display
|
||||
// https://www.aliexpress.com/item/STM32F407ZET6-development-board-M4-STM32F4-core-board-arm-development-board-cortex-M4/32689262341.html?spm=a2g0s.9042311.0.0.49b14c4dUViVg4
|
||||
// https://www.aliexpress.com/item/32662835059.html?spm=a2g0o.cart.0.0.56f03c00mB9alZ&mp=1
|
||||
//
|
||||
// for pin information see the backside of the TFT, for the data pin to port pin mapping see FSMC pin table STM32F407V doc.
|
||||
//
|
||||
// this io class can be used with or adapted to other STM32F407V/Z processor boards with FSMC TFT connector.
|
||||
|
||||
|
||||
#ifndef _GxIO_STM32F407ZGX_FSMC_H_
|
||||
#define _GxIO_STM32F407ZGX_FSMC_H_
|
||||
|
||||
#include "../../GxIO.h"
|
||||
|
||||
#if defined(ARDUINO_ARCH_STM32) && (defined(STM32F407VE) || defined(STM32F407ZE) || defined(STM32F407ZG))
|
||||
|
||||
class GxIO_STM32F407ZGx_FSMC : public GxIO
|
||||
{
|
||||
public:
|
||||
GxIO_STM32F407ZGx_FSMC(bool bl_active_high = true);
|
||||
const char* name = "GxIO_STM32F407ZGx_FSMC";
|
||||
void reset();
|
||||
void init();
|
||||
uint8_t readDataTransaction();
|
||||
uint16_t readData16Transaction();
|
||||
uint8_t readData();
|
||||
uint16_t readData16();
|
||||
uint32_t readRawData32(uint8_t part); // debug purpose
|
||||
void writeCommandTransaction(uint8_t c);
|
||||
void writeCommand16Transaction(uint16_t c);
|
||||
void writeDataTransaction(uint8_t d);
|
||||
void writeData16Transaction(uint16_t d, uint32_t num = 1);
|
||||
void writeCommand(uint8_t c);
|
||||
void writeCommand16(uint16_t c);
|
||||
void writeData(uint8_t d);
|
||||
void writeData(uint8_t* d, uint32_t num);
|
||||
void writeData16(uint16_t d, uint32_t num = 1);
|
||||
void writeAddrMSBfirst(uint16_t d);
|
||||
void startTransaction();
|
||||
void endTransaction();
|
||||
void selectRegister(bool rs_low); // for generalized readData & writeData (RA8875)
|
||||
void setBackLight(bool lit);
|
||||
private:
|
||||
int8_t _cs, _rs, _rst, _wr, _rd, _bl; // Control lines
|
||||
bool _bl_active_high;
|
||||
};
|
||||
|
||||
#define GxIO_Class GxIO_STM32F407ZGx_FSMC
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -21,7 +21,15 @@
|
||||
*/
|
||||
#include "XPT2046_Touchscreen.h"
|
||||
|
||||
SPIClass spi(PB15, PB14, PB13); // SPI2
|
||||
// SPIClass spi(PB15, PB14, PB13); // SPI2
|
||||
#if defined(STM32F407ZG)
|
||||
#include "SoftSPI.h"
|
||||
extern SoftSPI xpt2046_spi;
|
||||
SoftSPI spi = xpt2046_spi;
|
||||
#else
|
||||
extern SPIClass xpt2046_spi;
|
||||
SPIClass spi = xpt2046_spi;
|
||||
#endif
|
||||
|
||||
#define Z_THRESHOLD 400
|
||||
#define Z_THRESHOLD_INT 75
|
||||
|
||||
@ -37,9 +37,14 @@ static void xpt2046_avg(int16_t * x, int16_t * y);
|
||||
int16_t avg_buf_x[XPT2046_AVG];
|
||||
int16_t avg_buf_y[XPT2046_AVG];
|
||||
uint8_t avg_last;
|
||||
#if defined(STM32F407ZG)
|
||||
#include "SoftSPI.h"
|
||||
SoftSPI xpt2046_spi(PF11, PB2, PB0);
|
||||
XPT2046_Touchscreen ts(PC13);
|
||||
#else
|
||||
SPIClass xpt2046_spi(PB15, PB14, PB13, PB12);
|
||||
XPT2046_Touchscreen ts(PB12);
|
||||
|
||||
#endif
|
||||
/**********************
|
||||
* MACROS
|
||||
**********************/
|
||||
|
||||
@ -29,9 +29,12 @@
|
||||
// I use it with ST-LINK-V2, Upload method "STLink[Automatic serial = SerialUSB]", USB disabled.
|
||||
// For Serial I use a Serial to USB converter on PA9, PA10, "SerialUART1".
|
||||
// https://github.com/danieleff/STM32GENERIC
|
||||
#if defined(STM32F407ZG)
|
||||
#include "GxIO/STM32GENERIC/GxIO_STM32F407ZGx_FSMC/GxIO_STM32F407ZGx_FSMC.h"
|
||||
#else
|
||||
#include "GxIO/STM32DUINO/GxIO_STM32F4_FSMC/GxIO_STM32F4_FSMC.h"
|
||||
//#include "myTFTs/my_3.2_TFT_320x240_ILI9341_STM32F407ZGM4_FSMC.h"
|
||||
|
||||
#endif
|
||||
// #include "../GxIO/STM32GENERIC/GxIO_STM32F407ZGM4_FSMC/GxIO_STM32F407ZGM4_FSMC.h"
|
||||
//#include "../GxIO/STM32DUINO/GxIO_STM32F4_FSMC/GxIO_STM32F4_FSMC.h"
|
||||
#include "GxCTRL/GxCTRL_ILI9341/GxCTRL_ILI9341.h" // 240x320
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user