From 162084082e92384d40c1789457eb574f8790ea87 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 22:18:35 +0100 Subject: [PATCH] Fix boot from 128GB Micron eMMC on ODROID-N2(+) (#1064) --- ...ARM-meson-isolate-loading-of-socinfo.patch | 6 +- .../0002-meson-Add-board_rev-to-env.patch | 10 +- ...change-clock-phase-value-on-SM1-SoCs.patch | 103 ++++++++++++++++++ ...change-clock-phase-value-on-AGX-SoCs.patch | 73 +++++++++++++ 4 files changed, 184 insertions(+), 8 deletions(-) create mode 100644 buildroot-external/board/hardkernel/patches/uboot/0003-mmc-meson-gx-change-clock-phase-value-on-SM1-SoCs.patch create mode 100644 buildroot-external/board/hardkernel/patches/uboot/0004-mmc-meson-gx-change-clock-phase-value-on-AGX-SoCs.patch diff --git a/buildroot-external/board/hardkernel/patches/uboot/0001-ARM-meson-isolate-loading-of-socinfo.patch b/buildroot-external/board/hardkernel/patches/uboot/0001-ARM-meson-isolate-loading-of-socinfo.patch index da7d8b910..cbc1c7a2c 100644 --- a/buildroot-external/board/hardkernel/patches/uboot/0001-ARM-meson-isolate-loading-of-socinfo.patch +++ b/buildroot-external/board/hardkernel/patches/uboot/0001-ARM-meson-isolate-loading-of-socinfo.patch @@ -1,8 +1,8 @@ -From f9877c2895d6c05710a828d0cd46d9f25626b070 Mon Sep 17 00:00:00 2001 -Message-Id: +From 526ccae8321b9b48925c44999611c3c5a374328e Mon Sep 17 00:00:00 2001 +Message-Id: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch> From: Stefan Agner Date: Mon, 31 Aug 2020 13:40:18 +0200 -Subject: [PATCH 1/2] ARM: meson: isolate loading of socinfo +Subject: [PATCH 1/4] ARM: meson: isolate loading of socinfo Move loading of socinfo into a separate function so the value can be reused later. diff --git a/buildroot-external/board/hardkernel/patches/uboot/0002-meson-Add-board_rev-to-env.patch b/buildroot-external/board/hardkernel/patches/uboot/0002-meson-Add-board_rev-to-env.patch index 6f34689c9..7a314ac8f 100644 --- a/buildroot-external/board/hardkernel/patches/uboot/0002-meson-Add-board_rev-to-env.patch +++ b/buildroot-external/board/hardkernel/patches/uboot/0002-meson-Add-board_rev-to-env.patch @@ -1,10 +1,10 @@ -From 31e32295dc261032d7f5540a0b7f79a4f5a5b807 Mon Sep 17 00:00:00 2001 -Message-Id: <31e32295dc261032d7f5540a0b7f79a4f5a5b807.1606490648.git.stefan@agner.ch> -In-Reply-To: -References: +From 2b2ad8c105cbb5fb48c3c5f0512c031f6533d522 Mon Sep 17 00:00:00 2001 +Message-Id: <2b2ad8c105cbb5fb48c3c5f0512c031f6533d522.1607361661.git.stefan@agner.ch> +In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch> +References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch> From: Pascal Vizeli Date: Tue, 4 Aug 2020 13:50:57 +0000 -Subject: [PATCH 2/2] meson: Add board_rev to env +Subject: [PATCH 2/4] meson: Add board_rev to env Signed-off-by: Pascal Vizeli Signed-off-by: Stefan Agner diff --git a/buildroot-external/board/hardkernel/patches/uboot/0003-mmc-meson-gx-change-clock-phase-value-on-SM1-SoCs.patch b/buildroot-external/board/hardkernel/patches/uboot/0003-mmc-meson-gx-change-clock-phase-value-on-SM1-SoCs.patch new file mode 100644 index 000000000..3e710bfe3 --- /dev/null +++ b/buildroot-external/board/hardkernel/patches/uboot/0003-mmc-meson-gx-change-clock-phase-value-on-SM1-SoCs.patch @@ -0,0 +1,103 @@ +From 77241850a471015eb18e1b3cb124fce71c7b59c8 Mon Sep 17 00:00:00 2001 +Message-Id: <77241850a471015eb18e1b3cb124fce71c7b59c8.1607361661.git.stefan@agner.ch> +In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch> +References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch> +From: Neil Armstrong +Date: Wed, 11 Nov 2020 08:22:10 +0900 +Subject: [PATCH 3/4] mmc: meson-gx: change clock phase value on SM1 SoCs + +Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's +working fine over 50MHz on Amlogic SM1 SoCs. +Since Other Amlogic SoCs doens't report an issue, phase value is using +to 180' by default. + +To distinguish which value is used adds an u-boot only sm1 compatible. + +In future, it needs to find what value is a proper about each SoCs. + +Signed-off-by: Neil Armstrong +Signed-off-by: Jaehoon Chung +Tested-by: Anand Moon +--- + arch/arm/include/asm/arch-meson/sd_emmc.h | 5 +++++ + drivers/mmc/meson_gx_mmc.c | 27 +++++++++++++++++++---- + 2 files changed, 28 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h +index 1e9f8cf498..cb16f75fc6 100644 +--- a/arch/arm/include/asm/arch-meson/sd_emmc.h ++++ b/arch/arm/include/asm/arch-meson/sd_emmc.h +@@ -12,6 +12,11 @@ + #endif + + ++enum meson_gx_mmc_compatible { ++ MMC_COMPATIBLE_GX, ++ MMC_COMPATIBLE_SM1, ++}; ++ + #define SDIO_PORT_A 0 + #define SDIO_PORT_B 1 + #define SDIO_PORT_C 2 +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index 719dd1e5e5..5facbfdd9a 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -17,6 +17,14 @@ + #include + #include + ++bool meson_gx_mmc_is_compatible(struct udevice *dev, ++ enum meson_gx_mmc_compatible family) ++{ ++ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev); ++ ++ return compat == family; ++} ++ + static inline void *get_regbase(const struct mmc *mmc) + { + struct meson_mmc_platdata *pdata = mmc->priv; +@@ -42,6 +50,8 @@ static void meson_mmc_config_clock(struct mmc *mmc) + if (!mmc->clock) + return; + ++ /* TOFIX This should use the proper clock taken from DT */ ++ + /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ + if (mmc->clock > 16000000) { + clk = SD_EMMC_CLKSRC_DIV2; +@@ -52,8 +62,16 @@ static void meson_mmc_config_clock(struct mmc *mmc) + } + clk_div = DIV_ROUND_UP(clk, mmc->clock); + +- /* 180 phase core clock */ +- meson_mmc_clk |= CLK_CO_PHASE_180; ++ /* ++ * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180 ++ * If CLK_CO_PHASE_270 is used, it's more stable than other. ++ * Other SoCs use CLK_CO_PHASE_180 by default. ++ * It needs to find what is a proper value about each SoCs. ++ */ ++ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) ++ meson_mmc_clk |= CLK_CO_PHASE_270; ++ else ++ meson_mmc_clk |= CLK_CO_PHASE_180; + + /* 180 phase tx clock */ + meson_mmc_clk |= CLK_TX_PHASE_000; +@@ -308,8 +326,9 @@ int meson_mmc_bind(struct udevice *dev) + } + + static const struct udevice_id meson_mmc_match[] = { +- { .compatible = "amlogic,meson-gx-mmc" }, +- { .compatible = "amlogic,meson-axg-mmc" }, ++ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, ++ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, ++ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, + { /* sentinel */ } + }; + +-- +2.29.2 + diff --git a/buildroot-external/board/hardkernel/patches/uboot/0004-mmc-meson-gx-change-clock-phase-value-on-AGX-SoCs.patch b/buildroot-external/board/hardkernel/patches/uboot/0004-mmc-meson-gx-change-clock-phase-value-on-AGX-SoCs.patch new file mode 100644 index 000000000..69a5f9557 --- /dev/null +++ b/buildroot-external/board/hardkernel/patches/uboot/0004-mmc-meson-gx-change-clock-phase-value-on-AGX-SoCs.patch @@ -0,0 +1,73 @@ +From 179546705437886904fd8215bf2e6fbe7d731fb9 Mon Sep 17 00:00:00 2001 +Message-Id: <179546705437886904fd8215bf2e6fbe7d731fb9.1607361661.git.stefan@agner.ch> +In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch> +References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch> +From: Stefan Agner +Date: Mon, 7 Dec 2020 17:55:28 +0100 +Subject: [PATCH 4/4] mmc: meson-gx: change clock phase value on AGX SoCs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Amlogic AGX SoCs seem to have issue communicating with some eMMC +devices (in particular with a Micron 128GB eMMC 5.1). The device +is detected with 1-bit bus width, and at higher temperature loading +pretty much anything from the storage fails: (e.g. fs_devread read error +- block). + +When phase is set to 270° it is detected with 8-bit bus width and is +working fine accross all temperatures. + +Signed-off-by: Stefan Agner +--- + arch/arm/include/asm/arch-meson/sd_emmc.h | 1 + + drivers/mmc/meson_gx_mmc.c | 9 +++++---- + 2 files changed, 6 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h +index cb16f75fc6..db5e058098 100644 +--- a/arch/arm/include/asm/arch-meson/sd_emmc.h ++++ b/arch/arm/include/asm/arch-meson/sd_emmc.h +@@ -14,6 +14,7 @@ + + enum meson_gx_mmc_compatible { + MMC_COMPATIBLE_GX, ++ MMC_COMPATIBLE_AGX, + MMC_COMPATIBLE_SM1, + }; + +diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c +index 5facbfdd9a..2c27113c10 100644 +--- a/drivers/mmc/meson_gx_mmc.c ++++ b/drivers/mmc/meson_gx_mmc.c +@@ -64,14 +64,15 @@ static void meson_mmc_config_clock(struct mmc *mmc) + + /* + * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180 ++ * AGX SoCs don't work reliable with some eMMCs with CLK_CO_PHASE_180 + * If CLK_CO_PHASE_270 is used, it's more stable than other. + * Other SoCs use CLK_CO_PHASE_180 by default. + * It needs to find what is a proper value about each SoCs. + */ +- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1)) +- meson_mmc_clk |= CLK_CO_PHASE_270; +- else ++ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_GX)) + meson_mmc_clk |= CLK_CO_PHASE_180; ++ else ++ meson_mmc_clk |= CLK_CO_PHASE_270; + + /* 180 phase tx clock */ + meson_mmc_clk |= CLK_TX_PHASE_000; +@@ -327,7 +328,7 @@ int meson_mmc_bind(struct udevice *dev) + + static const struct udevice_id meson_mmc_match[] = { + { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX }, +- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX }, ++ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AGX }, + { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 }, + { /* sentinel */ } + }; +-- +2.29.2 +