diff --git a/.github/workflows/matrix.json b/.github/workflows/matrix.json index d258ac594..a888f53d8 100644 --- a/.github/workflows/matrix.json +++ b/.github/workflows/matrix.json @@ -41,6 +41,12 @@ "architecture": "aarch64", "label": "board/odroid" }, + { + "id": "odroid-m1s", + "defconfig": "odroid_m1s", + "architecture": "aarch64", + "label": "board/odroid" + }, { "id": "odroid-n2", "defconfig": "odroid_n2", diff --git a/buildroot-external/board/hardkernel/odroid-m1s/boot-env.txt b/buildroot-external/board/hardkernel/odroid-m1s/boot-env.txt new file mode 100644 index 000000000..e69de29bb diff --git a/buildroot-external/board/hardkernel/odroid-m1s/cmdline.txt b/buildroot-external/board/hardkernel/odroid-m1s/cmdline.txt new file mode 100644 index 000000000..e69de29bb diff --git a/buildroot-external/board/hardkernel/odroid-m1s/hassos-hook.sh b/buildroot-external/board/hardkernel/odroid-m1s/hassos-hook.sh new file mode 100755 index 000000000..14c703f38 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/hassos-hook.sh @@ -0,0 +1,24 @@ +#!/bin/bash +# shellcheck disable=SC2155 + +function hassos_pre_image() { + local BOOT_DATA="$(path_boot_dir)" + local SPL_IMG="$(path_spl_img)" + + cp "${BINARIES_DIR}/boot.scr" "${BOOT_DATA}/boot.scr" + cp "${BINARIES_DIR}"/*.dtb "${BOOT_DATA}/" + + cp "${BOARD_DIR}/boot-env.txt" "${BOOT_DATA}/haos-config.txt" + cp "${BOARD_DIR}/cmdline.txt" "${BOOT_DATA}/cmdline.txt" + + # SPL + create_spl_image + + dd if="${BINARIES_DIR}/u-boot-rockchip.bin" of="${SPL_IMG}" conv=notrunc bs=512 seek=64 +} + + +function hassos_post_image() { + convert_disk_image_xz +} + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/kernel.config b/buildroot-external/board/hardkernel/odroid-m1s/kernel.config new file mode 100644 index 000000000..1087ac0e6 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/kernel.config @@ -0,0 +1,12 @@ +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y + +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_SENSORS_GPIO_FAN=y + +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y + +CONFIG_MMC_SDHCI_OF_DWCMSHC=y + +# CONFIG_DW_WATCHDOG is not set diff --git a/buildroot-external/board/hardkernel/odroid-m1s/meta b/buildroot-external/board/hardkernel/odroid-m1s/meta new file mode 100644 index 000000000..b73bb38e0 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/meta @@ -0,0 +1,12 @@ +BOARD_ID=odroid-m1s +BOARD_NAME="Hardkernel ODROID-M1S" +CHASSIS=embedded +BOOTLOADER=uboot +KERNEL_FILE=Image +BOOT_SYS=gpt +BOOT_SIZE=16M +BOOT_SPL=true +BOOT_SPL_SIZE=16M +BOOT_ENV_SIZE=0x8000 +SUPERVISOR_MACHINE=odroid-m1 +SUPERVISOR_ARCH=aarch64 diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0001-arm64-dts-rockchip-Import-Hardkernel-ODROID-M1S-boar.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0001-arm64-dts-rockchip-Import-Hardkernel-ODROID-M1S-boar.patch new file mode 100644 index 000000000..3b6d9963e --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0001-arm64-dts-rockchip-Import-Hardkernel-ODROID-M1S-boar.patch @@ -0,0 +1,896 @@ +From 83dadbe0a615f6fc7550dec98dee938647050990 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Sun, 28 Jan 2024 18:52:26 +1100 +Subject: [PATCH] arm64: dts: rockchip: Import Hardkernel ODROID-M1S board + +Odroid-m1s is in the process of being upstreamed. +For now sync dts for Odroid-m1s: +https://github.com/tobetter/linux/blob/ae33b445578884c70d7bfc5d6d519de4db815ccd/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3566-odroid-m1s.dts | 861 ++++++++++++++++++ + 2 files changed, 862 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 8c15593c0ca4..362359684ed0 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +new file mode 100644 +index 000000000000..1cad9217c374 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +@@ -0,0 +1,861 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2023 Hardkernel Co., Ltd. ++ * ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++ ++#include "rk3566.dtsi" ++ ++/ { ++ model = "Hardkernel ODROID-M1S"; ++ compatible = "rockchip,rk3566-odroid-m1", "rockchip,rk3566"; ++ ++ aliases { ++ ethernet1 = &gmac1; ++ i2c0 = &i2c3; ++ i2c3 = &i2c0; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ serial0 = &uart1; ++ serial1 = &uart0; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ gmac1_clkin: external-gmac1-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac1_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ status = "okay"; ++ ++ red_led: red { ++ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ function = LED_FUNCTION_POWER; ++ color = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power_en>; ++ }; ++ blue_led: blue { ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ function = LED_FUNCTION_HEARTBEAT; ++ color = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_work_en>; ++ }; ++ }; ++ ++ pcie20_3v3: pcie20-3v3-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie20_3v3_en>; ++ regulator-name = "pcie20_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ rk809-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "ODROID-M1-FRONT"; ++ simple-audio-card,mclk-fs = <256>; ++ status = "okay"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v_dcin: vcc5v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v_dcin>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en>; ++ regulator-name = "vcc5v0_usb_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb3-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en>; ++ regulator-name = "vcc5v0_usb_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy1 { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&display_subsystem { ++ status = "okay"; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_3v3>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 20ms, 100ms for rtl8211f */ ++ snps,reset-delays-us = <0 20000 100000>; ++ tx_delay = <0x4f>; ++ rx_delay = <0x2d>; ++ phy-handle = <&rgmii_phy1>; ++ status = "okay"; ++}; ++ ++&gpio0 { ++ gpio-line-names = ++ /* GPIO0_A0-A3 */ ++ "", "", "", "", ++ /* GPIO0_A4-A7 */ ++ "", "", "", "", ++ ++ /* GPIO0_B0-B3 */ ++ "", "", "", "PIN_28", ++ /* GPIO0_B4-B7 */ ++ "PIN_27", "PIN_33", "PIN_7", "", ++ ++ /* GPIO0_C0-C3 */ ++ "PIN_11", "PIN_13", "PIN_15", "", ++ /* GPIO0_C4-C7 */ ++ "", "", "", "", ++ ++ /* GPIO0_D0-D3 */ ++ "", "", "", "", ++ /* GPIO0_D4-D7 */ ++ "", "", "", ""; ++}; ++ ++&gpio1 { ++ gpio-line-names = ++ /* GPIO1_A0-A3 */ ++ "", "", "", "", ++ /* GPIO1_A4-A7 */ ++ "", "", "", "", ++ ++ /* GPIO1_B0-B3 */ ++ "", "", "", "", ++ /* GPIO1_B4-B7 */ ++ "", "", "", "", ++ ++ /* GPIO1_C0-C3 */ ++ "", "", "", "", ++ /* GPIO1_C4-C7 */ ++ "", "", "", "", ++ ++ /* GPIO1_D0-D3 */ ++ "", "", "", "", ++ /* GPIO1_D4-D7 */ ++ "", "", "", ""; ++}; ++ ++&gpio2 { ++ gpio-line-names = ++ /* GPIO2_A0-A3 */ ++ "", "", "", "PIN_10", ++ /* GPIO2_A4-A7 */ ++ "PIN_8", "PINN_35", "PIN_36", "PIN_12", ++ ++ /* GPIO2_B0-B3 */ ++ "PIN_22", "PIN_26", "PIN_32", "", ++ /* GPIO2_B4-B7 */ ++ "", "PIN_16", "PIN_18", "PIN_31", ++ ++ /* GPIO2_C0-C3 */ ++ "PIN_29", "", "", "", ++ /* GPIO2_C4-C7 */ ++ "", "", "", "", ++ ++ /* GPIO2_D0-D3 */ ++ "", "", "", "", ++ /* GPIO2_D4-D7 */ ++ "", "", "", ""; ++}; ++ ++&gpio3 { ++ gpio-line-names = ++ /* GPIO3_A0-A3 */ ++ "", "PIN_24", "", "", ++ /* GPIO3_A4-A7 */ ++ "", "", "", "", ++ ++ /* GPIO3_B0-B3 */ ++ "", "", "", "EXTPIN_13", ++ /* GPIO3_B4-B7 */ ++ "EXTPIN_14", "PIN_5", "PIN_3", "", ++ ++ /* GPIO3_C0-C3 */ ++ "", "PIN_19", "PIN_21", "PIN_23", ++ /* GPIO3_C4-C7 */ ++ "EXTPIN_11", "EXTPIN_12", "", "", ++ ++ /* GPIO3_D0-D3 */ ++ "", "", "", "", ++ /* GPIO3_D4-D7 */ ++ "", "", "", ""; ++}; ++ ++&gpio4 { ++ gpio-line-names = ++ /* GPIO4_A0-A3 */ ++ "", "", "", "", ++ /* GPIO4_A4-A7 */ ++ "", "", "", "", ++ ++ /* GPIO4_B0-B3 */ ++ "", "", "", "", ++ /* GPIO4_B4-B7 */ ++ "", "", "", "", ++ ++ /* GPIO4_C0-C3 */ ++ "", "", "", "", ++ /* GPIO4_C4-C7 */ ++ "", "", "", "", ++ ++ /* GPIO4_D0-D3 */ ++ "", "", "", "", ++ /* GPIO4_D4-D7 */ ++ "", "", "", ""; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ simple-audio-card,name = "ODROID-M1-HDMI"; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ vdd_cpu: tcs4525@1c { ++ compatible = "tcs,tcs452x"; ++ reg = <0x1c>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_cpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <2300>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ #clock-cells = <1>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT_TX>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; ++ rockchip,system-power-controller; ++ #sound-dai-cells = <0>; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_logic"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_gpu"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc_ddr"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_npu"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda0v9_image"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda_0v9"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda0v9_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vccio_acodec"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_ddr: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_image"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc_3v3"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc3v3_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "disabled"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2m1_xfer>; ++ ++ clock-frequency = <400000>; ++}; ++ ++&i2c3 { ++ status = "disabled"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3m1_xfer>; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ status = "okay"; ++ rockchip,clk-trcm = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++}; ++ ++&mdio1 { ++ rgmii_phy1: phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ }; ++}; ++ ++&pcie2x1 { ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&pcie20_3v3>; ++ pinctrl-0 = <&pcie20m2_pins>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gmac1 { ++ gmac1m1_miim: gmac1m1-miim { ++ rockchip,pins = ++ /* gmac1_mdcm1 */ ++ <4 RK_PB6 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_mdiom1 */ ++ <4 RK_PB7 3 &pcfg_pull_none_drv_level_15>; ++ }; ++ ++ gmac1m1_clkinout: gmac1m1-clkinout { ++ rockchip,pins = ++ /* gmac1_mclkinoutm1 */ ++ <4 RK_PC1 3 &pcfg_pull_none_drv_level_15>; ++ }; ++ ++ gmac1m1_rx_bus2: gmac1m1-rx-bus2 { ++ rockchip,pins = ++ /* gmac1_rxd0m1 */ ++ <4 RK_PA7 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_rxd1m1 */ ++ <4 RK_PB0 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_rxdvcrsm1 */ ++ <4 RK_PB1 3 &pcfg_pull_none_drv_level_15>; ++ }; ++ ++ gmac1m1_tx_bus2: gmac1m1-tx-bus2 { ++ rockchip,pins = ++ /* gmac1_txd0m1 */ ++ <4 RK_PA4 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_txd1m1 */ ++ <4 RK_PA5 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_txenm1 */ ++ <4 RK_PA6 3 &pcfg_pull_none_drv_level_15>; ++ }; ++ ++ gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { ++ rockchip,pins = ++ /* gmac1_rxclkm1 */ ++ <4 RK_PA3 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_txclkm1 */ ++ <4 RK_PA0 3 &pcfg_pull_none_drv_level_15>; ++ }; ++ ++ gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { ++ rockchip,pins = ++ /* gmac1_rxd2m1 */ ++ <4 RK_PA1 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_rxd3m1 */ ++ <4 RK_PA2 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_txd2m1 */ ++ <3 RK_PD6 3 &pcfg_pull_none_drv_level_15>, ++ /* gmac1_txd3m1 */ ++ <3 RK_PD7 3 &pcfg_pull_none_drv_level_15>; ++ }; ++ }; ++ ++ leds { ++ led_power_en: led_power_en { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_work_en: led_work_en { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie20_3v3_en: pcie20-3v3-en { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic_int { ++ rockchip,pins = ++ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_otg_en: vcc5v0-otg-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_host_en: vcc5v0-usb3-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_3v3>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "disabled"; ++ pinctrl-0 = <&pwm1m1_pins>; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&uart1 { ++ dma-names = "tx", "rx"; ++ /* uart1 uart1-with-ctsrts */ ++ pinctrl-0 = <&uart1m1_xfer>; ++ pinctrl-1 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; ++ status = "disabled"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ vbus-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0002-arm64-dts-clean-up-as-required-for-mainline-linux.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0002-arm64-dts-clean-up-as-required-for-mainline-linux.patch new file mode 100644 index 000000000..ead22352b --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0002-arm64-dts-clean-up-as-required-for-mainline-linux.patch @@ -0,0 +1,335 @@ +From eb02261dd6c88a7fcf3c28e59a7976905815fa6b Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Sun, 28 Jan 2024 18:55:57 +1100 +Subject: [PATCH] arm64: dts: clean up as required for mainline linux + +--- + .../boot/dts/rockchip/rk3566-odroid-m1s.dts | 212 +++--------------- + 1 file changed, 27 insertions(+), 185 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +index 1cad9217c374..cbf2495901d7 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +@@ -18,12 +18,8 @@ / { + + aliases { + ethernet1 = &gmac1; +- i2c0 = &i2c3; +- i2c3 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc0; +- serial0 = &uart1; +- serial1 = &uart0; + }; + + chosen: chosen { +@@ -52,7 +48,7 @@ leds { + compatible = "gpio-leds"; + status = "okay"; + +- red_led: red { ++ red_led: led-0 { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + function = LED_FUNCTION_POWER; +@@ -60,7 +56,7 @@ red_led: red { + pinctrl-names = "default"; + pinctrl-0 = <&led_power_en>; + }; +- blue_led: blue { ++ blue_led: led-1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; +@@ -97,6 +93,25 @@ simple-audio-card,codec { + }; + }; + ++ spdif_dit: spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spdif_sound: spdif-sound { ++ compatible = "simple-audio-card"; ++ status = "disabled"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; ++ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; +@@ -164,7 +179,6 @@ vcc5v0_usb_host: vcc5v0-usb3-regulator { + }; + + &combphy1 { +- phy-supply = <&vcc5v0_usb_host>; + status = "okay"; + }; + +@@ -215,121 +229,6 @@ &gmac1m1_rgmii_bus + status = "okay"; + }; + +-&gpio0 { +- gpio-line-names = +- /* GPIO0_A0-A3 */ +- "", "", "", "", +- /* GPIO0_A4-A7 */ +- "", "", "", "", +- +- /* GPIO0_B0-B3 */ +- "", "", "", "PIN_28", +- /* GPIO0_B4-B7 */ +- "PIN_27", "PIN_33", "PIN_7", "", +- +- /* GPIO0_C0-C3 */ +- "PIN_11", "PIN_13", "PIN_15", "", +- /* GPIO0_C4-C7 */ +- "", "", "", "", +- +- /* GPIO0_D0-D3 */ +- "", "", "", "", +- /* GPIO0_D4-D7 */ +- "", "", "", ""; +-}; +- +-&gpio1 { +- gpio-line-names = +- /* GPIO1_A0-A3 */ +- "", "", "", "", +- /* GPIO1_A4-A7 */ +- "", "", "", "", +- +- /* GPIO1_B0-B3 */ +- "", "", "", "", +- /* GPIO1_B4-B7 */ +- "", "", "", "", +- +- /* GPIO1_C0-C3 */ +- "", "", "", "", +- /* GPIO1_C4-C7 */ +- "", "", "", "", +- +- /* GPIO1_D0-D3 */ +- "", "", "", "", +- /* GPIO1_D4-D7 */ +- "", "", "", ""; +-}; +- +-&gpio2 { +- gpio-line-names = +- /* GPIO2_A0-A3 */ +- "", "", "", "PIN_10", +- /* GPIO2_A4-A7 */ +- "PIN_8", "PINN_35", "PIN_36", "PIN_12", +- +- /* GPIO2_B0-B3 */ +- "PIN_22", "PIN_26", "PIN_32", "", +- /* GPIO2_B4-B7 */ +- "", "PIN_16", "PIN_18", "PIN_31", +- +- /* GPIO2_C0-C3 */ +- "PIN_29", "", "", "", +- /* GPIO2_C4-C7 */ +- "", "", "", "", +- +- /* GPIO2_D0-D3 */ +- "", "", "", "", +- /* GPIO2_D4-D7 */ +- "", "", "", ""; +-}; +- +-&gpio3 { +- gpio-line-names = +- /* GPIO3_A0-A3 */ +- "", "PIN_24", "", "", +- /* GPIO3_A4-A7 */ +- "", "", "", "", +- +- /* GPIO3_B0-B3 */ +- "", "", "", "EXTPIN_13", +- /* GPIO3_B4-B7 */ +- "EXTPIN_14", "PIN_5", "PIN_3", "", +- +- /* GPIO3_C0-C3 */ +- "", "PIN_19", "PIN_21", "PIN_23", +- /* GPIO3_C4-C7 */ +- "EXTPIN_11", "EXTPIN_12", "", "", +- +- /* GPIO3_D0-D3 */ +- "", "", "", "", +- /* GPIO3_D4-D7 */ +- "", "", "", ""; +-}; +- +-&gpio4 { +- gpio-line-names = +- /* GPIO4_A0-A3 */ +- "", "", "", "", +- /* GPIO4_A4-A7 */ +- "", "", "", "", +- +- /* GPIO4_B0-B3 */ +- "", "", "", "", +- /* GPIO4_B4-B7 */ +- "", "", "", "", +- +- /* GPIO4_C0-C3 */ +- "", "", "", "", +- /* GPIO4_C4-C7 */ +- "", "", "", "", +- +- /* GPIO4_D0-D3 */ +- "", "", "", "", +- /* GPIO4_D4-D7 */ +- "", "", "", ""; +-}; +- + &gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +@@ -368,7 +267,6 @@ vdd_cpu: tcs4525@1c { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; +- regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; +@@ -409,7 +307,6 @@ vdd_logic: DCDC_REG1 { + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; +- regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; +@@ -423,7 +320,6 @@ vdd_gpu: DCDC_REG2 { + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; +- regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; +@@ -447,7 +343,6 @@ vdd_npu: DCDC_REG4 { + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; +- regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; +@@ -587,6 +482,9 @@ regulator-state-mem { + }; + }; + }; ++ codec { ++ rockchip,mic-in-differential; ++ }; + }; + }; + +@@ -611,7 +509,7 @@ &i2s0_8ch { + + &i2s1_8ch { + status = "okay"; +- rockchip,clk-trcm = <1>; ++ rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx +@@ -620,7 +518,7 @@ &i2s1m0_sdi0 + }; + + &mdio1 { +- rgmii_phy1: phy@0 { ++ rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +@@ -634,62 +532,6 @@ &pcie2x1 { + }; + + &pinctrl { +- gmac1 { +- gmac1m1_miim: gmac1m1-miim { +- rockchip,pins = +- /* gmac1_mdcm1 */ +- <4 RK_PB6 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_mdiom1 */ +- <4 RK_PB7 3 &pcfg_pull_none_drv_level_15>; +- }; +- +- gmac1m1_clkinout: gmac1m1-clkinout { +- rockchip,pins = +- /* gmac1_mclkinoutm1 */ +- <4 RK_PC1 3 &pcfg_pull_none_drv_level_15>; +- }; +- +- gmac1m1_rx_bus2: gmac1m1-rx-bus2 { +- rockchip,pins = +- /* gmac1_rxd0m1 */ +- <4 RK_PA7 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_rxd1m1 */ +- <4 RK_PB0 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_rxdvcrsm1 */ +- <4 RK_PB1 3 &pcfg_pull_none_drv_level_15>; +- }; +- +- gmac1m1_tx_bus2: gmac1m1-tx-bus2 { +- rockchip,pins = +- /* gmac1_txd0m1 */ +- <4 RK_PA4 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_txd1m1 */ +- <4 RK_PA5 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_txenm1 */ +- <4 RK_PA6 3 &pcfg_pull_none_drv_level_15>; +- }; +- +- gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { +- rockchip,pins = +- /* gmac1_rxclkm1 */ +- <4 RK_PA3 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_txclkm1 */ +- <4 RK_PA0 3 &pcfg_pull_none_drv_level_15>; +- }; +- +- gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { +- rockchip,pins = +- /* gmac1_rxd2m1 */ +- <4 RK_PA1 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_rxd3m1 */ +- <4 RK_PA2 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_txd2m1 */ +- <3 RK_PD6 3 &pcfg_pull_none_drv_level_15>, +- /* gmac1_txd3m1 */ +- <3 RK_PD7 3 &pcfg_pull_none_drv_level_15>; +- }; +- }; +- + leds { + led_power_en: led_power_en { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -825,7 +667,7 @@ &usb2phy0_host { + }; + + &usb2phy0_otg { +- vbus-supply = <&vcc5v0_usb_otg>; ++ phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; + }; + +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0003-arm64-dts-fix-vdd_cpu-regulator-for-mainline.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0003-arm64-dts-fix-vdd_cpu-regulator-for-mainline.patch new file mode 100644 index 000000000..654311e45 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0003-arm64-dts-fix-vdd_cpu-regulator-for-mainline.patch @@ -0,0 +1,43 @@ +From 641ec8e05726d42c8ec7fa3bda1d8a64f126b475 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Fri, 12 Jan 2024 22:32:56 +1100 +Subject: [PATCH] arm64: dts: fix vdd_cpu regulator for mainline + +--- + .../arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +index cbf2495901d7..a5d9216b544b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +@@ -259,18 +259,19 @@ &hdmi_sound { + + &i2c0 { + status = "okay"; +- vdd_cpu: tcs4525@1c { +- compatible = "tcs,tcs452x"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; + reg = <0x1c>; +- vin-supply = <&vcc5v0_sys>; +- regulator-compatible = "fan53555-reg"; ++ fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; +- fcs,suspend-voltage-selector = <1>; +- regulator-boot-on; +- regulator-always-on; ++ vin-supply = <&vcc3v3_sys>; ++ + regulator-state-mem { + regulator-off-in-suspend; + }; +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0005-Remove-deprecated-snps-reset-properties.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0005-Remove-deprecated-snps-reset-properties.patch new file mode 100644 index 000000000..7e0584d9d --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/linux/0005-Remove-deprecated-snps-reset-properties.patch @@ -0,0 +1,51 @@ +From b4d16cd88ec2701dcb15b9519a79288ea5d2bfec Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Sat, 3 Feb 2024 23:40:16 +1100 +Subject: [PATCH] Remove deprecated snps,reset properties + +--- + arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts | 11 +++++------ + 1 file changed, 5 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +index b8adfd7024f9..e755d00b1d4f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-odroid-m1s.dts +@@ -192,8 +192,9 @@ &gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; +- phy-supply = <&vcc_3v3>; ++ phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; ++ phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 +@@ -201,13 +202,8 @@ &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; +- snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- /* Reset time is 20ms, 100ms for rtl8211f */ +- snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x2d>; +- phy-handle = <&rgmii_phy1>; + status = "okay"; + }; + +@@ -504,6 +500,9 @@ &mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; + +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0001-board-rockchip-Add-Hardkernel-ODROID-M1S.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0001-board-rockchip-Add-Hardkernel-ODROID-M1S.patch new file mode 100644 index 000000000..f586c96aa --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0001-board-rockchip-Add-Hardkernel-ODROID-M1S.patch @@ -0,0 +1,1049 @@ +From f7bc9a62a5ff7e8b95d902103b12c6ace208d11a Mon Sep 17 00:00:00 2001 +From: Dongjin Kim +Date: Thu, 25 Jan 2024 16:02:51 +0900 +Subject: [PATCH] board: rockchip: Add Hardkernel ODROID-M1S + +Hardkernel ODROID-M1S is a single board computer with a RK3566 SoC, +a slightly modified version of the RK3566 SoC. + +Features tested on a ODROID-M1S 8GB v1.0 2023-08-10: + - SD-card boot + - eMMC boot + - PCIe/NVMe + +Signed-off-by: Dongjin Kim +Message ID: 20240125070252.2057679-1-tobetter@gmail.com +--- + arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi | 28 + + arch/arm/dts/rk3566-odroid-m1s.dts | 665 +++++++++++++++++++++ + arch/arm/mach-rockchip/rk3568/Kconfig | 6 + + board/hardkernel/odroid_m1s/Kconfig | 15 + + board/hardkernel/odroid_m1s/MAINTAINERS | 9 + + board/hardkernel/odroid_m1s/Makefile | 7 + + board/hardkernel/odroid_m1s/board.c | 81 +++ + configs/odroid-m1s-rk3566_defconfig | 109 ++++ + doc/board/rockchip/rockchip.rst | 1 + + include/configs/odroid_m1s.h | 12 + + 10 files changed, 933 insertions(+) + create mode 100644 arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3566-odroid-m1s.dts + create mode 100644 board/hardkernel/odroid_m1s/Kconfig + create mode 100644 board/hardkernel/odroid_m1s/MAINTAINERS + create mode 100644 board/hardkernel/odroid_m1s/Makefile + create mode 100644 board/hardkernel/odroid_m1s/board.c + create mode 100644 configs/odroid-m1s-rk3566_defconfig + create mode 100644 include/configs/odroid_m1s.h + +diff --git a/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi +new file mode 100644 +index 0000000000..33a1d142b8 +--- /dev/null ++++ b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi +@@ -0,0 +1,28 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x-u-boot.dtsi" ++ ++#include ++#include ++ ++/ { ++ chosen { ++ stdout-path = &uart2; ++ u-boot,spl-boot-order = &sdmmc0, &sdhci; ++ }; ++}; ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++}; ++ ++&uart2 { ++ bootph-all; ++ clock-frequency = <24000000>; ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/rk3566-odroid-m1s.dts b/arch/arm/dts/rk3566-odroid-m1s.dts +new file mode 100644 +index 0000000000..73e29d80c7 +--- /dev/null ++++ b/arch/arm/dts/rk3566-odroid-m1s.dts +@@ -0,0 +1,665 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2024 Hardkernel Co., Ltd. ++ * ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ model = "Hardkernel ODROID-M1S"; ++ compatible = "hardkernel,rk3568-odroid-m1s", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ i2c0 = &i2c3; ++ i2c3 = &i2c0; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ serial0 = &uart1; ++ serial1 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac1_clkin: external-gmac1-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac1_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_power: led-0 { ++ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ function = LED_FUNCTION_POWER; ++ color = ; ++ default-state = "keep"; ++ linux,default-trigger = "default-on"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power_pin>; ++ }; ++ led_work: led-1 { ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ function = LED_FUNCTION_HEARTBEAT; ++ color = ; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_work_pin>; ++ }; ++ }; ++ ++ pcie20_3v3: pcie20-3v3-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc3v3_pcie20_en_pin>; ++ regulator-name = "pcie20_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ rk809-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "Analog RK817"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Headphone", "Headphones", ++ "Speaker", "Speaker"; ++ simple-audio-card,routing = ++ "Headphones", "HPOL", ++ "Headphones", "HPOR", ++ "Speaker", "SPKO"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ ++ spdif_dit: spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spdif_sound: spdif-sound { ++ compatible = "simple-audio-card"; ++ status = "disabled"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v_dcin>; ++ }; ++ ++ vcc5v_dcin: vcc5v0-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&vcc5v0_usb_host_en_pin>; ++ pinctrl-names = "default"; ++ regulator-max-microvolt = <5000000>; ++ regulator-min-microvolt = <5000000>; ++ regulator-name = "vcc5v0_usb_host"; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&vcc5v0_usb_otg_en_pin>; ++ pinctrl-names = "default"; ++ regulator-max-microvolt = <5000000>; ++ regulator-min-microvolt = <5000000>; ++ regulator-name = "vcc5v0_usb_otg"; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy1 { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac1 { ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; ++ assigned-clock-rates = <0>, <125000000>; ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc3v3_sys>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus ++ &gmac1m1_clkinout>; ++ status = "okay"; ++ ++ tx_delay = <0x4f>; ++ rx_delay = <0x2d>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ #clock-cells = <1>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT_TX>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; ++ rockchip,system-power-controller; ++ #sound-dai-cells = <0>; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-always-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ }; ++}; ++ ++&pcie2x1 { ++ pinctrl-0 = <&pcie20m2_pins>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ vpcie3v3-supply = <&pcie20_3v3>; ++}; ++ ++&pinctrl { ++ leds { ++ led_power_pin: led-power-pin { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_work_pin: led-work-pin { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ vcc3v3_pcie20_en_pin: vcc3v3-pcie20-en-pin { ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_3v3>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr50; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig +index baa51349f4..2f03b983ee 100644 +--- a/arch/arm/mach-rockchip/rk3568/Kconfig ++++ b/arch/arm/mach-rockchip/rk3568/Kconfig +@@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568 + help + Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC. + ++config TARGET_ODROID_M1S_RK3566 ++ bool "ODROID-M1S" ++ help ++ Hardkernel ODROID-M1S single board computer with a RK3566 SoC. ++ + config TARGET_QUARTZ64_RK3566 + bool "Pine64 Quartz64" + help +@@ -44,6 +49,7 @@ config SYS_MALLOC_F_LEN + source "board/rockchip/evb_rk3568/Kconfig" + source "board/anbernic/rgxx3_rk3566/Kconfig" + source "board/hardkernel/odroid_m1/Kconfig" ++source "board/hardkernel/odroid_m1s/Kconfig" + source "board/pine64/quartz64_rk3566/Kconfig" + + endif +diff --git a/board/hardkernel/odroid_m1s/Kconfig b/board/hardkernel/odroid_m1s/Kconfig +new file mode 100644 +index 0000000000..0acea61dac +--- /dev/null ++++ b/board/hardkernel/odroid_m1s/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_ODROID_M1S_RK3566 ++ ++config SYS_BOARD ++ default "odroid_m1s" ++ ++config SYS_VENDOR ++ default "hardkernel" ++ ++config SYS_CONFIG_NAME ++ default "odroid_m1s" ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ ++endif +diff --git a/board/hardkernel/odroid_m1s/MAINTAINERS b/board/hardkernel/odroid_m1s/MAINTAINERS +new file mode 100644 +index 0000000000..20fc277ccc +--- /dev/null ++++ b/board/hardkernel/odroid_m1s/MAINTAINERS +@@ -0,0 +1,9 @@ ++ODROID-M1S ++M: Dongjin Kim ++S: Maintained ++F: arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi ++F: arch/arm/dts/rk3566-odroid-m1s.dts ++F: board/hardkernel/odroid_m1s/ ++F: board/hardkernel/odroid_m1s/board.c ++F: configs/odroid-m1s-rk3566_defconfig ++F: include/configs/odroid_m1s.h +diff --git a/board/hardkernel/odroid_m1s/Makefile b/board/hardkernel/odroid_m1s/Makefile +new file mode 100644 +index 0000000000..6ca49c49b7 +--- /dev/null ++++ b/board/hardkernel/odroid_m1s/Makefile +@@ -0,0 +1,7 @@ ++# ++# Copyright (c) 2024 Hardkernel Co,. Ltd ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += board.o +diff --git a/board/hardkernel/odroid_m1s/board.c b/board/hardkernel/odroid_m1s/board.c +new file mode 100644 +index 0000000000..e87cfc4797 +--- /dev/null ++++ b/board/hardkernel/odroid_m1s/board.c +@@ -0,0 +1,81 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2024 Hardkernel Co., Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_MISC_INIT_R ++ ++/* Read first block 512 bytes from the first BOOT partition of eMMC ++ * that stores device identifcation sting in UUID type 1, this string ++ * is written in factory to give device seranl number and MAC address. ++ */ ++static int odroid_setup_macaddr(void) ++{ ++ struct mmc *mmc; ++ struct blk_desc *desc; ++ unsigned long mac_addr; ++ unsigned long count; ++ int ret; ++ u8 buf[512]; ++ ++ mmc = find_mmc_device(0); ++ if (!mmc) ++ return -ENODEV; ++ ++ desc = mmc_get_blk_desc(mmc); ++ ++ // Switch to the first BOOT partition ++ ret = blk_select_hwpart_devnum(UCLASS_MMC, 0, 1); ++ if (ret) ++ return -EIO; ++ ++ count = blk_dread(desc, 0, 1, (void *)buf); ++ ++ // Switch back to USER partition ++ ret = blk_dselect_hwpart(desc, 0); ++ if (ret || count != 1) ++ return -EIO; ++ ++ *(char *)(buf + 36) = 0; ++ ++ // Serial number ++ env_set("serial#", (char *)buf); ++ ++ // MAC address ++ mac_addr = cpu_to_be64(simple_strtoul((char *)buf + 24, NULL, 16)) >> 16; ++ ++ eth_env_set_enetaddr("ethaddr", (unsigned char *)&mac_addr); ++ eth_env_set_enetaddr("eth1addr", (unsigned char *)&mac_addr); ++ ++ return 0; ++} ++ ++int misc_init_r(void) ++{ ++ const u32 cpuid_offset = CFG_CPUID_OFFSET; ++ const u32 cpuid_length = 0x10; ++ u8 cpuid[cpuid_length]; ++ int ret; ++ ++ ret = odroid_setup_macaddr(); ++ if (ret) { ++ ret = rockchip_setup_macaddr(); ++ if (ret) ++ return ret; ++ } ++ ++ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_cpuid_set(cpuid, cpuid_length); ++ ++ return ret; ++} ++#endif +diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig +new file mode 100644 +index 0000000000..d70a10dc08 +--- /dev/null ++++ b/configs/odroid-m1s-rk3566_defconfig +@@ -0,0 +1,109 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_SF_DEFAULT_SPEED=24000000 ++CONFIG_SF_DEFAULT_MODE=0x1000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3566-odroid-m1s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_ODROID_M1S_RK3566=y ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-odroid-m1s.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_INI=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_CRAMFS=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_AHCI_PCI=y ++CONFIG_DWC_AHCI=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SF_DEFAULT_BUS=4 ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_PHY_ROCKCHIP_PCIE=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SCSI=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_FS_CRAMFS=y ++CONFIG_ERRNO_STR=y ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0800 +diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst +index 18d0b6f089..3ce9966fc1 100644 +--- a/doc/board/rockchip/rockchip.rst ++++ b/doc/board/rockchip/rockchip.rst +@@ -93,6 +93,7 @@ List of mainline supported Rockchip boards: + + * rk3566 + - Anbernic RGxx3 (anbernic-rgxx3-rk3566) ++ - Hardkernel ODROID-M1S (odroid-m1s-rk3566) + - Pine64 Quartz64-A Board (quartz64-a-rk3566) + - Pine64 Quartz64-B Board (quartz64-b-rk3566) + - Pine64 SOQuartz on Blade (soquartz-blade-rk3566) +diff --git a/include/configs/odroid_m1s.h b/include/configs/odroid_m1s.h +new file mode 100644 +index 0000000000..b271861388 +--- /dev/null ++++ b/include/configs/odroid_m1s.h +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef __ODROID_M1S_H ++#define __ODROID_M1S_H ++ ++#include ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdout=serial\0" \ ++ "stderr=serial\0" ++ ++#endif +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0002-Apply-fixes-for-mainline-u-boot.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0002-Apply-fixes-for-mainline-u-boot.patch new file mode 100644 index 000000000..ef4cbbb81 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0002-Apply-fixes-for-mainline-u-boot.patch @@ -0,0 +1,48 @@ +From ed61d0b5f18bf333ff7f35fc8546dd58d227b12f Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Sat, 3 Feb 2024 18:38:49 +1100 +Subject: [PATCH] Apply fixes for mainline u-boot + +--- + arch/arm/dts/rk3566-odroid-m1s.dts | 6 +----- + configs/odroid-m1s-rk3566_defconfig | 1 - + 2 files changed, 1 insertion(+), 6 deletions(-) + +diff --git a/arch/arm/dts/rk3566-odroid-m1s.dts b/arch/arm/dts/rk3566-odroid-m1s.dts +index 73e29d80c7..2dba07ba19 100644 +--- a/arch/arm/dts/rk3566-odroid-m1s.dts ++++ b/arch/arm/dts/rk3566-odroid-m1s.dts +@@ -17,12 +17,8 @@ + + aliases { + ethernet0 = &gmac1; +- i2c0 = &i2c3; +- i2c3 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc0; +- serial0 = &uart1; +- serial1 = &uart0; + }; + + chosen { +@@ -578,7 +574,7 @@ + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; +- sd-uhs-sdr50; ++ sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig +index d70a10dc08..61b6962063 100644 +--- a/configs/odroid-m1s-rk3566_defconfig ++++ b/configs/odroid-m1s-rk3566_defconfig +@@ -106,4 +106,3 @@ CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_FS_CRAMFS=y + CONFIG_ERRNO_STR=y +-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0800 +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0003-Improve-reliability-of-eMMC.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0003-Improve-reliability-of-eMMC.patch new file mode 100644 index 000000000..5309c6b70 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0003-Improve-reliability-of-eMMC.patch @@ -0,0 +1,44 @@ +From 2a1d8f586799e4166e802babcce18c9980aa1f44 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Thu, 1 Feb 2024 17:50:46 +1100 +Subject: [PATCH] Improve reliability of eMMC + +Cherry-picked from: +20240126232615.6826-2-jonas@kwiboo.se +--- + arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi | 4 ---- + configs/odroid-m1s-rk3566_defconfig | 2 ++ + 2 files changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi +index 33a1d142b8..04d0cd17ef 100644 +--- a/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi ++++ b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi +@@ -14,11 +14,7 @@ + + &sdhci { + cap-mmc-highspeed; +- mmc-ddr-1_8v; + mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + }; + + &uart2 { +diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig +index 61b6962063..7920ef224d 100644 +--- a/configs/odroid-m1s-rk3566_defconfig ++++ b/configs/odroid-m1s-rk3566_defconfig +@@ -70,6 +70,8 @@ CONFIG_ROCKCHIP_GPIO=y + CONFIG_SYS_I2C_ROCKCHIP=y + CONFIG_MISC=y + CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_SPL_MMC_HS200_SUPPORT=y + CONFIG_MMC_DW=y + CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0004-Fix-ethernet-properties.patch b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0004-Fix-ethernet-properties.patch new file mode 100644 index 000000000..3f453c6d6 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/patches/uboot/0004-Fix-ethernet-properties.patch @@ -0,0 +1,52 @@ +From 65a304151817626157e7be4e7e1581cdddca2a02 Mon Sep 17 00:00:00 2001 +From: Tim Lunn +Date: Sat, 3 Feb 2024 23:42:47 +1100 +Subject: [PATCH] Fix ethernet properties + +--- + arch/arm/dts/rk3566-odroid-m1s.dts | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/arch/arm/dts/rk3566-odroid-m1s.dts b/arch/arm/dts/rk3566-odroid-m1s.dts +index 2dba07ba19..73b545109d 100644 +--- a/arch/arm/dts/rk3566-odroid-m1s.dts ++++ b/arch/arm/dts/rk3566-odroid-m1s.dts +@@ -197,10 +197,9 @@ + }; + + &gmac1 { +- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; +- assigned-clock-rates = <0>, <125000000>; +- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; +- clock_in_out = "output"; ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; ++ clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_sys>; +@@ -211,10 +210,9 @@ + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; +- status = "okay"; +- + tx_delay = <0x4f>; + rx_delay = <0x2d>; ++ status = "okay"; + }; + + &gpu { +@@ -496,6 +494,9 @@ + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; + +-- +2.40.1 + diff --git a/buildroot-external/board/hardkernel/odroid-m1s/uboot-boot.ush b/buildroot-external/board/hardkernel/odroid-m1s/uboot-boot.ush new file mode 100644 index 000000000..719c6c0e5 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/uboot-boot.ush @@ -0,0 +1,98 @@ +part start ${devtype} ${devnum} hassos-bootstate mmc_env +${devtype} dev ${devnum} + +setenv loadbootstate " \ + echo 'loading env...'; \ + ${devtype} read ${ramdisk_addr_r} ${mmc_env} 0x40; \ + env import -c ${ramdisk_addr_r} 0x8000;" + +setenv storebootstate " \ + echo 'storing env...'; \ + env export -c -s 0x8000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT MACHINE_ID; \ + ${devtype} write ${ramdisk_addr_r} ${mmc_env} 0x40;" + +run loadbootstate +test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B" +test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3 +test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3 + +# Allows ConditionFirstBoot= +test -n "${MACHINE_ID}" || setenv BOOT_CONDITION "systemd.condition-first-boot=true" + +# HassOS bootargs +setenv bootargs_hassos "zram.enabled=1 zram.num_devices=3 systemd.machine_id=${MACHINE_ID} fsck.repair=yes ${BOOT_CONDITION}" + +# HassOS system A/B +setenv bootargs_a "root=PARTUUID=8d3d53e3-6d49-4c38-8349-aff6859e82fd rootfstype=squashfs ro rootwait" +setenv bootargs_b "root=PARTUUID=a3ec664e-32ce-4665-95ea-7ae90ce9aa20 rootfstype=squashfs ro rootwait" + +part number ${devtype} ${devnum} hassos-boot boot_partnum + +# Load environment from haos-config.txt +if test -e ${devtype} ${devnum}:${boot_partnum} haos-config.txt; then + fatload ${devtype} ${devnum}:${boot_partnum} ${ramdisk_addr_r} haos-config.txt + env import -t ${ramdisk_addr_r} ${filesize} +fi + +# Load extraargs +fileenv ${devtype} ${devnum}:${boot_partnum} ${ramdisk_addr_r} cmdline.txt cmdline + +# Load device tree +setenv fdtfile rk3566-odroid-m1s.dtb +echo "Loading standard device tree ${fdtfile}" +fatload ${devtype} ${devnum}:${boot_partnum} ${fdt_addr_r} ${fdtfile} +fdt addr ${fdt_addr_r} + +# load dt overlays +fdt resize 65536 +for overlay_file in ${overlays}; do + if fatload ${devtype} ${devnum}:${boot_partnum} ${ramdisk_addr_r} overlays/${overlay_file}.dtbo; then + echo "Applying kernel provided DT overlay ${overlay_file}.dtbo" + fdt apply ${ramdisk_addr_r} || setenv overlay_error "true" + fi +done +if test "${overlay_error}" = "true"; then + echo "Error applying DT overlays, restoring original DT" + fatload ${devtype} ${devnum}:${boot_partnum} ${fdt_addr_r} ${fdtfile} +fi + +setenv bootargs +for BOOT_SLOT in "${BOOT_ORDER}"; do + if test "x${bootargs}" != "x"; then + # skip remaining slots + elif test "x${BOOT_SLOT}" = "xA"; then + if test ${BOOT_A_LEFT} -gt 0; then + setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1 + echo "Trying to boot slot A, ${BOOT_A_LEFT} attempts remaining. Loading kernel ..." + part number ${devtype} ${devnum} hassos-kernel0 kernel_partnum + if load ${devtype} ${devnum}:${kernel_partnum} ${kernel_addr_r} Image; then + setenv bootargs "${bootargs_hassos} ${bootargs_a} rauc.slot=A ${cmdline}" + fi + fi + elif test "x${BOOT_SLOT}" = "xB"; then + if test ${BOOT_B_LEFT} -gt 0; then + setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1 + echo "Trying to boot slot B, ${BOOT_B_LEFT} attempts remaining. Loading kernel ..." + part number ${devtype} ${devnum} hassos-kernel1 kernel_partnum + if load ${devtype} ${devnum}:${kernel_partnum} ${kernel_addr_r} Image; then + setenv bootargs "${bootargs_hassos} ${bootargs_b} rauc.slot=B ${cmdline}" + fi + fi + fi +done + +if test -n "${bootargs}"; then + run storebootstate +else + echo "No valid slot found, resetting tries to 3" + setenv BOOT_A_LEFT 3 + setenv BOOT_B_LEFT 3 + run storebootstate + reset +fi + +echo "Starting kernel" +booti ${kernel_addr_r} - ${fdt_addr_r} + +echo "Boot failed, resetting..." +reset diff --git a/buildroot-external/board/hardkernel/odroid-m1s/uboot.config b/buildroot-external/board/hardkernel/odroid-m1s/uboot.config new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/buildroot-external/board/hardkernel/odroid-m1s/uboot.config @@ -0,0 +1 @@ + diff --git a/buildroot-external/configs/odroid_m1s_defconfig b/buildroot-external/configs/odroid_m1s_defconfig new file mode 100644 index 000000000..7ef08f20b --- /dev/null +++ b/buildroot-external/configs/odroid_m1s_defconfig @@ -0,0 +1,168 @@ +BR2_aarch64=y +BR2_TOOLCHAIN_BUILDROOT_CXX=y +BR2_DL_DIR="/cache/dl" +BR2_CCACHE=y +BR2_CCACHE_DIR="/cache/cc" +BR2_OPTIMIZE_2=y +BR2_ENABLE_LTO=y +BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_HASSOS_PATH)/patches $(BR2_EXTERNAL_HASSOS_PATH)/patches-rockchip $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s/patches" +BR2_SSP_REGULAR=y +BR2_TARGET_GENERIC_HOSTNAME="homeassistant" +BR2_TARGET_GENERIC_ISSUE="Welcome to Home Assistant" +BR2_INIT_SYSTEMD=y +# BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW is not set +BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_HASSOS_PATH)/rootfs-overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-build.sh" +BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh" +BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s/hassos-hook.sh" +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.16" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/kernel-arm64-rockchip.config" +BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/v6.6.y/device-support-wireless.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s/kernel.config" +BR2_LINUX_KERNEL_LZ4=y +BR2_LINUX_KERNEL_DTS_SUPPORT=y +BR2_LINUX_KERNEL_INTREE_DTS_NAME="rockchip/rk3566-odroid-m1s" +BR2_LINUX_KERNEL_DTB_OVERLAY_SUPPORT=y +BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y +BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y +BR2_PACKAGE_BUSYBOX_CONFIG="$(BR2_EXTERNAL_HASSOS_PATH)/busybox.config" +BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES=y +BR2_PACKAGE_V4L2LOOPBACK=y +BR2_PACKAGE_JQ=y +BR2_PACKAGE_CIFS_UTILS=y +BR2_PACKAGE_DOSFSTOOLS=y +BR2_PACKAGE_DOSFSTOOLS_FSCK_FAT=y +BR2_PACKAGE_E2FSPROGS=y +BR2_PACKAGE_E2FSPROGS_E2IMAGE=y +BR2_PACKAGE_NFS_UTILS=y +# BR2_PACKAGE_NFS_UTILS_RPC_NFSD is not set +BR2_PACKAGE_LINUX_FIRMWARE=y +BR2_PACKAGE_LINUX_FIRMWARE_COMPRESS=y +BR2_PACKAGE_LINUX_FIRMWARE_COMPRESS_ZSTD=y +BR2_PACKAGE_LINUX_FIRMWARE_MEDIATEK_MT7921_BT=y +BR2_PACKAGE_LINUX_FIRMWARE_MEDIATEK_MT7922_BT=y +BR2_PACKAGE_LINUX_FIRMWARE_QUALCOMM_6174A_BT=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_87XX_BT=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_88XX_BT=y +BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_6003=y +BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_6004=y +BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_7010=y +BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_9170=y +BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_9271=y +BR2_PACKAGE_LINUX_FIRMWARE_BRCM_BCM43XX=y +BR2_PACKAGE_LINUX_FIRMWARE_BRCM_BCM43XXX=y +BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8787=y +BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8797=y +BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_USB8797=y +BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_USB8801=y +BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8887=y +BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_SD8897=y +BR2_PACKAGE_LINUX_FIRMWARE_MWIFIEX_USB8897=y +BR2_PACKAGE_LINUX_FIRMWARE_MEDIATEK_MT7601U=y +BR2_PACKAGE_LINUX_FIRMWARE_MEDIATEK_MT7610E=y +BR2_PACKAGE_LINUX_FIRMWARE_MEDIATEK_MT76X2E=y +BR2_PACKAGE_LINUX_FIRMWARE_MEDIATEK_MT7921=y +BR2_PACKAGE_LINUX_FIRMWARE_MEDIATEK_MT7922=y +BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT73=y +BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT2XX=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_81XX=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_87XX=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_RTW88=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_RTW89=y +BR2_PACKAGE_LINUX_FIRMWARE_RTL_815X=y +BR2_PACKAGE_LINUX_FIRMWARE_USB_SERIAL_TI=y +BR2_PACKAGE_DBUS_BROKER=y +BR2_PACKAGE_GPTFDISK=y +BR2_PACKAGE_GPTFDISK_SGDISK=y +# BR2_PACKAGE_LVM2_STANDARD_INSTALL is not set +BR2_PACKAGE_RTL8812AU_AIRCRACK_NG=y +BR2_PACKAGE_USB_MODESWITCH_DATA=y +BR2_PACKAGE_CA_CERTIFICATES=y +BR2_PACKAGE_LIBCURL_CURL=y +BR2_PACKAGE_LIBDNET=y +BR2_PACKAGE_LIBCGROUP=y +BR2_PACKAGE_LIBCGROUP_TOOLS=y +BR2_PACKAGE_BLUEZ5_UTILS=y +BR2_PACKAGE_BLUEZ5_UTILS_CLIENT=y +BR2_PACKAGE_BLUEZ5_UTILS_TOOLS=y +BR2_PACKAGE_BLUEZ5_UTILS_DEPRECATED=y +BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_AUDIO=y +BR2_PACKAGE_BLUEZ5_UTILS_PLUGINS_HID=y +BR2_PACKAGE_DHCP=y +BR2_PACKAGE_DHCP_CLIENT=y +BR2_PACKAGE_DROPBEAR=y +# BR2_PACKAGE_IFUPDOWN_SCRIPTS is not set +BR2_PACKAGE_IPROUTE2=y +BR2_PACKAGE_IPTABLES_NFTABLES=y +BR2_PACKAGE_IPTABLES_NFTABLES_DEFAULT=y +BR2_PACKAGE_NETWORK_MANAGER=y +BR2_PACKAGE_NETWORK_MANAGER_CLI=y +BR2_PACKAGE_RPCBIND=y +BR2_PACKAGE_WIRELESS_REGDB=y +BR2_PACKAGE_WPA_SUPPLICANT=y +BR2_PACKAGE_WPA_SUPPLICANT_WEXT=y +BR2_PACKAGE_WPA_SUPPLICANT_AP_SUPPORT=y +BR2_PACKAGE_WPA_SUPPLICANT_WPA3=y +BR2_PACKAGE_WPA_SUPPLICANT_DBUS=y +BR2_PACKAGE_WPA_SUPPLICANT_DBUS_INTROSPECTION=y +BR2_PACKAGE_APPARMOR=y +BR2_PACKAGE_APPARMOR_PROFILES=y +BR2_PACKAGE_TINI=y +BR2_PACKAGE_DOCKER_CLI=y +BR2_PACKAGE_DOCKER_ENGINE=y +BR2_PACKAGE_PROCPS_NG=y +BR2_PACKAGE_RAUC=y +BR2_PACKAGE_RAUC_DBUS=y +BR2_PACKAGE_RAUC_NETWORK=y +BR2_PACKAGE_SYSTEMD_JOURNAL_REMOTE=y +BR2_PACKAGE_SYSTEMD_COREDUMP=y +# BR2_PACKAGE_SYSTEMD_HWDB is not set +BR2_PACKAGE_SYSTEMD_LOGIND=y +# BR2_PACKAGE_SYSTEMD_NETWORKD is not set +BR2_PACKAGE_SYSTEMD_RANDOMSEED=y +BR2_PACKAGE_UTIL_LINUX_LOGIN=y +BR2_PACKAGE_UTIL_LINUX_NOLOGIN=y +BR2_PACKAGE_UTIL_LINUX_PARTX=y +BR2_PACKAGE_UTIL_LINUX_SULOGIN=y +BR2_PACKAGE_UTIL_LINUX_ZRAMCTL=y +BR2_TARGET_ROOTFS_SQUASHFS=y +BR2_TARGET_ROOTFS_SQUASHFS4_LZ4=y +# BR2_TARGET_ROOTFS_TAR is not set +BR2_TARGET_UBOOT=y +BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y +BR2_TARGET_UBOOT_CUSTOM_GIT=y +BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/u-boot/u-boot.git" +BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="v2024.01" +BR2_TARGET_UBOOT_BOARD_DEFCONFIG="odroid-m1s-rk3566" +BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/bootloader/uboot.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s/uboot.config" +BR2_TARGET_UBOOT_NEEDS_PYLIBFDT=y +BR2_TARGET_UBOOT_NEEDS_PYELFTOOLS=y +BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y +BR2_TARGET_UBOOT_NEEDS_ATF_BL31_ELF=y +BR2_TARGET_UBOOT_NEEDS_TPL=y +BR2_TARGET_UBOOT_FORMAT_CUSTOM=y +BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-rockchip.bin" +BR2_PACKAGE_HOST_DOSFSTOOLS=y +BR2_PACKAGE_HOST_E2FSPROGS=y +BR2_PACKAGE_HOST_GPTFDISK=y +BR2_PACKAGE_HOST_MTOOLS=y +BR2_PACKAGE_HOST_RAUC=y +BR2_PACKAGE_HOST_UBOOT_TOOLS=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT_SOURCE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-m1s/uboot-boot.ush" +BR2_PACKAGE_GASKET=y +BR2_PACKAGE_HASSIO=y +BR2_PACKAGE_HASSIO_ARCH="aarch64" +BR2_PACKAGE_HASSIO_MACHINE="odroid-m1" +BR2_PACKAGE_OS_AGENT=y +BR2_PACKAGE_OS_AGENT_BOARD="OdroidM1S" +BR2_PACKAGE_ROCKCHIP_BLOBS=y +BR2_PACKAGE_ROCKCHIP_BLOBS_VERSION="b4558da0860ca48bf1a571dd33ccba580b9abe23" +BR2_PACKAGE_ROCKCHIP_BLOBS_ATF="bin/rk35/rk3568_bl31_v1.43.elf" +BR2_PACKAGE_ROCKCHIP_BLOBS_TPL="bin/rk35/rk3566_ddr_1056MHz_v1.18.bin" +BR2_PACKAGE_RPI_RF_MOD=y +BR2_PACKAGE_RTL88X2BU=y +BR2_PACKAGE_HOST_TEMPIO=y +BR2_PACKAGE_UDISKS2=y diff --git a/buildroot-external/scripts/hdd-image.sh b/buildroot-external/scripts/hdd-image.sh index 753fc662f..48cbc05d7 100755 --- a/buildroot-external/scripts/hdd-image.sh +++ b/buildroot-external/scripts/hdd-image.sh @@ -162,9 +162,9 @@ function _create_disk_gpt() { # Make sure boot partition is shifted by SPL size boot_offset=$((boot_offset+$(size2sectors "${BOOT_SPL_SIZE}"))) fi - if [ "${BOARD_ID}" == "odroid-m1" ]; then + if [ "${BOARD_ID}" == "odroid-m1" ] || [ "${BOARD_ID}" == "odroid-m1s" ]; then # Create partition for U-Boot binary (required by Hardkernel SPL to boot - # using default petitboot SPI + # using default petitboot SPI sgdisk -n "0:16384:+8M" -c 0:"uboot" -t 0:"21686148-6449-6E6F-744E-656564454649" "${hdd_img}" fi sgdisk -n "0:${boot_offset}:+$(get_boot_size)" -c 0:"hassos-boot" -t 0:"C12A7328-F81F-11D2-BA4B-00A0C93EC93B" -u 0:${BOOT_UUID} "${hdd_img}"