mirror of
https://github.com/home-assistant/operating-system.git
synced 2025-07-27 06:56:29 +00:00
NVMe patches are applied for all Raspberry Pi based boards now (#1959)
This commit is contained in:
Stefan Agner
parent
ad2f3a3570
commit
306c07b1b1
@ -1,51 +0,0 @@
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From 78924e9cf8c4af0baafcb2e7224bf04ad65276de Mon Sep 17 00:00:00 2001
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Message-Id: <78924e9cf8c4af0baafcb2e7224bf04ad65276de.1650924333.git.stefan@agner.ch>
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In-Reply-To: <78704bc154d695ee16fdf8396f4d60b740190014.1650924333.git.stefan@agner.ch>
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References: <78704bc154d695ee16fdf8396f4d60b740190014.1650924333.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Thu, 23 Sep 2021 23:52:44 +0200
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Subject: [PATCH 3/5] nvme: improve readability of nvme_setup_prps()
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Improve readability by introducing consts, reuse consts where
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appropriate and adding variables with discriptive name.
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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---
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drivers/nvme/nvme.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
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index 3bda491e12..1601651449 100644
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--- a/drivers/nvme/nvme.c
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+++ b/drivers/nvme/nvme.c
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@@ -76,12 +76,12 @@ static int nvme_wait_ready(struct nvme_dev *dev, bool enabled)
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static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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int total_len, u64 dma_addr)
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{
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- u32 page_size = dev->page_size;
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+ const u32 page_size = dev->page_size;
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+ const u32 prps_per_page = (page_size >> 3) - 1;
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int offset = dma_addr & (page_size - 1);
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u64 *prp_pool;
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int length = total_len;
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int i, nprps;
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- u32 prps_per_page = (page_size >> 3) - 1;
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u32 num_pages;
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length -= (page_size - offset);
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@@ -119,9 +119,9 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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prp_pool = dev->prp_pool;
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i = 0;
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while (nprps) {
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- if (i == ((page_size >> 3) - 1)) {
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- *(prp_pool + i) = cpu_to_le64((ulong)prp_pool +
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- page_size);
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+ if (i == prps_per_page) {
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+ u64 next_prp_list = (u64)prp_pool + page_size;
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+ *(prp_pool + i) = cpu_to_le64(next_prp_list);
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i = 0;
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prp_pool += page_size;
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}
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--
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2.36.0
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@ -1,263 +0,0 @@
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From e040d976ecbdd8071bbcb73d78e17ababa88c51f Mon Sep 17 00:00:00 2001
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Message-Id: <e040d976ecbdd8071bbcb73d78e17ababa88c51f.1650924333.git.stefan@agner.ch>
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In-Reply-To: <78704bc154d695ee16fdf8396f4d60b740190014.1650924333.git.stefan@agner.ch>
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References: <78704bc154d695ee16fdf8396f4d60b740190014.1650924333.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Thu, 23 Sep 2021 23:58:35 +0200
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Subject: [PATCH 4/5] nvme: Use pointer for CPU addressed buffers
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Pass buffers which use CPU addressing as void pointers. This aligns with
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DMA APIs which use void pointers as argument. It will avoid unnecessary
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type casts when adding support bus address translations.
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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---
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drivers/nvme/nvme.c | 50 ++++++++++++++++++++--------------------
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drivers/nvme/nvme_show.c | 4 ++--
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include/nvme.h | 12 +++++-----
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3 files changed, 33 insertions(+), 33 deletions(-)
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diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
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index 1601651449..6ab94ada7e 100644
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--- a/drivers/nvme/nvme.c
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+++ b/drivers/nvme/nvme.c
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@@ -74,11 +74,11 @@ static int nvme_wait_ready(struct nvme_dev *dev, bool enabled)
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}
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static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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- int total_len, u64 dma_addr)
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+ int total_len, void *buffer)
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{
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const u32 page_size = dev->page_size;
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const u32 prps_per_page = (page_size >> 3) - 1;
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- int offset = dma_addr & (page_size - 1);
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+ int offset = (uintptr_t)buffer & (page_size - 1);
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u64 *prp_pool;
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int length = total_len;
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int i, nprps;
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@@ -92,10 +92,10 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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}
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if (length)
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- dma_addr += (page_size - offset);
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+ buffer += (page_size - offset);
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if (length <= page_size) {
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- *prp2 = dma_addr;
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+ *prp2 = (u64)buffer;
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return 0;
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}
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@@ -125,11 +125,11 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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i = 0;
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prp_pool += page_size;
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}
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- *(prp_pool + i++) = cpu_to_le64(dma_addr);
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- dma_addr += page_size;
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+ *(prp_pool + i++) = cpu_to_le64((u64)buffer);
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+ buffer += page_size;
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nprps--;
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}
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- *prp2 = (ulong)dev->prp_pool;
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+ *prp2 = (u64)dev->prp_pool;
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flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
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dev->prp_entry_num * sizeof(u64));
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@@ -450,42 +450,42 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
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}
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int nvme_identify(struct nvme_dev *dev, unsigned nsid,
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- unsigned cns, dma_addr_t dma_addr)
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+ unsigned int cns, void *buffer)
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{
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struct nvme_command c;
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u32 page_size = dev->page_size;
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- int offset = dma_addr & (page_size - 1);
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+ int offset = (uintptr_t)buffer & (page_size - 1);
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int length = sizeof(struct nvme_id_ctrl);
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int ret;
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memset(&c, 0, sizeof(c));
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c.identify.opcode = nvme_admin_identify;
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c.identify.nsid = cpu_to_le32(nsid);
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- c.identify.prp1 = cpu_to_le64(dma_addr);
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+ c.identify.prp1 = cpu_to_le64((u64)buffer);
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length -= (page_size - offset);
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if (length <= 0) {
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c.identify.prp2 = 0;
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} else {
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- dma_addr += (page_size - offset);
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- c.identify.prp2 = cpu_to_le64(dma_addr);
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+ buffer += (page_size - offset);
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+ c.identify.prp2 = cpu_to_le64((u64)buffer);
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}
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c.identify.cns = cpu_to_le32(cns);
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- invalidate_dcache_range(dma_addr,
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- dma_addr + sizeof(struct nvme_id_ctrl));
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+ invalidate_dcache_range((uintptr_t)buffer,
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+ (uintptr_t)buffer + sizeof(struct nvme_id_ctrl));
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ret = nvme_submit_admin_cmd(dev, &c, NULL);
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if (!ret)
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- invalidate_dcache_range(dma_addr,
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- dma_addr + sizeof(struct nvme_id_ctrl));
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+ invalidate_dcache_range((uintptr_t)buffer,
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+ (uintptr_t)buffer + sizeof(struct nvme_id_ctrl));
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return ret;
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}
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int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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- dma_addr_t dma_addr, u32 *result)
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+ void *buffer, u32 *result)
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{
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struct nvme_command c;
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int ret;
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@@ -493,7 +493,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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memset(&c, 0, sizeof(c));
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c.features.opcode = nvme_admin_get_features;
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c.features.nsid = cpu_to_le32(nsid);
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- c.features.prp1 = cpu_to_le64(dma_addr);
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+ c.features.prp1 = cpu_to_le64((u64)buffer);
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c.features.fid = cpu_to_le32(fid);
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ret = nvme_submit_admin_cmd(dev, &c, result);
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@@ -513,13 +513,13 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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}
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int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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- dma_addr_t dma_addr, u32 *result)
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+ void *buffer, u32 *result)
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{
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struct nvme_command c;
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memset(&c, 0, sizeof(c));
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c.features.opcode = nvme_admin_set_features;
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- c.features.prp1 = cpu_to_le64(dma_addr);
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+ c.features.prp1 = cpu_to_le64((u64)buffer);
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c.features.fid = cpu_to_le32(fid);
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c.features.dword11 = cpu_to_le32(dword11);
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@@ -570,7 +570,7 @@ static int nvme_set_queue_count(struct nvme_dev *dev, int count)
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u32 q_count = (count - 1) | ((count - 1) << 16);
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status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES,
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- q_count, 0, &result);
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+ q_count, NULL, &result);
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if (status < 0)
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return status;
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@@ -622,7 +622,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)
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if (!ctrl)
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return -ENOMEM;
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- ret = nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl);
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+ ret = nvme_identify(dev, 0, 1, ctrl);
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if (ret) {
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free(ctrl);
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return -EIO;
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@@ -708,7 +708,7 @@ static int nvme_blk_probe(struct udevice *udev)
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ns->dev = ndev;
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/* extract the namespace id from the block device name */
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ns->ns_id = trailing_strtol(udev->name);
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- if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)(long)id)) {
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+ if (nvme_identify(ndev, ns->ns_id, 0, id)) {
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free(id);
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return -EIO;
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}
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@@ -743,7 +743,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,
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u64 prp2;
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u64 total_len = blkcnt << desc->log2blksz;
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u64 temp_len = total_len;
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- uintptr_t temp_buffer = (uintptr_t)buffer;
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+ void *temp_buffer = buffer;
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u64 slba = blknr;
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u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
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@@ -890,7 +890,7 @@ static int nvme_probe(struct udevice *udev)
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char name[20];
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memset(id, 0, sizeof(*id));
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- if (nvme_identify(ndev, i, 0, (dma_addr_t)(long)id)) {
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+ if (nvme_identify(ndev, i, 0, id)) {
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ret = -EIO;
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goto free_id;
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}
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diff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c
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index 15e459da1a..c30adfada5 100644
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--- a/drivers/nvme/nvme_show.c
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+++ b/drivers/nvme/nvme_show.c
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@@ -111,14 +111,14 @@ int nvme_print_info(struct udevice *udev)
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ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl));
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struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl;
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- if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl))
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+ if (nvme_identify(dev, 0, 1, ctrl))
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return -EIO;
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print_optional_admin_cmd(le16_to_cpu(ctrl->oacs), ns->devnum);
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print_optional_nvm_cmd(le16_to_cpu(ctrl->oncs), ns->devnum);
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print_format_nvme_attributes(ctrl->fna, ns->devnum);
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- if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id))
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+ if (nvme_identify(dev, ns->ns_id, 0, id))
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return -EIO;
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print_formats(id, ns);
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diff --git a/include/nvme.h b/include/nvme.h
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index 2cdf8ce320..8ff823cd81 100644
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--- a/include/nvme.h
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+++ b/include/nvme.h
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@@ -18,12 +18,12 @@ struct nvme_dev;
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* @dev: NVMe controller device
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* @nsid: 0 for controller, namespace id for namespace to identify
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* @cns: 1 for controller, 0 for namespace
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- * @dma_addr: dma buffer address to store the identify result
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+ * @buffer: dma buffer address to store the identify result
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* @return: 0 on success, -ETIMEDOUT on command execution timeout,
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* -EIO on command execution fails
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*/
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int nvme_identify(struct nvme_dev *dev, unsigned nsid,
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- unsigned cns, dma_addr_t dma_addr);
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+ unsigned int cns, void *buffer);
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/**
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* nvme_get_features - retrieve the attributes of the feature specified
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@@ -33,13 +33,13 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
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* @dev: NVMe controller device
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* @fid: feature id to provide data
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* @nsid: namespace id the command applies to
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- * @dma_addr: data structure used as part of the specified feature
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+ * @buffer: data structure used as part of the specified feature
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* @result: command-specific result in the completion queue entry
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* @return: 0 on success, -ETIMEDOUT on command execution timeout,
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* -EIO on command execution fails
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*/
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int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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- dma_addr_t dma_addr, u32 *result);
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+ void *buffer, u32 *result);
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/**
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* nvme_set_features - specify the attributes of the feature indicated
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@@ -49,13 +49,13 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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* @dev: NVMe controller device
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* @fid: feature id to provide data
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* @dword11: command-specific input parameter
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- * @dma_addr: data structure used as part of the specified feature
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+ * @buffer: data structure used as part of the specified feature
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* @result: command-specific result in the completion queue entry
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* @return: 0 on success, -ETIMEDOUT on command execution timeout,
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* -EIO on command execution fails
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*/
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int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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- dma_addr_t dma_addr, u32 *result);
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+ void *buffer, u32 *result);
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/**
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* nvme_scan_namespace - scan all namespaces attached to NVMe controllers
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--
|
|
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2.36.0
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@ -1,198 +0,0 @@
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From c4736c35141e519d15430660e17c274e142e886d Mon Sep 17 00:00:00 2001
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Message-Id: <c4736c35141e519d15430660e17c274e142e886d.1650924333.git.stefan@agner.ch>
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In-Reply-To: <78704bc154d695ee16fdf8396f4d60b740190014.1650924333.git.stefan@agner.ch>
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References: <78704bc154d695ee16fdf8396f4d60b740190014.1650924333.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Fri, 24 Sep 2021 00:27:39 +0200
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Subject: [PATCH 5/5] nvme: translate virtual addresses into the bus's address
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space
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So far we've been content with passing physical/CPU addresses when
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configuring memory addresses into NVMe controllers, but not all
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platforms have buses with transparent mappings. Specifically the
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Raspberry Pi 4 might introduce an offset to memory accesses incoming
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from its PCIe port.
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Introduce nvme_virt_to_bus() and nvme_bus_to_virt() to cater with these
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limitations, and make sure we don't break non DM users.
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For devices where PCIe's view of host memory doesn't match the memory
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as seen by the CPU.
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A similar change has been introduced for XHCI controller with
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commit 1a474559d90a ("xhci: translate virtual addresses into the bus's
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address space").
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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---
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drivers/nvme/nvme.c | 32 ++++++++++++++++++--------------
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drivers/nvme/nvme.h | 15 +++++++++++++++
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2 files changed, 33 insertions(+), 14 deletions(-)
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diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c
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index 6ab94ada7e..dd190bd654 100644
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--- a/drivers/nvme/nvme.c
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+++ b/drivers/nvme/nvme.c
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@@ -95,7 +95,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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buffer += (page_size - offset);
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if (length <= page_size) {
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- *prp2 = (u64)buffer;
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+ *prp2 = nvme_virt_to_bus(dev, buffer);
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return 0;
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}
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@@ -120,16 +120,16 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2,
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i = 0;
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||||||
while (nprps) {
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if (i == prps_per_page) {
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- u64 next_prp_list = (u64)prp_pool + page_size;
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- *(prp_pool + i) = cpu_to_le64(next_prp_list);
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+ u64 next = nvme_virt_to_bus(dev, prp_pool + page_size);
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+ *(prp_pool + i) = cpu_to_le64(next);
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i = 0;
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||||||
prp_pool += page_size;
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}
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||||||
- *(prp_pool + i++) = cpu_to_le64((u64)buffer);
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+ *(prp_pool + i++) = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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buffer += page_size;
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nprps--;
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}
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- *prp2 = (u64)dev->prp_pool;
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+ *prp2 = nvme_virt_to_bus(dev, dev->prp_pool);
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flush_dcache_range((ulong)dev->prp_pool, (ulong)dev->prp_pool +
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dev->prp_entry_num * sizeof(u64));
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@@ -356,6 +356,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
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int result;
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u32 aqa;
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u64 cap = dev->cap;
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+ u64 dma_addr;
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struct nvme_queue *nvmeq;
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/* most architectures use 4KB as the page size */
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unsigned page_shift = 12;
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@@ -396,8 +397,10 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)
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dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
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writel(aqa, &dev->bar->aqa);
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- nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq);
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- nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq);
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+ dma_addr = nvme_virt_to_bus(dev, nvmeq->sq_cmds);
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+ nvme_writeq(dma_addr, &dev->bar->asq);
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+ dma_addr = nvme_virt_to_bus(dev, nvmeq->cqes);
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+ nvme_writeq(dma_addr, &dev->bar->acq);
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result = nvme_enable_ctrl(dev);
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if (result)
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@@ -423,7 +426,7 @@ static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid,
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memset(&c, 0, sizeof(c));
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c.create_cq.opcode = nvme_admin_create_cq;
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- c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes);
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+ c.create_cq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->cqes));
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c.create_cq.cqid = cpu_to_le16(qid);
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c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
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c.create_cq.cq_flags = cpu_to_le16(flags);
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@@ -440,7 +443,7 @@ static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid,
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memset(&c, 0, sizeof(c));
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c.create_sq.opcode = nvme_admin_create_sq;
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- c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds);
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+ c.create_sq.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, nvmeq->sq_cmds));
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c.create_sq.sqid = cpu_to_le16(qid);
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c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
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c.create_sq.sq_flags = cpu_to_le16(flags);
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@@ -461,14 +464,14 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
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memset(&c, 0, sizeof(c));
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c.identify.opcode = nvme_admin_identify;
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c.identify.nsid = cpu_to_le32(nsid);
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- c.identify.prp1 = cpu_to_le64((u64)buffer);
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+ c.identify.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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length -= (page_size - offset);
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if (length <= 0) {
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c.identify.prp2 = 0;
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} else {
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||||||
buffer += (page_size - offset);
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- c.identify.prp2 = cpu_to_le64((u64)buffer);
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+ c.identify.prp2 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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}
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c.identify.cns = cpu_to_le32(cns);
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@@ -493,7 +496,7 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
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memset(&c, 0, sizeof(c));
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c.features.opcode = nvme_admin_get_features;
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c.features.nsid = cpu_to_le32(nsid);
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|
||||||
- c.features.prp1 = cpu_to_le64((u64)buffer);
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||||||
+ c.features.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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c.features.fid = cpu_to_le32(fid);
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|
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ret = nvme_submit_admin_cmd(dev, &c, result);
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|
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@@ -519,7 +522,7 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
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||||||
memset(&c, 0, sizeof(c));
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c.features.opcode = nvme_admin_set_features;
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||||||
- c.features.prp1 = cpu_to_le64((u64)buffer);
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||||||
+ c.features.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, buffer));
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||||||
c.features.fid = cpu_to_le32(fid);
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c.features.dword11 = cpu_to_le32(dword11);
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@@ -776,7 +779,7 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,
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c.rw.slba = cpu_to_le64(slba);
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||||||
slba += lbas;
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c.rw.length = cpu_to_le16(lbas - 1);
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||||||
- c.rw.prp1 = cpu_to_le64(temp_buffer);
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||||||
+ c.rw.prp1 = cpu_to_le64(nvme_virt_to_bus(dev, temp_buffer));
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|
||||||
c.rw.prp2 = cpu_to_le64(prp2);
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status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
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&c, NULL, IO_TIMEOUT);
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@@ -835,6 +838,7 @@ static int nvme_probe(struct udevice *udev)
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||||||
struct nvme_id_ns *id;
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|
||||||
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|
||||||
ndev->instance = trailing_strtol(udev->name);
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|
||||||
+ ndev->dev = udev->parent;
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||||||
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|
||||||
INIT_LIST_HEAD(&ndev->namespaces);
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|
||||||
ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0,
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|
||||||
diff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h
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|
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index c6aae4da5d..31e6899bca 100644
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|
||||||
--- a/drivers/nvme/nvme.h
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|
||||||
+++ b/drivers/nvme/nvme.h
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|
||||||
@@ -7,8 +7,15 @@
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|
||||||
#ifndef __DRIVER_NVME_H__
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|
||||||
#define __DRIVER_NVME_H__
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|
||||||
|
|
||||||
+#include <phys2bus.h>
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|
||||||
#include <asm/io.h>
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|
||||||
|
|
||||||
+#if CONFIG_IS_ENABLED(DM_USB)
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|
||||||
+#define nvme_to_dev(_dev) _dev->dev
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|
||||||
+#else
|
|
||||||
+#define nvme_to_dev(_dev) NULL
|
|
||||||
+#endif
|
|
||||||
+
|
|
||||||
struct nvme_id_power_state {
|
|
||||||
__le16 max_power; /* centiwatts */
|
|
||||||
__u8 rsvd2;
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|
||||||
@@ -596,6 +603,9 @@ enum {
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|
||||||
|
|
||||||
/* Represents an NVM Express device. Each nvme_dev is a PCI function. */
|
|
||||||
struct nvme_dev {
|
|
||||||
+#if CONFIG_IS_ENABLED(DM_USB)
|
|
||||||
+ struct udevice *dev;
|
|
||||||
+#endif
|
|
||||||
struct list_head node;
|
|
||||||
struct nvme_queue **queues;
|
|
||||||
u32 __iomem *dbs;
|
|
||||||
@@ -635,4 +645,9 @@ struct nvme_ns {
|
|
||||||
u8 flbas;
|
|
||||||
};
|
|
||||||
|
|
||||||
+static inline dma_addr_t nvme_virt_to_bus(struct nvme_dev *dev, void *addr)
|
|
||||||
+{
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|
||||||
+ return dev_phys_to_bus(nvme_to_dev(dev), virt_to_phys(addr));
|
|
||||||
+}
|
|
||||||
+
|
|
||||||
#endif /* __DRIVER_NVME_H__ */
|
|
||||||
--
|
|
||||||
2.36.0
|
|
||||||
|
|
||||||
Loading…
x
Reference in New Issue
Block a user