Update Linux kernel to 5.10 LTS (#1214)

* Drop ODROID specific kernel update script

With the jump to Linux 5.10 LTS we can use the same upstream kernel for
Hardkernel ODROID boards as well. Extend the update-kernel-upstream.sh
to support the ODROID boards.

* Linux: Update kernel 5.10.13
This commit is contained in:
Stefan Agner 2021-02-05 18:52:16 +01:00 committed by GitHub
parent 8bbc330407
commit 57ffd6444b
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
24 changed files with 39 additions and 2208 deletions

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@ -5,15 +5,15 @@ Default Kernel tree: 5.4
| Board | Version |
|-------|---------|
| Open Virtual Appliance | 5.4.82 |
| Open Virtual Appliance | 5.10.13 |
| Raspberry Pi | 5.4.83 |
| Raspberry Pi 0-W | 5.4.83 |
| Raspberry Pi 2 | 5.4.83 |
| Raspberry Pi 3 | 5.4.83 |
| Raspberry Pi 4 | 5.4.83 |
| Tinker Board | 5.4.82 |
| Odroid-C2 | 5.9.13 |
| Odroid-C4 | 5.9.13 |
| Odroid-N2 | 5.9.13 |
| Odroid-XU4 | 5.9.13 |
| Intel NUC | 5.4.82 |
| Tinker Board | 5.10.13 |
| Odroid-C2 | 5.10.13 |
| Odroid-C4 | 5.10.13 |
| Odroid-N2 | 5.10.13 |
| Odroid-XU4 | 5.10.13 |
| Intel NUC | 5.10.13 |

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@ -1,28 +0,0 @@
From c5af6798c9a411b3f550f463182a4b4904a21ec2 Mon Sep 17 00:00:00 2001
From: Myy Miouyouyou <myy@miouyouyou.fr>
Date: Thu, 19 Oct 2017 21:51:14 +0200
Subject: [PATCH 16/28] ARM: DTSI: rk3288.dtsi: Adding missing VOPB registers
Imported from @wzyy2 patches... I think...
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 455446f6..125f8835 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -987,7 +987,7 @@
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff930000 0x0 0x19c>;
+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
--
2.11.0

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@ -1,28 +0,0 @@
From ebc29962ac27264772a4227f5abd6900cb72fa79 Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Mon, 5 Nov 2018 20:16:05 +0100
Subject: [PATCH] ARM: DTSI: rk3288-tinker: Improving the CPU max voltage
Taken from the various patches provided by @TonyMac32 .
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
index aa107ee41..3da1c830f 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -164,7 +164,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1450000>;
regulator-name = "vdd_arm";
regulator-ramp-delay = <6000>;
regulator-state-mem {
--
2.16.4

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@ -1,31 +0,0 @@
From 3dacea70a8e434008f5b1f119a7f7da9aebc772c Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Mon, 5 Nov 2018 20:18:58 +0100
Subject: [PATCH] ARM: DTSI: rk3288-tinker: Setting up the SD regulators
Some are needed and some are not. Playing with these parameters is
required to get reboot working on these boards.
I still can't believe that these boards can't soft reset correctly.
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rk3288-tinker.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
index 3da1c830f..dd1090728 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -254,7 +254,8 @@
};
vccio_sd: LDO_REG5 {
+ regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
--
2.16.4

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@ -1,434 +0,0 @@
From 6c86916e81fa18394d9b57b4af44f9948e100e96 Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Sat, 29 Sep 2018 03:02:10 +0200
Subject: [PATCH 6/6] drm: dw_hdmi-rockchip: better clock selection logic and
dts-based rate list
This patch is taken from Urja Rannikko ( @urjaman ) patchset here :
https://github.com/urjaman/arch-c201/blob/master/linux-c201/0020-RK3288-HDMI-clock-hacks-combined.patch
https://www.spinics.net/lists/arm-kernel/msg673156.html
The original description was :
This contains traces of the following commits from the ChromeOS 3.14
tree, which improve RF/EMI performance and detach the clock selection
logic from the HDMI PHY configurations, plus support for configuring
the allowed clock rates via device tree as they are dependent on
PLL configuration and maybe even the PCB layout and other hardware things,
eg. interference to wifi or such (EMI).
Rates that were allowed previous to this patch are added as the fallback
list if no dts configuration exists.
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Adjust rockchip_mpll_cfg for 146.25
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: expand the informal mpll config
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: add slop to more tables
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: redo rockchip hdmi to allow slop
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Use auto-generated tables
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Fixup the clock to be what we expect
CHROMIUM: drm/rockchip: hdmi: adjust cklvl & txlvl for RF/EMI
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Set cur_ctr to 0 always
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Decrease slop
https://www.spinics.net/lists/arm-kernel/msg673163.html
This is the patch that takes into account the new property
"rockchip,hdmi-rates-hz" that allows the definition of the HDMI
frequencies in the DTS file.
This also change a lot of HDMI frequencies definition, so that
*will* require some extensive testing.
Still, if it works fine, this should make tinkering the HDMI
frequencies easier, in case you have a very special HDMI screen.
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index cdc304d4c..91c7dc07b 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -73,122 +73,141 @@ struct rockchip_hdmi {
struct clk *grf_clk;
struct dw_hdmi *hdmi;
struct phy *phy;
+ u32* rates;
+ u32 rates_cnt;
};
+#define CLK_SLOP(clk) ((clk) / 1000)
+#define CLK_PLUS_SLOP(clk) ((clk) + CLK_SLOP(clk))
+
#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
+/* These were the rates allowed by the driver before rates list in device tree,
+ * so keep them around as a fallback */
+static const u32 dw_hdmi_fallback_rates[] = {
+ 27000000,
+ 36000000,
+ 40000000,
+ 54000000,
+ 65000000,
+ 66000000,
+ 74250000,
+ 83500000,
+ 106500000,
+ 108000000,
+ 146250000,
+ 148500000
+};
+
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
{
- 27000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ 30666000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40f3, 0x0000 },
+ },
+ }, {
+ 36800000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 36000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ }, {
+ 46000000, {
+ { 0x00b3, 0x0000 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 40000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
+ }, {
+ 61333000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
},
- }, {
- 54000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
+ }, {
+ 73600000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x4061, 0x0002 },
},
- }, {
- 65000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
+ }, {
+ 92000000, {
+ { 0x0072, 0x0001 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
},
- }, {
- 66000000, {
- { 0x013e, 0x0003},
- { 0x217e, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 122666000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
},
- }, {
- 74250000, {
- { 0x0072, 0x0001},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 147200000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4064, 0x0003 },
},
- }, {
- 83500000, {
- { 0x0072, 0x0001},
+ }, {
+ 184000000, {
+ { 0x0051, 0x0002 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
},
- }, {
- 108000000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 226666000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
},
- }, {
- 106500000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 272000000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
- 146250000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
+ }, {
+ 340000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
- 148500000, {
- { 0x0051, 0x0003},
- { 0x214c, 0x0003},
- { 0x4064, 0x0003}
+ }, {
+ 600000000, {
+ { 0x1a40, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
+ }, {
~0UL, {
- { 0x00a0, 0x000a },
- { 0x2001, 0x000f },
- { 0x4002, 0x000f },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
},
}
};
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
- /* pixelclk bpp8 bpp10 bpp12 */
+ /* pixelclk bpp8 bpp10 bpp12 */
{
- 40000000, { 0x0018, 0x0018, 0x0018 },
- }, {
- 65000000, { 0x0028, 0x0028, 0x0028 },
- }, {
- 66000000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 74250000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 83500000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 146250000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 148500000, { 0x0000, 0x0038, 0x0038 },
- }, {
- ~0UL, { 0x0000, 0x0000, 0x0000},
- }
+ 600000000, { 0x0000, 0x0000, 0x0000 },
+ }, {
+ ~0UL, { 0x0000, 0x0000, 0x0000 },
+ },
};
static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
/*pixelclk symbol term vlev*/
- { 74250000, 0x8009, 0x0004, 0x0272},
- { 148500000, 0x802b, 0x0004, 0x028d},
- { 297000000, 0x8039, 0x0005, 0x028d},
- { ~0UL, 0x0000, 0x0000, 0x0000}
+ { CLK_PLUS_SLOP(74250000), 0x8009, 0x0004, 0x0272},
+ { CLK_PLUS_SLOP(165000000), 0x802b, 0x0004, 0x0209},
+ { CLK_PLUS_SLOP(297000000), 0x8039, 0x0005, 0x028d},
+ { ~0UL, 0x0000, 0x0000, 0x0000}
};
static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
{
struct device_node *np = hdmi->dev->of_node;
+ int rates_cnt;
hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
if (IS_ERR(hdmi->regmap)) {
@@ -216,26 +235,55 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
return PTR_ERR(hdmi->grf_clk);
}
+ if ((rates_cnt = of_property_count_u32_elems(np, "rockchip,hdmi-rates-hz")) > 0) {
+ int rv;
+ u32 *rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL);
+ if (!rates)
+ return -ENOMEM;
+ rv = of_property_read_u32_array(np, "rockchip,hdmi-rates-hz", rates, rates_cnt);
+ if (rv)
+ return rv;
+ hdmi->rates = rates;
+ hdmi->rates_cnt = rates_cnt;
+ } else {
+ rates_cnt = ARRAY_SIZE(dw_hdmi_fallback_rates);
+ hdmi->rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL);
+ if (!hdmi->rates)
+ return -ENOMEM;
+ memcpy(hdmi->rates, dw_hdmi_fallback_rates, rates_cnt * sizeof(u32));
+ hdmi->rates_cnt = rates_cnt;
+ }
+
+
return 0;
}
static enum drm_mode_status
-dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
+dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder,
const struct drm_display_mode *mode)
{
- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
int pclk = mode->clock * 1000;
- bool valid = false;
+ int num_rates = hdmi->rates_cnt;
int i;
- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
- if (pclk == mpll_cfg[i].mpixelclock) {
- valid = true;
- break;
- }
+ /*
+ * Pixel clocks we support are always < 2GHz and so fit in an
+ * int. We should make sure source rate does too so we don't get
+ * overflow when we multiply by 1000.
+ */
+ if (mode->clock > INT_MAX / 1000)
+ return MODE_BAD;
+
+ for (i = 0; i < num_rates; i++) {
+ int slop = CLK_SLOP(pclk);
+
+ if ((pclk >= hdmi->rates[i] - slop) &&
+ (pclk <= hdmi->rates[i] + slop))
+ return MODE_OK;
}
- return (valid) ? MODE_OK : MODE_BAD;
+ return MODE_BAD;
}
static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
@@ -251,7 +299,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
{
- return true;
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ int pclk = adj_mode->clock * 1000;
+ int best_diff = INT_MAX;
+ int best_clock = 0;
+ int slop;
+ int i;
+
+ /* Pick the best clock */
+ for (i = 0; i < hdmi->rates_cnt; i++) {
+ int diff = hdmi->rates[i] - pclk;
+
+ if (diff < 0)
+ diff = -diff;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_clock = hdmi->rates[i];
+
+ /* Bail early if we're exact */
+ if (best_diff == 0)
+ return true;
+ }
+ }
+
+ /* Double check that it's OK */
+ slop = CLK_SLOP(pclk);
+ if ((pclk >= best_clock - slop) && (pclk <= best_clock + slop)) {
+ adj_mode->clock = DIV_ROUND_UP(best_clock, 1000);
+ return true;
+ }
+
+ /* Shoudn't be here; we should have said rate wasn't valid */
+ dev_warn(hdmi->dev, "tried to set invalid rate %d\n", adj_mode->clock);
+ return false;
}
static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
@@ -307,6 +387,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
}
static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
+ .mode_valid = dw_hdmi_rockchip_encoder_mode_valid,
.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
.mode_set = dw_hdmi_rockchip_encoder_mode_set,
.enable = dw_hdmi_rockchip_encoder_enable,
@@ -406,7 +487,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
};
static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -423,7 +503,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
};
static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -443,7 +522,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = {
};
static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -460,7 +538,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
};
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -558,6 +635,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
*/
if (IS_ERR(hdmi->hdmi)) {
ret = PTR_ERR(hdmi->hdmi);
+ devm_kfree(hdmi->dev, hdmi->rates);
drm_encoder_cleanup(encoder);
clk_disable_unprepare(hdmi->vpll_clk);
}
@@ -570,6 +648,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
{
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
+ devm_kfree(hdmi->dev, hdmi->rates);
dw_hdmi_unbind(hdmi->hdmi);
clk_disable_unprepare(hdmi->vpll_clk);
}

View File

@ -1,10 +1,8 @@
From 2c15ad491233a80d61c811a944b86067e2e74686 Mon Sep 17 00:00:00 2001
Message-Id: <2c15ad491233a80d61c811a944b86067e2e74686.1606829302.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
From 516c081bcdd8f248982588aa8ca5bd8d24b2e7ef Mon Sep 17 00:00:00 2001
Message-Id: <516c081bcdd8f248982588aa8ca5bd8d24b2e7ef.1612541102.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Mon, 16 Nov 2020 23:11:02 +0100
Subject: [PATCH 5/7] arm64: dts: meson: add RTC to ODROID-N2 boards
Subject: [PATCH 1/4] arm64: dts: meson: add RTC to ODROID-N2 boards
All ODROID-N2 boards come with a NXP PCF8563TS RTC connected to I2C bus
3. This is the RTC which is connected to the on-board RTC backup battery.
@ -16,7 +14,7 @@ Signed-off-by: Stefan Agner <stefan@agner.ch>
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
index 6982632ae646..40390feba053 100644
index 39a09661c5f6..445d90d25aa3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
@@ -13,6 +13,8 @@ / {
@ -48,5 +46,5 @@ index 6982632ae646..40390feba053 100644
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
--
2.29.2
2.30.0

View File

@ -1,10 +1,10 @@
From 83ec133319bc8b04fad2bec65ffe95246c600520 Mon Sep 17 00:00:00 2001
Message-Id: <83ec133319bc8b04fad2bec65ffe95246c600520.1610380198.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1610380198.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1610380198.git.stefan@agner.ch>
From 3a2086e15c0b121250dd4c48214cd0486a67fde1 Mon Sep 17 00:00:00 2001
Message-Id: <3a2086e15c0b121250dd4c48214cd0486a67fde1.1612541102.git.stefan@agner.ch>
In-Reply-To: <516c081bcdd8f248982588aa8ca5bd8d24b2e7ef.1612541102.git.stefan@agner.ch>
References: <516c081bcdd8f248982588aa8ca5bd8d24b2e7ef.1612541102.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Mon, 11 Jan 2021 11:20:48 +0100
Subject: [PATCH 08/10] arm64: dts: meson: g12b: add power button support
Subject: [PATCH 2/4] arm64: dts: meson: g12b: add power button support
Add power button support on J2 pin 11 (GPIOX_3 on the SoC side). The
GPIO is low active, e.g. when connecting with pin 9 (GND) a power

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@ -1,36 +0,0 @@
From 258f03fa4fd897a61b5861df1f809e234711dd49 Mon Sep 17 00:00:00 2001
Message-Id: <258f03fa4fd897a61b5861df1f809e234711dd49.1606829302.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Tue, 15 Sep 2020 17:24:31 +0200
Subject: [PATCH 2/7] dt-bindings: arm: amlogic: add support for the ODROID-N2+
HardKernel ODROID-N2+ uses a revised Amlogic S922X v2 chip that supports
higher cpu clock speeds than the original ODROID-N2.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200915152432.30616-3-narmstrong@baylibre.com
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 5eba9f48823e..12ba8d074370 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -153,6 +153,7 @@ properties:
- azw,gtking
- azw,gtking-pro
- hardkernel,odroid-n2
+ - hardkernel,odroid-n2-plus
- khadas,vim3
- ugoos,am6
- const: amlogic,s922x
--
2.29.2

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@ -1,78 +0,0 @@
From 6cfaddae585e5a87c5253c932b8d58e153159f6b Mon Sep 17 00:00:00 2001
Message-Id: <6cfaddae585e5a87c5253c932b8d58e153159f6b.1606829302.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Tue, 15 Sep 2020 17:24:32 +0200
Subject: [PATCH 3/7] arm64: dts: meson: add support for the ODROID-N2+
HardKernel ODROID-N2+ uses an Amlogic S922X rev. C chip capable of higher
clock speeds than the original ODROID-N2.
The rev. C support a slighly higher VDDCPU_A & VDDCPU_B voltages and supports
the same OPPs as the Amlogic A311D SoC from the same G12B family.
Suggested-by: Dongjin Kim <tobetter@hardkernel.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20200915152432.30616-4-narmstrong@baylibre.com
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../dts/amlogic/meson-g12b-odroid-n2-plus.dts | 31 +++++++++++++++++++
2 files changed, 32 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 4e2239ffcaa5..b0b3d6791499 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
new file mode 100644
index 000000000000..5de2815ba99d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */
+#include "meson-g12b-a311d.dtsi"
+#include "meson-g12b-odroid-n2.dtsi"
+
+/ {
+ compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b";
+ model = "Hardkernel ODROID-N2Plus";
+};
+
+&vddcpu_a {
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwms = <&pwm_AO_cd 1 1500 0>;
+};
+
+&vddcpu_b {
+ regulator-min-microvolt = <680000>;
+ regulator-max-microvolt = <1040000>;
+
+ pwms = <&pwm_AO_cd 1 1500 0>;
+};
+
--
2.29.2

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@ -1,10 +1,10 @@
From beb4dcdf3cd73f243563228528bc62e3caa881e8 Mon Sep 17 00:00:00 2001
Message-Id: <beb4dcdf3cd73f243563228528bc62e3caa881e8.1610380198.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1610380198.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1610380198.git.stefan@agner.ch>
From 0a4d355fe7b8245427ba7d774b082ea5f2d257d9 Mon Sep 17 00:00:00 2001
Message-Id: <0a4d355fe7b8245427ba7d774b082ea5f2d257d9.1612541102.git.stefan@agner.ch>
In-Reply-To: <516c081bcdd8f248982588aa8ca5bd8d24b2e7ef.1612541102.git.stefan@agner.ch>
References: <516c081bcdd8f248982588aa8ca5bd8d24b2e7ef.1612541102.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Mon, 11 Jan 2021 11:38:54 +0100
Subject: [PATCH 09/10] arm64: dts: meson: g12b: add GPIO fan support
Subject: [PATCH 3/4] arm64: dts: meson: g12b: add GPIO fan support
Add simple GPIO fan node to support a fan on GPIO J8. Unfortunately the
pad used to control the fan does not support real PWM, hence the RPM

View File

@ -1,10 +1,10 @@
From 8ff3ba007f500ec4f21361fcac4ec7a5b67bcf7e Mon Sep 17 00:00:00 2001
Message-Id: <8ff3ba007f500ec4f21361fcac4ec7a5b67bcf7e.1610382778.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1610382778.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1610382778.git.stefan@agner.ch>
From 575ca5decaccee6cdea036ce88711dac6672cc4b Mon Sep 17 00:00:00 2001
Message-Id: <575ca5decaccee6cdea036ce88711dac6672cc4b.1612541102.git.stefan@agner.ch>
In-Reply-To: <516c081bcdd8f248982588aa8ca5bd8d24b2e7ef.1612541102.git.stefan@agner.ch>
References: <516c081bcdd8f248982588aa8ca5bd8d24b2e7ef.1612541102.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Mon, 11 Jan 2021 15:53:55 +0100
Subject: [PATCH 10/10] arm64: dts: meson: g12b: odroid-n2: add fan as cooling
Subject: [PATCH 4/4] arm64: dts: meson: g12b: odroid-n2: add fan as cooling
device
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8

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@ -1,42 +0,0 @@
From 47f804dc970e2b1f71f1f032a0da2ef3b8315be0 Mon Sep 17 00:00:00 2001
Message-Id: <47f804dc970e2b1f71f1f032a0da2ef3b8315be0.1606829302.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Fri, 23 Oct 2020 11:41:39 +0200
Subject: [PATCH 4/7] arm64: dts: meson: odroid-n2 plus: fix vddcpu_a pwm
On the odroid N2 plus, cpufreq is not available due to an error on the cpu
regulators. vddcpu a and b get the same PWM. The one provided to vddcpu A
is incorrect. Because vddcpu B PWM is busy the regulator cannot register:
> pwm-regulator regulator-vddcpu-b: Failed to get PWM: -16
Like on the odroid n2, use PWM A out of GPIOE_2 for vddcpu A to fix the
problem
Fixes: 98d24896ee11 ("arm64: dts: meson: add support for the ODROID-N2+")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201023094139.809379-1-jbrunet@baylibre.com
---
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
index 5de2815ba99d..ce1198ad34e4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts
@@ -19,7 +19,7 @@ &vddcpu_a {
regulator-min-microvolt = <680000>;
regulator-max-microvolt = <1040000>;
- pwms = <&pwm_AO_cd 1 1500 0>;
+ pwms = <&pwm_ab 0 1500 0>;
};
&vddcpu_b {
--
2.29.2

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@ -1,41 +0,0 @@
From 35d2de7b27bc3f4bc2d977fb6b7671d9ba889496 Mon Sep 17 00:00:00 2001
Message-Id: <35d2de7b27bc3f4bc2d977fb6b7671d9ba889496.1606829302.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Tue, 1 Dec 2020 00:32:23 +0100
Subject: [PATCH 6/7] arm64: dts: meson: g12b: odroid-n2: fix PHY deassert
timing requirements
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
egisters. This fixes an issue where the Ethernet link doesn't come up
when using ip link set down/up:
[ 29.360965] meson8b-dwmac ff3f0000.ethernet eth0: Link is Down
[ 34.569012] meson8b-dwmac ff3f0000.ethernet eth0: PHY [0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31)
[ 34.676732] meson8b-dwmac ff3f0000.ethernet: Failed to reset the dma
[ 34.678874] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 34.687850] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_open: Hw setup failed
Fixes: 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line")
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
index 40390feba053..445d90d25aa3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
@@ -415,7 +415,7 @@ external_phy: ethernet-phy@0 {
max-speed = <1000>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;
--
2.29.2

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@ -1,152 +0,0 @@
From 40e8e7e28c44993e352195b359c4d4540bfb2105 Mon Sep 17 00:00:00 2001
Message-Id: <40e8e7e28c44993e352195b359c4d4540bfb2105.1606829302.git.stefan@agner.ch>
In-Reply-To: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
References: <9d2a2b44e67b0ef49e534c097e8b5e3e1173b033.1606829302.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Tue, 1 Dec 2020 00:32:23 +0100
Subject: [PATCH 7/7] arm64: dts: meson: fix PHY deassert timing requirements
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
egisters. This fixes an issue seen on ODROID-C2 where the Ethernet
link doesn't come up when using ip link set down/up:
[ 6630.714855] meson8b-dwmac c9410000.ethernet eth0: Link is Down
[ 6630.785775] meson8b-dwmac c9410000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=36)
[ 6630.893071] meson8b-dwmac c9410000.ethernet: Failed to reset the dma
[ 6630.893800] meson8b-dwmac c9410000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 6630.902835] meson8b-dwmac c9410000.ethernet eth0: stmmac_open: Hw setup failed
Fixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings")
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 +-
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
index 7be3e354093b..de27beafe9db 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
@@ -165,7 +165,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 70fcfb7b0683..50de1d01e565 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -200,7 +200,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 222ee8069cfa..9b0b81f191f1 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -126,7 +126,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
index ad812854a107..a350fee1264d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
@@ -147,7 +147,7 @@ eth_phy0: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index b08c4537f260..b2ab05c22090 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -82,7 +82,7 @@ external_phy: ethernet-phy@0 {
/* External PHY reset is shared with internal PHY Led signal */
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index bff8ec2c1c70..e38d9e50caa7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -194,7 +194,7 @@ external_phy: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index 83eca3af44ce..dfa7a37a1281 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -112,7 +112,7 @@ external_phy: ethernet-phy@0 {
max-speed = <1000>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index ea45ae0c71b7..8edbfe040805 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -64,7 +64,7 @@ external_phy: ethernet-phy@0 {
/* External PHY reset is shared with internal PHY Led signal */
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio_intc>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
index c89c9f846fb1..dde7cfe12cff 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
@@ -114,7 +114,7 @@ external_phy: ethernet-phy@0 {
max-speed = <1000>;
reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
+ reset-deassert-us = <80000>;
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
};
};
--
2.29.2

View File

@ -22,13 +22,13 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/hassos-hook.sh"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.82"
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.13"
BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/nuc/kernel.config"
BR2_LINUX_KERNEL_LZ4=y
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_4=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_9=y
BR2_PACKAGE_BUSYBOX_CONFIG="$(BR2_EXTERNAL_HASSOS_PATH)/busybox.config"
BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES=y
BR2_PACKAGE_PROCPS_NG=y

View File

@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c2/hassos-hook.sh"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.9.13"
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.13"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"

View File

@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c4 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c4/hassos-hook.sh"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.9.13"
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.13"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"

View File

@ -22,7 +22,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2/hassos-hook.sh"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.9.13"
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.13"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/kernel-amlogic.config"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-n2/kernel.config"

View File

@ -23,7 +23,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4 $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-xu4/hassos-hook.sh"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.9.13"
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.13"
BR2_LINUX_KERNEL_DEFCONFIG="exynos"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
BR2_LINUX_KERNEL_LZ4=y

View File

@ -23,13 +23,13 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/hassos-hook.sh"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.82"
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.13"
BR2_LINUX_KERNEL_DEFCONFIG="x86_64"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config $(BR2_EXTERNAL_HASSOS_PATH)/board/intel/ova/kernel.config"
BR2_LINUX_KERNEL_LZ4=y
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_4=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_9=y
BR2_PACKAGE_BUSYBOX_CONFIG="$(BR2_EXTERNAL_HASSOS_PATH)/busybox.config"
BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES=y
BR2_PACKAGE_PROCPS_NG=y

View File

@ -24,7 +24,7 @@ BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_HASSOS_PATH)/scripts/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker $(BR2_EXTERNAL_HASSOS_PATH)/board/asus/hassos-hook.sh"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.4.82"
BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.13"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker/kernel.config"
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_HASSOS_PATH)/kernel/hassos.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/docker.config $(BR2_EXTERNAL_HASSOS_PATH)/kernel/device-support.config"
@ -96,7 +96,7 @@ BR2_TARGET_UBOOT_SPL_NAME="idbloader.img"
BR2_PACKAGE_HOST_UBOOT_TOOLS=y
BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT=y
BR2_PACKAGE_HOST_UBOOT_TOOLS_BOOT_SCRIPT_SOURCE="$(BR2_EXTERNAL_HASSOS_PATH)/board/asus/tinker/uboot-boot.ush"
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_4=y
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_9=y
BR2_PACKAGE_HOST_DOSFSTOOLS=y
BR2_PACKAGE_HOST_E2FSPROGS=y
BR2_PACKAGE_HOST_GPTFDISK=y

View File

@ -1,11 +0,0 @@
#!/bin/bash
set -e
if [ -z "$1" ]; then
echo "Need a kernel version!"
exit 1
fi
sed -i "s/BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE=\".*\"/BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE=\"$1\"/g" buildroot-external/configs/odroid_*
sed -i "s/| Odroid\(.*\) | .* |/| Odroid\1 | $1 |/g" Documentation/kernel.md
git commit -m "Odroid: Update kernel $1" buildroot-external/configs/* Documentation/kernel.md

View File

@ -6,6 +6,6 @@ if [ -z "$1" ]; then
exit 1
fi
sed -i "s/BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE=\".*\"/BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE=\"$1\"/g" buildroot-external/configs/{intel_nuc,ova,tinker}_defconfig
sed -i "s/| \(Open Virtual Appliance\|Intel NUC\|Tinker Board\) | .* |/| \1 | $1 |/g" Documentation/kernel.md
sed -i "s/BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE=\".*\"/BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE=\"$1\"/g" buildroot-external/configs/{intel_nuc,ova,tinker,odroid*}_defconfig
sed -i "s/| \(Open Virtual Appliance\|Intel NUC\|Tinker Board\|Odroid-.*\) | .* |/| \1 | $1 |/g" Documentation/kernel.md
git commit -m "Linux: Update kernel $1" buildroot-external/configs/* Documentation/kernel.md