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Fix patches p2
This commit is contained in:
Pascal Vizeli
parent
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commit
6b3919beeb
@ -1,13 +1,15 @@
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From 9afaacdda672452b52a95b9bcea259646c3b5850 Mon Sep 17 00:00:00 2001
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From 6add848d66a7bdebed73416a3cf27b8bf10a2cd8 Mon Sep 17 00:00:00 2001
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From: Pascal Vizeli <pvizeli@syshack.ch>
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From: Pascal Vizeli <pvizeli@syshack.ch>
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Date: Sat, 19 May 2018 17:35:26 +0200
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Date: Sat, 19 May 2018 17:58:01 +0200
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Subject: [PATCH 1/1] p2
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Subject: [PATCH 1/1] p2
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---
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---
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arch/arm/cpu/Makefile | 7 +++++++
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arch/arm/cpu/Makefile | 7 +++
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arch/arm/cpu/sm_as.S | 11 -----------
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arch/arm/cpu/hyp.S | 115 ++++++++++++++++++++++++++++++++++++++++++
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arch/arm/include/asm/secure.h | 2 ++
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arch/arm/cpu/sm_as.S | 11 ----
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3 files changed, 9 insertions(+), 11 deletions(-)
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arch/arm/include/asm/secure.h | 2 +
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4 files changed, 124 insertions(+), 11 deletions(-)
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create mode 100644 arch/arm/cpu/hyp.S
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diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
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diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
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index 0316d25..6d67b42 100644
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index 0316d25..6d67b42 100644
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@ -27,6 +29,127 @@ index 0316d25..6d67b42 100644
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#
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#
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# Any variants can be called as start-armxyz.S
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# Any variants can be called as start-armxyz.S
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#
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#
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diff --git a/arch/arm/cpu/hyp.S b/arch/arm/cpu/hyp.S
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new file mode 100644
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index 0000000..435d416
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--- /dev/null
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+++ b/arch/arm/cpu/hyp.S
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@@ -0,0 +1,115 @@
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+#include <linux/linkage.h>
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+#include <asm/system.h>
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+#include <asm/opcodes-virt.h>
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+
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+.arch_extension sec
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+.arch_extension virt
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+
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+.section ".text_bare_init_","ax"
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+
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+.data
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+ .align 2
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+ENTRY(__boot_cpu_mode)
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+ .long 0
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+.text
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+
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+ENTRY(__hyp_install)
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+ mrs r12, cpsr
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+ and r12, r12, #MODE_MASK
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+
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+ @ Save the initial CPU state
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+ adr r0, .L__boot_cpu_mode_offset
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+ ldr r1, [r0]
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+ str r12, [r0, r1]
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+
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+ cmp r12, #HYP_MODE
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+ movne pc, lr @ give up if the CPU is not in HYP mode
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+
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+ @ Now install the hypervisor stub:
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+ adr r12, __hyp_vectors
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+ mcr p15, 4, r12, c12, c0, 0 @ set hypervisor vector base (HVBAR)
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+
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+ @ Disable all traps, so we don't get any nasty surprise
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+ mov r12, #0
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+ mcr p15, 4, r12, c1, c1, 0 @ HCR
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+ mcr p15, 4, r12, c1, c1, 2 @ HCPTR
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+ mcr p15, 4, r12, c1, c1, 3 @ HSTR
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+
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+THUMB( orr r12, #(1 << 30) ) @ HSCTLR.TE
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+ mcr p15, 4, r12, c1, c0, 0 @ HSCTLR
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+
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+ mrc p15, 4, r12, c1, c1, 1 @ HDCR
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+ and r12, #0x1f @ Preserve HPMN
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+ mcr p15, 4, r12, c1, c1, 1 @ HDCR
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+
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+ @ Make sure NS-SVC is initialised appropriately
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+ mrc p15, 0, r12, c1, c0, 0 @ SCTLR
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+ orr r12, #(1 << 5) @ CP15 barriers enabled
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+ bic r12, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
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+ bic r12, #(3 << 19) @ WXN and UWXN disabled
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+ mcr p15, 0, r12, c1, c0, 0 @ SCTLR
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+
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+ mrc p15, 0, r12, c0, c0, 0 @ MIDR
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+ mcr p15, 4, r12, c0, c0, 0 @ VPIDR
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+
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+ mrc p15, 0, r12, c0, c0, 5 @ MPIDR
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+ mcr p15, 4, r12, c0, c0, 5 @ VMPIDR
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+ bx lr
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+ENDPROC(__hyp_install)
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+
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+ENTRY(armv7_hyp_install)
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+ mov r2, lr
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+
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+ bl __hyp_install
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+
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+ /* set the cpu to SVC32 mode, mask irq and fiq */
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+ mrs r12 , cpsr
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+ eor r12, r12, #HYP_MODE
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+ tst r12, #MODE_MASK
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+ bic r12 , r12 , #MODE_MASK
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+ orr r12 , r12 , #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
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+THUMB( orr r12 , r12 , #PSR_T_BIT )
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+ bne 1f
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+ orr r12, r12, #PSR_A_BIT
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+ adr lr, 2f
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+ msr spsr_cxsf, r12
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+ __MSR_ELR_HYP(14)
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+ __ERET
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+1: msr cpsr_c, r12
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+2:
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+ mov pc, r2
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+ENDPROC(armv7_hyp_install)
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+
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+ENTRY(armv7_switch_to_hyp)
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+ mov r0, lr
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+ mov r1, sp @ save SVC copy of LR and SP
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+ isb
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+ hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
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+ mov sp, r1
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+ mov lr, r0 @ restore SVC copy of LR and SP
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+
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+ bx lr
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+ENDPROC(armv7_switch_to_hyp)
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+
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+.align 2
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+.L__boot_cpu_mode_offset:
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+ .long __boot_cpu_mode - .
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+
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+/* The HYP trap is crafted to match armv7_switch_to_hyp() */
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+__hyp_do_trap:
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+ mov lr, r0
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+ mov sp, r1
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+ bx lr
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+ENDPROC(__hyp_do_trap)
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+
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+.align 5
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+__hyp_vectors:
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+__hyp_reset: W(b) .
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+__hyp_und: W(b) .
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+__hyp_svc: W(b) .
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+__hyp_pabort: W(b) .
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+__hyp_dabort: W(b) .
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+__hyp_trap: W(b) __hyp_do_trap
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+__hyp_irq: W(b) .
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+__hyp_fiq: W(b) .
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+ENDPROC(__hyp_vectors)
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diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
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diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
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index 0d01e1b..de6cd04 100644
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index 0d01e1b..de6cd04 100644
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--- a/arch/arm/cpu/sm_as.S
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--- a/arch/arm/cpu/sm_as.S
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