Merge pull request #172 from home-assistant/ota-odriod

odroid-c2: initial import

Documentation/boards/odroid-c2.md

@@ -0,0 +1,22 @@
+# Odroid-C2
+
+## eMMC
+
+eMMC support is provided transparently. Just flash the image to the eMMC board as you would an SD card.
+
+## Console
+
+By default, console access is granted over the serial header and over HDMI. Certain startup messages will only appear on the serial console by default. To show the messages on the HDMI console instead, swap the order of the two consoles in the `cmdline.txt` file on the boot partition. You can also delete the AML0 console if you don't plan on using the serial adapter.
+eg. `console=ttyAML0,115200n8 console=tty0`
+
+## USB
+
+A long-standing kernel bug currently results in some odd behavior. To use the USB, a device must be plugged into one of the USB ports at hard boot. If all devices are removed from the USB ports, the USB will cease to function until a reboot.
+
+### OTG
+
+The OTG USB is untested.
+
+## GPIO
+
+Refer to [the odroid wiki](https://wiki.odroid.com/odroid-c2/hardware/expansion_connectors).

Documentation/development.md

@@ -0,0 +1,24 @@
+# Development
+
+## Boot system
+
+`BOOT_SYS`:
+- efi
+- hyprid
+- spl
+- mbr
+
+HassOS is basicly used GPT. But for use GPT we need own the first 1024 of
+boot drive. Is that not possible, you can use MBR for your device, they work also with SPLs.
+
+Hyprid and SPL use both a hyprid MBR/GPT table but SPL move the GPT header 8MB for give space to write SPL and boot images before.
+
+`BOOTLOADER`:
+- uboot
+- barebox
+
+We support mainly uboot but for uefi system we can also use barebox. In future we hope to remove barebox with uboot also on uefi.
+
+`DISK_SIZE`:
+Default 2. That is the size of end image in GB.
+

Documentation/kernel.md

@@ -5,3 +5,4 @@
 |-------|---------|
 | Open Virtual Applicance | 4.14.59 |
 | Raspberry Pi | 4.14.58 |
+| Odroid-C2 | 4.14.36 |

buildroot-external/Config.in

@@ -3,3 +3,4 @@ source "$BR2_EXTERNAL_HASSOS_PATH/package/libapparmor/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/apparmor/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/bluetooth-bcm43xx/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/bluetooth-rtl8723/Config.in"
+source "$BR2_EXTERNAL_HASSOS_PATH/package/hardkernel-boot/Config.in"

buildroot-external/board/asus/hassos-hook.sh

@@ -0,0 +1,28 @@
+#!/bin/bash
+
+function hassos_pre_image() {
+    local BOOT_DATA="$(path_boot_dir)"
+    local SPL_IMG="$(path_spl_img)"
+
+    cp -t ${BOOT_DATA} \
+        ${BINARIES_DIR}/boot.scr \
+        ${BINARIES_DIR}/rk3288-tinker.dtb
+
+    echo "console=tty1" > ${BOOT_DATA}/cmdline.txt
+
+    # Create boot binary
+    rm -f ${BINARIES_DIR}/u-boot-spl-dtb.img
+    mkimage -n rk3288 -T rksd -d ${BINARIES_DIR}/u-boot-spl-dtb.bin ${BINARIES_DIR}/u-boot-spl-dtb.img
+    cat ${BINARIES_DIR}/u-boot-dtb.bin >> ${BINARIES_DIR}/u-boot-spl-dtb.img
+
+    # SPL
+    create_spl_image
+
+    dd if=${BINARIES_DIR}/u-boot-spl-dtb.img of=${SPL_IMG} conv=notrunc bs=512 seek=64
+}
+
+
+function hassos_post_image() {
+    convert_disk_image_gz
+}
+

buildroot-external/board/asus/tinker/meta

@@ -1,5 +1,5 @@
 BOARD_ID=tinker
-BOARD_NAME="Tinker Board"
+BOARD_NAME="Asus TinkerBoard"
 CHASSIS=embedded
 BOOTLOADER=uboot
 KERNEL_FILE=zImage

buildroot-external/board/asus/tinker/uboot.config

@@ -1,4 +1,6 @@
 # CONFIG_USB_STORAGE is not set
+# CONFIG_DOS_PARTITION is not set
 CONFIG_DM_VIDEO=y
 CONFIG_CMD_FILEENV=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_OFFSET=0x25100000

buildroot-external/board/hardkernel/odroid-c2/boot-env.txt

@@ -0,0 +1,131 @@
+
+
+# Custom modeline!
+# To use custom modeline you need to disable all the below resolutions
+# and setup your own!
+# For more information check our wiki:
+# http://odroid.com/dokuwiki/doku.php?id=en:c2_hdmi_autosetting
+# Example below:
+#m=custombuilt
+#modeline=1920,1200,154000,74040,60,1920,1968,2000,2080,1200,1202,1208,1235,1,0,1
+
+# 480 Lines (720x480)
+#m=480i60hz
+#m=480i_rpt
+#m=480p60hz
+#m=480p_rpt
+
+# 576 Lines (720x576)
+#m=576i50hz
+#m=576i_rpt
+#m=576p50hz
+#m=576p_rpt
+
+# 720 Lines (1280x720)
+#m=720p50hz
+#m=720p60hz
+
+# 1080 Lines (1920x1080)
+#m=1080i60hz
+m=1080p60hz
+#m=1080i50hz
+#m=1080p50hz
+#m=1080p24hz
+
+# 4K (3840x2160)
+#m=2160p30hz
+#m=2160p25hz
+#m=2160p24hz
+#m=smpte24hz
+#m=2160p50hz
+#m=2160p60hz
+#m=2160p50hz420
+#m=2160p60hz420
+
+### VESA modes ###
+#m=640x480p60hz
+#m=800x480p60hz
+#m=480x800p60hz
+#m=800x600p60hz
+#m=1024x600p60hz
+#m=1024x768p60hz
+#m=1280x800p60hz
+#m=1280x1024p60hz
+#m=1360x768p60hz
+#m=1440x900p60hz
+#m=1600x900p60hz
+#m=1680x1050p60hz
+#m=1600x1200p60hz
+#m=1920x1200p60hz
+#m=2560x1080p60hz
+#m=2560x1440p60hz
+#m=2560x1600p60hz
+#m=3440x1440p60hz
+
+# HDMI BPP Mode
+m_bpp=32
+#m_bpp=24
+#m_bpp=16
+
+# HDMI DVI/VGA modes
+# By default its set to HDMI, if needed change below.
+# Uncomment only a single Line.
+#vout=dvi
+#vout=vga
+
+# HDMI HotPlug Detection control
+# Allows you to force HDMI thinking that the cable is connected.
+# true = HDMI will believe that cable is always connected
+# false = will let board/monitor negotiate the connection status
+hpd=true
+#hpd=false
+
+# Monitor output
+# Controls if HDMI PHY should output anything to the monitor
+monitor_onoff=false
+
+# Server Mode (aka. No Graphics)
+# Setting nographics to 1 will disable all video subsystem
+# This mode is ideal of server type usage. (Saves ~300Mb of RAM)
+nographics=0
+
+# Meson Timer
+# 1 - Meson Timer
+# 0 - Arch Timer
+# Using meson_timer improves the video playback however it breaks KVM (virtualization).
+# Using arch timer allows KVM/Virtualization to work however you'll experience poor video
+mesontimer=1
+
+# UHS (Ultra High Speed) MicroSD mode enable/disable
+disableuhs=false
+
+# MicroSD Card Detection enable/disable
+# Force the MMC controlled to believe that a card is connected.
+mmc_removable=true
+
+# USB Multi WebCam tweak
+# Only enable this if you use it.
+usbmulticam=false
+
+# CPU Frequency / Cores control
+###########################################
+### WARNING!!! WARNING!!! WARNING!!!
+# Before changing anything here please read the wiki entry:
+# http://odroid.com/dokuwiki/doku.php?id=en:c2_set_cpu_freq
+#
+# MAX CPU's
+#maxcpus=1
+#maxcpus=2
+#maxcpus=3
+maxcpus=4
+
+# MAX Frequency
+#max_freq=2016
+#max_freq=1944
+#max_freq=1944
+#max_freq=1920
+#max_freq=1896
+#max_freq=1752
+#max_freq=1680
+#max_freq=1656
+max_freq=1536

buildroot-external/board/hardkernel/odroid-c2/hassos-hook.sh

@@ -0,0 +1,27 @@
+#!/bin/bash
+
+function hassos_pre_image() {
+    local BOOT_DATA="$(path_boot_dir)"
+    local BL1="${BINARIES_DIR}/bl1.bin.hardkernel"
+    local UBOOT_GXBB="${BINARIES_DIR}/u-boot.gxbb"
+    local spl_img="$(path_spl_img)"
+
+    cp ${BINARIES_DIR}/boot.scr ${BOOT_DATA}/boot.scr
+    cp ${BOARD_DIR}/boot-env.txt ${BOOT_DATA}/config.txt
+    cp ${BINARIES_DIR}/meson-gxbb-odroidc2.dtb ${BOOT_DATA}/meson-gxbb-odroidc2.dtb
+
+    echo "console=tty0 console=ttyAML0,115200n8" > ${BOOT_DATA}/cmdline.txt
+
+    # SPL
+    create_spl_image
+
+    dd if=${BL1} of=${spl_img} conv=notrunc bs=1 count=440
+    dd if=${BL1} of=${spl_img} conv=notrunc bs=512 skip=1 seek=1
+    dd if=${UBOOT_GXBB} of=${spl_img} conv=notrunc bs=512 seek=97
+}
+
+
+function hassos_post_image() {
+    convert_disk_image_gz
+}
+

buildroot-external/board/hardkernel/odroid-c2/meta

@@ -0,0 +1,7 @@
+BOARD_ID=odroid-c2
+BOARD_NAME="Hardkernel Odroid-C2"
+CHASSIS=embedded
+BOOTLOADER=uboot
+KERNEL_FILE=Image
+BOOT_SYS=mbr
+BOOT_ENV_SIZE=0x2000

buildroot-external/board/hardkernel/odroid-c2/patches/README

@@ -0,0 +1,2 @@
+kernel patches from
+https://github.com/superna9999/meta-meson/tree/sumo/recipes-kernel/linux/linux-yocto-meson64-4.14

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0001-ARM64-dts-meson-gxm-Add-support-for-Khadas-VIM2.patch

@@ -0,0 +1,455 @@
+From f802405c9aba2fb198d55fc010e7336f155c2713 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Wed, 2 Aug 2017 16:11:23 +0200
+Subject: [PATCH 01/39] ARM64: dts: meson-gxm: Add support for Khadas VIM2
+
+The Khadas VIM2 is a Single Board Computer, respin of the origin
+Khadas VIM board, using an Amlogic S912 SoC and more server oriented.
+
+It provides the same external connectors and header pinout, plus a SPI
+NOR Flash, a reprogrammable STM8S003 MCU, FPC Connector, Cooling FAN header
+and Pogo Pads Arrays.
+
+Cc: Gouwa <gouwa@szwesion.com>
+Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ Documentation/devicetree/bindings/arm/amlogic.txt  |   1 +
+ arch/arm64/boot/dts/amlogic/Makefile               |   1 +
+ .../boot/dts/amlogic/meson-gxm-khadas-vim2.dts     | 399 +++++++++++++++++++++
+ 3 files changed, 401 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+
+diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
+index 4e4bc0b..a445997 100644
+--- a/Documentation/devicetree/bindings/arm/amlogic.txt
++++ b/Documentation/devicetree/bindings/arm/amlogic.txt
+@@ -71,6 +71,7 @@ Board compatible values (alphabetically, grouped by SoC):
+ 
+   - "amlogic,q200" (Meson gxm s912)
+   - "amlogic,q201" (Meson gxm s912)
++  - "khadas,vim2" (Meson gxm s912)
+   - "kingnovel,r-box-pro" (Meson gxm S912)
+   - "nexbox,a1" (Meson gxm s912)
+ 
+diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
+index 543416b..747bcc3 100644
+--- a/arch/arm64/boot/dts/amlogic/Makefile
++++ b/arch/arm64/boot/dts/amlogic/Makefile
+@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
++dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
+ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+new file mode 100644
+index 0000000..32c138e
+--- /dev/null
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+@@ -0,0 +1,399 @@
++/*
++ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
++ * Copyright (c) 2017 BayLibre, SAS
++ * Author: Neil Armstrong <narmstrong@baylibre.com>
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/thermal/thermal.h>
++
++#include "meson-gxm.dtsi"
++
++/ {
++	compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
++	model = "Khadas VIM2";
++
++	aliases {
++		serial0 = &uart_AO;
++		serial1 = &uart_A;
++		serial2 = &uart_AO_B;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	memory@0 {
++		device_type = "memory";
++		reg = <0x0 0x0 0x0 0x80000000>;
++	};
++
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 0>;
++		io-channel-names = "buttons";
++		keyup-threshold-microvolt = <1710000>;
++
++		button-function {
++			label = "Function";
++			linux,code = <KEY_FN>;
++			press-threshold-microvolt = <10000>;
++		};
++	};
++
++	emmc_pwrseq: emmc-pwrseq {
++		compatible = "mmc-pwrseq-emmc";
++		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
++	};
++
++	gpio_fan: gpio-fan {
++		compatible = "gpio-fan";
++		gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
++			 &gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
++		/* Dummy RPM values since fan is optional */
++		gpio-fan,speed-map = <0 0
++				      1 1
++				      2 2
++				      3 3>;
++		cooling-min-level = <0>;
++		cooling-max-level = <3>;
++		#cooling-cells = <2>;
++	};
++
++	gpio-keys-polled {
++		compatible = "gpio-keys-polled";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		poll-interval = <100>;
++
++		button@0 {
++			label = "power";
++			linux,code = <KEY_POWER>;
++			gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_connector_in: endpoint {
++				remote-endpoint = <&hdmi_tx_tmds_out>;
++			};
++		};
++	};
++
++	pwmleds {
++		compatible = "pwm-leds";
++
++		power {
++			label = "vim:red:power";
++			pwms = <&pwm_AO_ab 1 7812500 0>;
++			max-brightness = <255>;
++			linux,default-trigger = "default-on";
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
++		clocks = <&wifi32k>;
++		clock-names = "ext_clock";
++	};
++
++	thermal-zones {
++		cpu-thermal {
++			polling-delay-passive = <250>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++
++			thermal-sensors = <&scpi_sensors 0>;
++
++			trips {
++				cpu_alert0: cpu-alert0 {
++					temperature = <70000>; /* millicelsius */
++					hysteresis = <2000>; /* millicelsius */
++					type = "active";
++				};
++
++				cpu_alert1: cpu-alert1 {
++					temperature = <80000>; /* millicelsius */
++					hysteresis = <2000>; /* millicelsius */
++					type = "passive";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&cpu_alert0>;
++					cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
++				};
++
++				map1 {
++					trip = <&cpu_alert1>;
++					cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>;
++				};
++
++				map2 {
++					trip = <&cpu_alert1>;
++					cooling-device =
++						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++
++				map3 {
++					trip = <&cpu_alert1>;
++					cooling-device =
++						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
++		};
++	};
++
++	vcc_3v3: regulator-vcc_3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "VCC_3V3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	vddio_ao18: regulator-vddio_ao18 {
++		compatible = "regulator-fixed";
++		regulator-name = "VDDIO_AO18";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++	};
++
++	vddio_boot: regulator-vddio_boot {
++		compatible = "regulator-fixed";
++		regulator-name = "VDDIO_BOOT";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++	};
++
++	vddao_3v3: regulator-vddao_3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "VDDAO_3V3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	wifi32k: wifi32k {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
++	};
++};
++
++&cec_AO {
++	status = "okay";
++	pinctrl-0 = <&ao_cec_pins>;
++	pinctrl-names = "default";
++	hdmi-phandle = <&hdmi_tx>;
++};
++
++&cpu0 {
++	cooling-min-level = <0>;
++	cooling-max-level = <6>;
++	#cooling-cells = <2>;
++};
++
++&cpu4 {
++	cooling-min-level = <0>;
++	cooling-max-level = <4>;
++	#cooling-cells = <2>;
++};
++
++&ethmac {
++	pinctrl-0 = <&eth_pins>;
++	pinctrl-names = "default";
++
++	/* Select external PHY by default */
++	phy-handle = <&external_phy>;
++
++	amlogic,tx-delay-ns = <2>;
++
++	/* External PHY reset is shared with internal PHY Led signals */
++	snps,reset-gpio = <&gpio GPIOZ_14 0>;
++	snps,reset-delays-us = <0 10000 1000000>;
++	snps,reset-active-low;
++
++	/* External PHY is in RGMII */
++	phy-mode = "rgmii";
++
++	status = "okay";
++};
++
++&external_mdio {
++	external_phy: ethernet-phy@0 {
++		/* Realtek RTL8211F (0x001cc916) */
++		reg = <0>;
++	};
++};
++
++&hdmi_tx {
++	status = "okay";
++	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
++	pinctrl-names = "default";
++};
++
++&hdmi_tx_tmds_port {
++	hdmi_tx_tmds_out: endpoint {
++		remote-endpoint = <&hdmi_connector_in>;
++	};
++};
++
++&i2c_A {
++	status = "okay";
++	pinctrl-0 = <&i2c_a_pins>;
++	pinctrl-names = "default";
++};
++
++&i2c_B {
++	status = "okay";
++	pinctrl-0 = <&i2c_b_pins>;
++	pinctrl-names = "default";
++
++	rtc: rtc@51 {
++		/* has to be enabled manually when a battery is connected: */
++		status = "disabled";
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		clock-output-names = "xin32k";
++	};
++};
++
++&ir {
++	status = "okay";
++	pinctrl-0 = <&remote_input_ao_pins>;
++	pinctrl-names = "default";
++	linux,rc-map-name = "rc-geekbox";
++};
++
++&pwm_AO_ab {
++	status = "okay";
++	pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
++	pinctrl-names = "default";
++	clocks = <&clkc CLKID_FCLK_DIV4>;
++	clock-names = "clkin0";
++};
++
++&pwm_ef {
++	status = "okay";
++	pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
++	pinctrl-names = "default";
++	clocks = <&clkc CLKID_FCLK_DIV4>;
++	clock-names = "clkin0";
++};
++
++&sd_emmc_a {
++	status = "okay";
++	pinctrl-0 = <&sdio_pins>;
++	pinctrl-names = "default";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	bus-width = <4>;
++	max-frequency = <100000000>;
++
++	non-removable;
++	disable-wp;
++
++	mmc-pwrseq = <&sdio_pwrseq>;
++
++	vmmc-supply = <&vddao_3v3>;
++	vqmmc-supply = <&vddio_boot>;
++
++	brcmf: wifi@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++	};
++};
++
++/* SD card */
++&sd_emmc_b {
++	status = "okay";
++	pinctrl-0 = <&sdcard_pins>;
++	pinctrl-names = "default";
++
++	bus-width = <4>;
++	cap-sd-highspeed;
++	max-frequency = <100000000>;
++	disable-wp;
++
++	cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
++	cd-inverted;
++
++	vmmc-supply = <&vddao_3v3>;
++	vqmmc-supply = <&vddio_boot>;
++};
++
++/* eMMC */
++&sd_emmc_c {
++	status = "okay";
++	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
++	pinctrl-names = "default";
++
++	bus-width = <8>;
++	cap-sd-highspeed;
++	cap-mmc-highspeed;
++	max-frequency = <200000000>;
++	non-removable;
++	disable-wp;
++	mmc-ddr-1_8v;
++	mmc-hs200-1_8v;
++
++	mmc-pwrseq = <&emmc_pwrseq>;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vddio_boot>;
++};
++
++/*
++ * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe
++ * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled
++ */
++&spifc {
++	status = "disabled";
++	pinctrl-0 = <&nor_pins>;
++	pinctrl-names = "default";
++
++	w25q32: spi-flash@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "winbond,w25q16", "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <3000000>;
++	};
++};
++
++/* This one is connected to the Bluetooth module */
++&uart_A {
++	status = "okay";
++	pinctrl-0 = <&uart_a_pins>;
++	pinctrl-names = "default";
++};
++
++/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
++&uart_AO {
++	status = "okay";
++	pinctrl-0 = <&uart_ao_a_pins>;
++	pinctrl-names = "default";
++};
++
++/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
++&uart_AO_B {
++	status = "okay";
++	pinctrl-0 = <&uart_ao_b_pins>;
++	pinctrl-names = "default";
++};
++
++&saradc {
++	status = "okay";
++	vref-supply = <&vddio_ao18>;
++};
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0002-ARM64-dts-meson-gxbb-allow-child-devices-on-the-USB-.patch

@@ -0,0 +1,41 @@
+From 841ec7b8484dee021a15fdc187cdadc1c89220f2 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 12 Jan 2017 01:38:26 +0100
+Subject: [PATCH 02/39] ARM64: dts: meson-gxbb: allow child devices on the USB
+ controller
+
+Add the size and adress cells to the USB controllers to allow specifying
+child devices (for example the USB hub on the Odroid-C2 which must be
+taken out of reset to work).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+index af834cd..7d38d55 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+@@ -73,6 +73,8 @@
+ 
+ 		usb0: usb@c9000000 {
+ 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			reg = <0x0 0xc9000000 0x0 0x40000>;
+ 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
+@@ -85,6 +87,8 @@
+ 
+ 		usb1: usb@c9100000 {
+ 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
++			#address-cells = <1>;
++			#size-cells = <0>;
+ 			reg = <0x0 0xc9100000 0x0 0x40000>;
+ 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0003-ARM64-dts-meson-gxbb-odroidc2-take-USB-hub-out-of-re.patch

@@ -0,0 +1,34 @@
+From 564bc89139a6bf0833cef64993dfe3fe2784c6a8 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 12 Jan 2017 01:39:20 +0100
+Subject: [PATCH 03/39] ARM64: dts: meson-gxbb-odroidc2: take USB hub out of
+ reset
+
+This takes the USB hub out of reset, otherwise the hub is not working.
+
+Fixes: 5a0803bd5ae ("ARM64: dts: meson-gxbb-odroidc2: Enable USB Nodes")
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+index 08b7bb7..c3a7b7f 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+@@ -310,4 +310,11 @@
+ 
+ &usb1 {
+ 	status = "okay";
++
++	hub@1 {
++		compatible = "usb5e3,610";
++		reg = <1>;
++		reset-gpios = <&gpio GPIOAO_4 GPIO_ACTIVE_LOW>;
++		reset-duration-us = <3000>;
++	};
+ };
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0004-phy-meson-add-USB3-PHY-support-for-Meson-GXL.patch

@@ -0,0 +1,260 @@
+From 563fa3aaad2752079c8ee05819bf9923370f39aa Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 26 Nov 2016 15:56:32 +0100
+Subject: [PATCH 04/39] phy: meson: add USB3 PHY support for Meson GXL
+
+This adds USB3 PHY driver found on Meson GXL and GXM SoCs.
+
+Unfortunately there are no datasheets available for any of these PHYs.
+Both drivers were written by reading the reference drivers provided by
+Amlogic and analyzing the registers on the kernel that was shipped with
+my board.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/phy/amlogic/Kconfig              |  13 ++
+ drivers/phy/amlogic/Makefile             |   1 +
+ drivers/phy/amlogic/phy-meson-gxl-usb3.c | 198 +++++++++++++++++++++++++++++++
+ 3 files changed, 212 insertions(+)
+ create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c
+
+diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
+index cb8f450..5d11a3e 100644
+--- a/drivers/phy/amlogic/Kconfig
++++ b/drivers/phy/amlogic/Kconfig
+@@ -13,6 +13,19 @@ config PHY_MESON8B_USB2
+ 	  Meson8b and GXBB SoCs.
+ 	  If unsure, say N.
+ 
++config PHY_MESON_GXL_USB3
++	tristate "Meson GXL and GXM USB3 PHY drivers"
++	default ARCH_MESON
++	depends on OF && (ARCH_MESON || COMPILE_TEST)
++	depends on USB_SUPPORT
++	select USB_COMMON
++	select GENERIC_PHY
++	select REGMAP_MMIO
++	help
++	  Enable this to support the Meson USB3 PHY found in Meson
++	  GXL and GXM SoCs.
++	  If unsure, say N.
++
+ config PHY_MESON_GXL_USB2
+ 	tristate "Meson GXL and GXM USB2 PHY drivers"
+ 	default ARCH_MESON
+diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
+index cfdc987..4fd8848 100644
+--- a/drivers/phy/amlogic/Makefile
++++ b/drivers/phy/amlogic/Makefile
+@@ -1,2 +1,3 @@
+ obj-$(CONFIG_PHY_MESON8B_USB2)		+= phy-meson8b-usb2.o
+ obj-$(CONFIG_PHY_MESON_GXL_USB2)	+= phy-meson-gxl-usb2.o
++obj-$(CONFIG_PHY_MESON_GXL_USB3)	+= phy-meson-gxl-usb3.o
+diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb3.c b/drivers/phy/amlogic/phy-meson-gxl-usb3.c
+new file mode 100644
+index 0000000..9af5222
+--- /dev/null
++++ b/drivers/phy/amlogic/phy-meson-gxl-usb3.c
+@@ -0,0 +1,198 @@
++/*
++ * Meson GXL USB3 PHY driver
++ *
++ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/reset.h>
++#include <linux/regmap.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/usb/of.h>
++#include <linux/workqueue.h>
++
++#define USB_R0							0x00
++	#define USB_R0_P30_FSEL_SHIFT				0
++	#define USB_R0_P30_FSEL_MASK				GENMASK(5, 0)
++	#define USB_R0_P30_PHY_RESET				BIT(6)
++	#define USB_R0_P30_TEST_POWERDOWN_HSP			BIT(7)
++	#define USB_R0_P30_TEST_POWERDOWN_SSP			BIT(8)
++	#define USB_R0_P30_ACJT_LEVEL_SHIFT			9
++	#define USB_R0_P30_ACJT_LEVEL_MASK			GENMASK(13, 9)
++	#define USB_R0_P30_TX_BOOST_LEVEL_SHIFT			14
++	#define USB_R0_P30_TX_BOOST_LEVEL_MASK			GENMASK(16, 14)
++	#define USB_R0_P30_LANE0_TX2RX_LOOPBACK			BIT(17)
++	#define USB_R0_P30_LANE0_EXT_PCLK_REQ			BIT(18)
++	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_SHIFT		19
++	#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		GENMASK(28, 19)
++	#define USB_R0_U2D_SS_SCALEDOWN_MODE_SHIFT		29
++	#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		GENMASK(30, 29)
++	#define USB_R0_U2D_ACT					BIT(31)
++
++#define USB_R1							0x04
++	#define USB_R1_U3H_BIGENDIAN_GS				BIT(0)
++	#define USB_R1_U3H_PME_ENABLE				BIT(1)
++	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_SHIFT		2
++	#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		GENMASK(6, 2)
++	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_SHIFT		7
++	#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		GENMASK(11, 7)
++	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_SHIFT		12
++	#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		GENMASK(15, 12)
++	#define USB_R1_U3H_HOST_U3_PORT_DISABLE			BIT(16)
++	#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT	BIT(17)
++	#define USB_R1_U3H_HOST_MSI_ENABLE			BIT(18)
++	#define USB_R1_U3H_FLADJ_30MHZ_REG_SHIFT		19
++	#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK			GENMASK(24, 19)
++	#define USB_R1_P30_PCS_TX_SWING_FULL_SHIFT		25
++	#define USB_R1_P30_PCS_TX_SWING_FULL_MASK		GENMASK(31, 25)
++
++#define USB_R2							0x08
++	#define USB_R2_P30_CR_DATA_IN_SHIFT			0
++	#define USB_R2_P30_CR_DATA_IN_MASK			GENMASK(15, 0)
++	#define USB_R2_P30_CR_READ				BIT(16)
++	#define USB_R2_P30_CR_WRITE				BIT(17)
++	#define USB_R2_P30_CR_CAP_ADDR				BIT(18)
++	#define USB_R2_P30_CR_CAP_DATA				BIT(19)
++	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_SHIFT		20
++	#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		GENMASK(25, 20)
++	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_SHIFT		26
++	#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		GENMASK(31, 26)
++
++#define USB_R3							0x0c
++	#define USB_R3_P30_SSC_ENABLE				BIT(0)
++	#define USB_R3_P30_SSC_RANGE_SHIFT			1
++	#define USB_R3_P30_SSC_RANGE_MASK			GENMASK(3, 1)
++	#define USB_R3_P30_SSC_REF_CLK_SEL_SHIFT		4
++	#define USB_R3_P30_SSC_REF_CLK_SEL_MASK			GENMASK(12, 4)
++	#define USB_R3_P30_REF_SSP_EN				BIT(13)
++	#define USB_R3_P30_LOS_BIAS_SHIFT			16
++	#define USB_R3_P30_LOS_BIAS_MASK			GENMASK(18, 16)
++	#define USB_R3_P30_LOS_LEVEL_SHIFT			19
++	#define USB_R3_P30_LOS_LEVEL_MASK			GENMASK(23, 19)
++	#define USB_R3_P30_MPLL_MULTIPLIER_SHIFT		24
++	#define USB_R3_P30_MPLL_MULTIPLIER_MASK			GENMASK(30, 24)
++
++#define USB_R4							0x10
++	#define USB_R4_P21_PORT_RESET_0				BIT(0)
++	#define USB_R4_P21_SLEEP_M0				BIT(1)
++	#define USB_R4_MEM_PD_SHIFT				2
++	#define USB_R4_MEM_PD_MASK				GENMASK(3, 2)
++	#define USB_R4_P21_ONLY					BIT(4)
++
++#define USB_R5							0x14
++	#define USB_R5_ID_DIG_SYNC				BIT(0)
++	#define USB_R5_ID_DIG_REG				BIT(1)
++	#define USB_R5_ID_DIG_CFG_SHIFT				2
++	#define USB_R5_ID_DIG_CFG_MASK				GENMASK(3, 2)
++	#define USB_R5_ID_DIG_EN_0				BIT(4)
++	#define USB_R5_ID_DIG_EN_1				BIT(5)
++	#define USB_R5_ID_DIG_CURR				BIT(6)
++	#define USB_R5_ID_DIG_IRQ				BIT(7)
++	#define USB_R5_ID_DIG_TH_SHIFT				8
++	#define USB_R5_ID_DIG_TH_MASK				GENMASK(15, 8)
++	#define USB_R5_ID_DIG_CNT_SHIFT				16
++	#define USB_R5_ID_DIG_CNT_MASK				GENMASK(23, 16)
++
++/* read-only register */
++#define USB_R6							0x18
++	#define USB_R6_P30_CR_DATA_OUT_SHIFT			0
++	#define USB_R6_P30_CR_DATA_OUT_MASK			GENMASK(15, 0)
++	#define USB_R6_P30_CR_ACK				BIT(16)
++
++#define RESET_COMPLETE_TIME				500
++
++struct phy_meson_gxl_usb3_priv {
++	struct regmap		*regmap;
++	struct phy		*this_phy;
++};
++
++static const struct regmap_config phy_meson_gxl_usb3_regmap_conf = {
++	.reg_bits = 32,
++	.val_bits = 32,
++	.reg_stride = 4,
++	.max_register = USB_R6,
++};
++
++static int phy_meson_gxl_usb3_power_on(struct phy *phy)
++{
++	struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
++
++	regmap_update_bits(priv->regmap, USB_R1,
++			   USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
++			   0x20 << USB_R1_U3H_FLADJ_30MHZ_REG_SHIFT);
++
++	return 0;
++}
++
++static const struct phy_ops phy_meson_gxl_usb3_ops = {
++	.power_on	= phy_meson_gxl_usb3_power_on,
++	.owner		= THIS_MODULE,
++};
++
++static int phy_meson_gxl_usb3_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct phy_meson_gxl_usb3_priv *priv;
++	struct resource *res;
++	struct phy *phy;
++	struct phy_provider *phy_provider;
++	void __iomem *base;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	priv->regmap = devm_regmap_init_mmio(dev, base,
++					     &phy_meson_gxl_usb3_regmap_conf);
++	if (IS_ERR(priv->regmap))
++		return PTR_ERR(priv->regmap);
++
++	phy = devm_phy_create(dev, np, &phy_meson_gxl_usb3_ops);
++	if (IS_ERR(phy)) {
++		dev_err(dev, "failed to create PHY\n");
++		return PTR_ERR(phy);
++	}
++
++	phy_set_drvdata(phy, priv);
++
++	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++
++	return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id phy_meson_gxl_usb3_of_match[] = {
++	{ .compatible = "amlogic,meson-gxl-usb3-phy", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb3_of_match);
++
++static struct platform_driver phy_meson_gxl_usb3_driver = {
++	.probe	= phy_meson_gxl_usb3_probe,
++	.driver	= {
++		.name		= "phy-meson-gxl-usb3",
++		.of_match_table	= phy_meson_gxl_usb3_of_match,
++	},
++};
++module_platform_driver(phy_meson_gxl_usb3_driver);
++
++MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
++MODULE_DESCRIPTION("Meson GXL USB3 PHY driver");
++MODULE_LICENSE("GPL");
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0005-usb-host-add-a-generic-platform-USB-roothub-driver.patch

@@ -0,0 +1,293 @@
+From 8dca632003156c7a4f2eb6238b6e299f3df03c55 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Tue, 10 Jan 2017 18:59:43 +0100
+Subject: [PATCH 05/39] usb: host: add a generic platform USB roothub driver
+
+Many SoC platforms have separate devices for the USB PHY which are
+registered through the generic PHY framework. These PHYs have to be
+enabled to make the USB controller actually work. They also have to be
+disabled again on shutdown/suspend.
+
+Currently (at least) the following HCI platform drivers are using custom
+code to obtain all PHYs via devicetree for the roothub/controller and
+disable/enable them when required:
+- ehci-platform.c has ehci_platform_power_{on,off}
+- xhci-mtk.c has xhci_mtk_phy_{init,exit,power_on,power_off}
+- ohci-platform.c has ohci_platform_power_{on,off}
+
+These drivers are not using the generic devicetree USB device bindings
+yet which were only introduced recently (documentation is available in
+devicetree/bindings/usb/usb-device.txt).
+With this new driver the usb2-phy and usb3-phy can be specified directly
+in the child-node of the corresponding port of the roothub via
+devicetree. This can be extended by not just parsing PHYs (some of the
+other drivers listed above are for example also parsing a list of clocks
+as well) when required.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ .../devicetree/bindings/usb/usb-roothub.txt        |  46 +++++++
+ drivers/usb/host/Kconfig                           |   3 +
+ drivers/usb/host/Makefile                          |   2 +
+ drivers/usb/host/platform-roothub.c                | 146 +++++++++++++++++++++
+ drivers/usb/host/platform-roothub.h                |  14 ++
+ 5 files changed, 211 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/usb/usb-roothub.txt
+ create mode 100644 drivers/usb/host/platform-roothub.c
+ create mode 100644 drivers/usb/host/platform-roothub.h
+
+diff --git a/Documentation/devicetree/bindings/usb/usb-roothub.txt b/Documentation/devicetree/bindings/usb/usb-roothub.txt
+new file mode 100644
+index 0000000..23b24b6
+--- /dev/null
++++ b/Documentation/devicetree/bindings/usb/usb-roothub.txt
+@@ -0,0 +1,46 @@
++Generic USB root-hub Properties
++
++similar to the USB device bindings (documented in usb-device.txt from the
++current directory) this provides support for configuring the root-hub.
++
++Required properties:
++- compatible: should be at least one of "usb1d6b,3", "usb1d6b,2"
++- reg: must be 0.
++- address-cells: must be 1
++- size-cells: must be 0
++
++Required sub-nodes:
++a sub-node per actual USB port is required. each sub-node supports the
++following properties:
++  Required properties:
++    - reg: the port number on the root-hub (mandatory)
++  Optional properties:
++    - phys: optional, from the *Generic PHY* bindings (mandatory needed
++      when phy-names is given)
++    - phy-names: optional, from the *Generic PHY* bindings; supported names
++      are "usb2-phy" or "usb3-phy"
++
++Example:
++	&usb1 {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		roothub@0 {
++			compatible = "usb1d6b,3", "usb1d6b,2";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0>;
++
++			port@1 {
++				reg = <1>;
++				usb-phy = <&usb2_phy1>, <&usb3_phy1>;
++				phy-names = "usb2-phy", "usb3-phy";
++			};
++
++			port@2 {
++				reg = <2>;
++				usb-phy = <&usb2_phy2>, <&usb3_phy2>;
++				phy-names = "usb2-phy", "usb3-phy";
++			};
++		};
++	}
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 92b1972..598ca56 100644
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -797,6 +797,9 @@ config USB_HCD_SSB
+ 
+ 	  If unsure, say N.
+ 
++config USB_PLATFORM_ROOTHUB
++	bool
++
+ config USB_HCD_TEST_MODE
+ 	bool "HCD test mode support"
+ 	---help---
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index 4ab2689..873ebd9 100644
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -30,6 +30,8 @@ obj-$(CONFIG_USB_WHCI_HCD)	+= whci/
+ 
+ obj-$(CONFIG_USB_PCI)	+= pci-quirks.o
+ 
++obj-$(CONFIG_USB_PLATFORM_ROOTHUB)	+= platform-roothub.o
++
+ obj-$(CONFIG_USB_EHCI_HCD)	+= ehci-hcd.o
+ obj-$(CONFIG_USB_EHCI_PCI)	+= ehci-pci.o
+ obj-$(CONFIG_USB_EHCI_HCD_PLATFORM)	+= ehci-platform.o
+diff --git a/drivers/usb/host/platform-roothub.c b/drivers/usb/host/platform-roothub.c
+new file mode 100644
+index 0000000..84837e4
+--- /dev/null
++++ b/drivers/usb/host/platform-roothub.c
+@@ -0,0 +1,146 @@
++/*
++ * platform roothub driver - a virtual PHY device which passes all phy_*
++ * function calls to multiple (actual) PHY devices. This is comes handy when
++ * initializing all PHYs on a root-hub (to keep them all in the same state).
++ *
++ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/device.h>
++#include <linux/list.h>
++#include <linux/phy/phy.h>
++#include <linux/of.h>
++#include <linux/usb/of.h>
++
++#include "platform-roothub.h"
++
++#define ROOTHUB_PORTNUM		0
++
++struct platform_roothub {
++	struct phy		*phy;
++	struct list_head	list;
++};
++
++static struct platform_roothub *platform_roothub_alloc(struct device *dev)
++{
++	struct platform_roothub *roothub_entry;
++
++	roothub_entry = devm_kzalloc(dev, sizeof(*roothub_entry), GFP_KERNEL);
++	if (!roothub_entry)
++		return ERR_PTR(-ENOMEM);
++
++	INIT_LIST_HEAD(&roothub_entry->list);
++
++	return roothub_entry;
++}
++
++static int platform_roothub_add_phy(struct device *dev,
++				    struct device_node *port_np,
++				    const char *con_id, struct list_head *list)
++{
++	struct platform_roothub *roothub_entry;
++	struct phy *phy = devm_of_phy_get(dev, port_np, con_id);
++
++	if (IS_ERR_OR_NULL(phy)) {
++		if (!phy || PTR_ERR(phy) == -ENODEV)
++			return 0;
++		else
++			return PTR_ERR(phy);
++	}
++
++	roothub_entry = platform_roothub_alloc(dev);
++	if (IS_ERR(roothub_entry))
++		return PTR_ERR(roothub_entry);
++
++	roothub_entry->phy = phy;
++
++	list_add_tail(&roothub_entry->list, list);
++
++	return 0;
++}
++
++struct platform_roothub *platform_roothub_init(struct device *dev)
++{
++	struct device_node *roothub_np, *port_np;
++	struct platform_roothub *plat_roothub;
++	int err;
++
++	roothub_np = usb_of_get_child_node(dev->of_node, ROOTHUB_PORTNUM);
++	if (!of_device_is_available(roothub_np))
++		return NULL;
++
++	plat_roothub = platform_roothub_alloc(dev);
++	if (IS_ERR(plat_roothub))
++		return plat_roothub;
++
++	for_each_available_child_of_node(roothub_np, port_np) {
++		err = platform_roothub_add_phy(dev, port_np, "usb2-phy",
++					       &plat_roothub->list);
++		if (err)
++			return ERR_PTR(err);
++
++		err = platform_roothub_add_phy(dev, port_np, "usb3-phy",
++					       &plat_roothub->list);
++		if (err)
++			return ERR_PTR(err);
++	}
++
++	return plat_roothub;
++}
++EXPORT_SYMBOL_GPL(platform_roothub_init);
++
++int platform_roothub_power_on(struct platform_roothub *plat_roothub)
++{
++	struct platform_roothub *roothub_entry;
++	struct list_head *head;
++	int err;
++
++	if (!plat_roothub)
++		return 0;
++
++	head = &plat_roothub->list;
++
++	list_for_each_entry(roothub_entry, head, list) {
++		err = phy_init(roothub_entry->phy);
++		if (err)
++			goto err_out;
++
++		err = phy_power_on(roothub_entry->phy);
++		if (err) {
++			phy_exit(roothub_entry->phy);
++			goto err_out;
++		}
++	}
++
++	return 0;
++
++err_out:
++	list_for_each_entry_continue_reverse(roothub_entry, head, list) {
++		phy_power_off(roothub_entry->phy);
++		phy_exit(roothub_entry->phy);
++	}
++
++	return err;
++}
++EXPORT_SYMBOL_GPL(platform_roothub_power_on);
++
++void platform_roothub_power_off(struct platform_roothub *plat_roothub)
++{
++	struct platform_roothub *roothub_entry;
++
++	if (!plat_roothub)
++		return;
++
++	list_for_each_entry_reverse(roothub_entry, &plat_roothub->list, list) {
++		phy_power_off(roothub_entry->phy);
++		phy_exit(roothub_entry->phy);
++	}
++}
++EXPORT_SYMBOL_GPL(platform_roothub_power_off);
+diff --git a/drivers/usb/host/platform-roothub.h b/drivers/usb/host/platform-roothub.h
+new file mode 100644
+index 0000000..bde0bf2
+--- /dev/null
++++ b/drivers/usb/host/platform-roothub.h
+@@ -0,0 +1,14 @@
++#ifndef USB_HOST_PLATFORM_ROOTHUB_H
++#define USB_HOST_PLATFORM_ROOTHUB_H
++
++struct phy;
++struct device_node;
++
++struct platform_roothub;
++
++struct platform_roothub *platform_roothub_init(struct device *dev);
++
++int platform_roothub_power_on(struct platform_roothub *plat_roothub);
++void platform_roothub_power_off(struct platform_roothub *plat_roothub);
++
++#endif /* USB_HOST_PLATFORM_ROOTHUB_H */
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0006-usb-host-xhci-plat-integrate-the-platform-roothub.patch

@@ -0,0 +1,146 @@
+From 55ba20ef5868e2a1fc3cefe264539affe55ef6b7 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 11 Jan 2017 11:34:59 +0100
+Subject: [PATCH 06/39] usb: host: xhci: plat: integrate the platform-roothub
+
+This enables the platform-roothub for the xhci-plat driver. This allows
+specifying a PHY for each port via devicetree. All PHYs will then be
+enabled/disabled by the platform-roothub driver.
+
+One example where this is required is the Amlogic GXL and GXM SoCs:
+They are using a dwc3 USB controller with up to three ports enabled on
+the internal roothub. Using only the top-level "phy" properties does not
+work here since one can only specify one "usb2-phy" and one "usb3-phy",
+while actually at least two "usb2-phy" have to be specified.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ Documentation/devicetree/bindings/usb/usb-xhci.txt |  7 ++++++
+ drivers/usb/host/Kconfig                           |  1 +
+ drivers/usb/host/xhci-plat.c                       | 26 +++++++++++++++++++++-
+ drivers/usb/host/xhci.h                            |  3 +++
+ 4 files changed, 36 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+index 7a69b8b..d0d8a67c 100644
+--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
++++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
+@@ -30,6 +30,13 @@ Optional properties:
+   - usb3-lpm-capable: determines if platform is USB3 LPM capable
+   - quirk-broken-port-ped: set if the controller has broken port disable mechanism
+ 
++sub-nodes:
++- optionally there can be a node for the root-hub, see usb-roothub.txt in the
++  current directory
++- one or more nodes with reg 1-31 for each port to which a device is connected.
++  See usb-device.txt in the current directory for more information.
++
++
+ Example:
+ 	usb@f0931000 {
+ 		compatible = "generic-xhci";
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 598ca56..8c3b11f 100644
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -36,6 +36,7 @@ config USB_XHCI_PCI
+ config USB_XHCI_PLATFORM
+ 	tristate "Generic xHCI driver for a platform device"
+ 	select USB_XHCI_RCAR if ARCH_RENESAS
++	select USB_PLATFORM_ROOTHUB
+ 	---help---
+ 	  Adds an xHCI host driver for a generic platform device, which
+ 	  provides a memory space and an irq.
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 1cb6eae..a80d585 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -281,10 +281,20 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ 			goto put_usb3_hcd;
+ 	}
+ 
+-	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
++	xhci->platform_roothub = platform_roothub_init(sysdev);
++	if (IS_ERR(xhci->platform_roothub)) {
++		ret = PTR_ERR(xhci->platform_roothub);
++		goto disable_clk;
++	}
++
++	ret = platform_roothub_power_on(xhci->platform_roothub);
+ 	if (ret)
+ 		goto disable_usb_phy;
+ 
++	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
++	if (ret)
++		goto disable_platform_roothub;
++
+ 	if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
+ 		xhci->shared_hcd->can_do_streams = 1;
+ 
+@@ -307,6 +317,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ dealloc_usb2_hcd:
+ 	usb_remove_hcd(hcd);
+ 
++disable_platform_roothub:
++	platform_roothub_power_off(xhci->platform_roothub);
++
+ disable_usb_phy:
+ 	usb_phy_shutdown(hcd->usb_phy);
+ 
+@@ -338,6 +351,8 @@ static int xhci_plat_remove(struct platform_device *dev)
+ 	usb_remove_hcd(xhci->shared_hcd);
+ 	usb_phy_shutdown(hcd->usb_phy);
+ 
++	platform_roothub_power_off(xhci->platform_roothub);
++
+ 	usb_remove_hcd(hcd);
+ 	usb_put_hcd(xhci->shared_hcd);
+ 
+@@ -370,6 +385,11 @@ static int __maybe_unused xhci_plat_suspend(struct device *dev)
+ 	if (!device_may_wakeup(dev) && !IS_ERR(xhci->clk))
+ 		clk_disable_unprepare(xhci->clk);
+ 
++	if (ret)
++		return ret;
++
++	platform_roothub_power_off(xhci->platform_roothub);
++
+ 	return ret;
+ }
+ 
+@@ -382,6 +402,10 @@ static int __maybe_unused xhci_plat_resume(struct device *dev)
+ 	if (!device_may_wakeup(dev) && !IS_ERR(xhci->clk))
+ 		clk_prepare_enable(xhci->clk);
+ 
++	ret = platform_roothub_power_on(xhci->platform_roothub);
++	if (ret)
++		return ret;
++
+ 	ret = xhci_priv_resume_quirk(hcd);
+ 	if (ret)
+ 		return ret;
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 2eaf6e1..552834c 100644
+--- a/drivers/usb/host/xhci.h
++++ b/drivers/usb/host/xhci.h
+@@ -34,6 +34,8 @@
+ #include	"xhci-ext-caps.h"
+ #include "pci-quirks.h"
+ 
++#include "platform-roothub.h"
++
+ /* xHCI PCI Configuration Registers */
+ #define XHCI_SBRN_OFFSET	(0x60)
+ 
+@@ -1735,6 +1737,7 @@ struct xhci_hcd {
+ 	int		msix_count;
+ 	/* optional clock */
+ 	struct clk		*clk;
++	struct platform_roothub	*platform_roothub;
+ 	/* data structures */
+ 	struct xhci_device_context_array *dcbaa;
+ 	struct xhci_ring	*cmd_ring;
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0007-ARM64-dts-meson-gxl-add-USB-host-support.patch

@@ -0,0 +1,99 @@
+From 547f8ce14bfc3d315dc8b64d0e2eff0c7be897d2 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 20 Nov 2016 00:23:52 +0100
+Subject: [PATCH 07/39] ARM64: dts: meson-gxl: add USB host support
+
+This adds USB host support to the Meson GXL SoC. A dwc3 controller is
+used for host-mode, while a dwc2 controller is used for device-mode only.
+The dwc3 controller's internal roothub has two USB2 ports enabled but no
+USB3 port. Each of the ports is supplied by a separate PHY. The USB pins
+are connected to the SoC's USBHOST_A and USBOTG_B pins.
+Due to the way the roothub works internally the USB PHYs are left
+enabled. When the dwc3 controller is disabled the PHY is never powered on
+so it does not draw any extra power. However, when the dwc3 host
+controller is enabled then all PHYs also have to be enabled, otherwise
+USB devices will not be detected (regardless of whether they are plugged
+into an enabled port or not). This means that only the dwc3 controller
+has to be enabled on boards with USB support (instead of requiring all
+boards to enable the PHYs additionally with the chance of forgetting to
+enable one and breaking all other ports with that as well).
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 59 ++++++++++++++++++++++++++++++
+ 1 file changed, 59 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+index fb8d76a..68ea67a 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+@@ -57,6 +57,65 @@
+ 			no-map;
+ 		};
+ 	};
++
++	soc {
++
++		usb0: usb@c9000000 {
++			compatible = "snps,dwc3";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0 0xc9000000 0x0 0x100000>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			dr_mode = "host";
++			maximum-speed = "high-speed";
++			snps,dis_u2_susphy_quirk;
++			phys = <&usb3_phy0>;
++			phy-names = "usb3-phy";
++			status = "disabled";
++
++			dwc3_roothub: roothub@0 {
++				compatible = "usb1d6b,3", "usb1d6b,2";
++				#address-cells = <1>;
++				#size-cells = <0>;
++				reg = <0>;
++
++				port@1 {
++					reg = <1>;
++					phys = <&usb2_phy0>;
++					phy-names = "usb2-phy";
++				};
++
++				port@2 {
++					reg = <2>;
++					phys = <&usb2_phy1>;
++					phy-names = "usb2-phy";
++				};
++			};
++		};
++	};
++};
++
++&apb {
++	usb2_phy0: phy@78000 {
++		compatible = "amlogic,meson-gxl-usb2-phy";
++		#phy-cells = <0>;
++		reg = <0x0 0x78000 0x0 0x20>;
++		status = "okay";
++	};
++
++	usb2_phy1: phy@78020 {
++		compatible = "amlogic,meson-gxl-usb2-phy";
++		#phy-cells = <0>;
++		reg = <0x0 0x78020 0x0 0x20>;
++		status = "okay";
++	};
++
++	usb3_phy0: phy@78080 {
++		compatible = "amlogic,meson-gxl-usb3-phy";
++		#phy-cells = <0>;
++		reg = <0x0 0x78080 0x0 0x20>;
++		status = "okay";
++	};
+ };
+ 
+ &ethmac {
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0008-ARM64-dts-meson-gxm-add-GXM-specific-USB-host-config.patch

@@ -0,0 +1,49 @@
+From 48d4988f2b3b93a6f17c0d1d5e6d932664bc0c74 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sat, 26 Nov 2016 00:17:22 +0100
+Subject: [PATCH 08/39] ARM64: dts: meson-gxm: add GXM specific USB host
+ configuration
+
+The USB configuration on GXM is slightly different than on GXL. The dwc3
+controller's internal hub has three USB2 ports (instead of 2 on GXL)
+along with a dedicated USB2 PHY for this port. However, it seems that
+there are no pins on GXM which would allow connecting the third port to
+a physical USB port.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+index 19a798d..5e4cb90 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+@@ -121,6 +121,23 @@
+ 	compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
+ };
+ 
++&apb {
++	usb2_phy2: phy@78040 {
++		compatible = "amlogic,meson-gxl-usb2-phy";
++		#phy-cells = <0>;
++		reg = <0x0 0x78040 0x0 0x20>;
++		status = "disabled";
++	};
++};
++
++&dwc3_roothub {
++	port@3 {
++		reg = <3>;
++		phys = <&usb2_phy2>;
++		phy-names = "usb2-phy";
++	};
++};
++
+ &saradc {
+ 	compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
+ };
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0009-ARM64-dts-meson-gx-Enable-USB-on-GXL-and-GXM-boards.patch

@@ -0,0 +1,129 @@
+From 1e5a4ee949281c47a03f5cee31226d803d396f48 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Thu, 13 Jul 2017 15:02:33 +0200
+Subject: [PATCH 09/39] ARM64: dts: meson-gx: Enable USB on GXL and GXM boards
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi            | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts     | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts   | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts    | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi          | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts          | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts            | 4 ++++
+ arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts             | 4 ++++
+ 9 files changed, 36 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+index 4157987..7ce9a62 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+@@ -236,3 +236,7 @@
+ 	pinctrl-0 = <&uart_ao_a_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
+index 977b424..6f2cd8e 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
+@@ -163,3 +163,7 @@
+ 	pinctrl-0 = <&uart_ao_a_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++       status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+index edc512a..89a5fd9 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+@@ -198,3 +198,7 @@
+ 	pinctrl-0 = <&uart_ao_b_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++       status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+index 64c54c9..4035891 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+@@ -242,3 +242,7 @@
+ 	pinctrl-0 = <&uart_ao_a_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++       status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+index 1b8f328..6338e6c 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+@@ -251,3 +251,7 @@
+ 	pinctrl-0 = <&uart_ao_a_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+index 129af90..7a1c20e 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+@@ -173,3 +173,7 @@
+ 	pinctrl-0 = <&uart_ao_a_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+index 32c138e..103575a 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+@@ -397,3 +397,7 @@
+ 	status = "okay";
+ 	vref-supply = <&vddio_ao18>;
+ };
++
++&usb0 {
++       status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+index 22c6977..cfde246 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+@@ -215,3 +215,7 @@
+ 	pinctrl-0 = <&uart_ao_a_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
+index 470f72b..9837a48 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
+@@ -237,3 +237,7 @@
+ 	pinctrl-0 = <&uart_ao_a_pins>;
+ 	pinctrl-names = "default";
+ };
++
++&usb0 {
++       status = "okay";
++};
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0010-ARM64-defconfig-add-CONFIG_MESON_EFUSE.patch

@@ -0,0 +1,28 @@
+From eb29dbaf90e217978d8abfab1912b11020825e28 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 13 Nov 2017 12:02:59 +0100
+Subject: [PATCH 10/39] ARM64: defconfig: add CONFIG_MESON_EFUSE
+
+Turn on CONFIG_MESON_EFUSE as module
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 34480e9..3cdfc74 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -541,6 +541,7 @@ CONFIG_PHY_XGENE=y
+ CONFIG_PHY_TEGRA_XUSB=y
+ CONFIG_QCOM_L2_PMU=y
+ CONFIG_QCOM_L3_PMU=y
++CONFIG_MESON_EFUSE=m
+ CONFIG_TEE=y
+ CONFIG_OPTEE=y
+ CONFIG_ARM_SCPI_PROTOCOL=y
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0011-ARM64-defconfig-enable-CEC-support.patch

@@ -0,0 +1,36 @@
+From 175366cb9e77fe54e6949f6599c0900cf0980b26 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 13 Nov 2017 12:09:40 +0100
+Subject: [PATCH 11/39] ARM64: defconfig: enable CEC support
+
+Turn on CONFIG_CEC_SUPPORT and CONFIG_CEC_PLATFORM_DRIVERS
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 3cdfc74..944b93b 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -350,6 +350,7 @@ CONFIG_MEDIA_SUPPORT=m
+ CONFIG_MEDIA_CAMERA_SUPPORT=y
+ CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+ CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_CEC_SUPPORT=y
+ CONFIG_MEDIA_CONTROLLER=y
+ CONFIG_MEDIA_RC_SUPPORT=y
+ CONFIG_RC_CORE=m
+@@ -364,6 +365,7 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
+ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+ CONFIG_VIDEO_RENESAS_FCP=m
+ CONFIG_VIDEO_RENESAS_VSP1=m
++CONFIG_CEC_PLATFORM_DRIVERS=y
+ CONFIG_DRM=m
+ CONFIG_DRM_NOUVEAU=m
+ CONFIG_DRM_EXYNOS=m
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0012-ARM64-defconfig-enable-CONFIG_VIDEO_MESON_AO_CEC.patch

@@ -0,0 +1,28 @@
+From c71be51a7778a6aa6b784dd0edc57951acf63ef2 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 13 Nov 2017 12:11:41 +0100
+Subject: [PATCH 12/39] ARM64: defconfig: enable CONFIG_VIDEO_MESON_AO_CEC
+
+Turn on CONFIG_VIDEO_MESON_AO_CEC as module
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 944b93b..fdf94cb 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -366,6 +366,7 @@ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+ CONFIG_VIDEO_RENESAS_FCP=m
+ CONFIG_VIDEO_RENESAS_VSP1=m
+ CONFIG_CEC_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MESON_AO_CEC=m
+ CONFIG_DRM=m
+ CONFIG_DRM_NOUVEAU=m
+ CONFIG_DRM_EXYNOS=m
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0013-ARM64-defconfig-enable-CONFIG_DRM_DW_HDMI_CEC.patch

@@ -0,0 +1,28 @@
+From 94fb1910e76e39cc910fb5b5a528712f4135891e Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 13 Nov 2017 12:15:18 +0100
+Subject: [PATCH 13/39] ARM64: defconfig: enable CONFIG_DRM_DW_HDMI_CEC
+
+Turn on CONFIG_DRM_DW_HDMI_CEC as module
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index fdf94cb..dcf1090 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -388,6 +388,7 @@ CONFIG_DRM_RCAR_VSP=y
+ CONFIG_DRM_TEGRA=m
+ CONFIG_DRM_PANEL_SIMPLE=m
+ CONFIG_DRM_I2C_ADV7511=m
++CONFIG_DRM_DW_HDMI_CEC=m
+ CONFIG_DRM_VC4=m
+ CONFIG_DRM_HISI_KIRIN=m
+ CONFIG_DRM_MESON=m
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0014-clk-meson-gxbb-Add-VPU-and-VAPB-clockids.patch

@@ -0,0 +1,55 @@
+From 9bc414d9e18f8c9d39be44165b4926e2b2cdc1d9 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Mon, 16 Oct 2017 17:29:33 +0200
+Subject: [PATCH 14/39] clk: meson: gxbb: Add VPU and VAPB clockids
+
+Add the clkids for the clocks feeding the Video Processing Unit.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/clk/meson/gxbb.h              |  6 +++++-
+ include/dt-bindings/clock/gxbb-clkc.h | 11 +++++++++++
+ 2 files changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
+index 5b1d4b3..aee6fbb 100644
+--- a/drivers/clk/meson/gxbb.h
++++ b/drivers/clk/meson/gxbb.h
+@@ -190,8 +190,12 @@
+ #define CLKID_SD_EMMC_B_CLK0_DIV  121
+ #define CLKID_SD_EMMC_C_CLK0_SEL  123
+ #define CLKID_SD_EMMC_C_CLK0_DIV  124
++#define CLKID_VPU_0_DIV		  127
++#define CLKID_VPU_1_DIV		  130
++#define CLKID_VAPB_0_DIV	  134
++#define CLKID_VAPB_1_DIV	  137
+ 
+-#define NR_CLKS			  126
++#define NR_CLKS			  141
+ 
+ /* include the CLKIDs that have been made part of the DT binding */
+ #include <dt-bindings/clock/gxbb-clkc.h>
+diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
+index 8c92528..8ba99a5 100644
+--- a/include/dt-bindings/clock/gxbb-clkc.h
++++ b/include/dt-bindings/clock/gxbb-clkc.h
+@@ -114,5 +114,16 @@
+ #define CLKID_SD_EMMC_A_CLK0	119
+ #define CLKID_SD_EMMC_B_CLK0	122
+ #define CLKID_SD_EMMC_C_CLK0	125
++#define CLKID_VPU_0_SEL		126
++#define CLKID_VPU_0		128
++#define CLKID_VPU_1_SEL		129
++#define CLKID_VPU_1		131
++#define CLKID_VPU		132
++#define CLKID_VAPB_0_SEL	133
++#define CLKID_VAPB_0		135
++#define CLKID_VAPB_1_SEL	136
++#define CLKID_VAPB_1		138
++#define CLKID_VAPB_SEL		139
++#define CLKID_VAPB		140
+ 
+ #endif /* __GXBB_CLKC_H */
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0015-clk-meson-gxbb-Add-VPU-and-VAPB-clocks-data.patch

@@ -0,0 +1,357 @@
+From a3b8b7bfd775fa521425c72856b4394fb6fec518 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Fri, 13 Oct 2017 14:38:37 +0200
+Subject: [PATCH 15/39] clk: meson: gxbb: Add VPU and VAPB clocks data
+
+The Amlogic Meson GX SoCs needs these two clocks to power up the
+VPU power domain.
+
+These two clocks are similar to the MALI clocks by having a glitch-free
+mux and two similar clocks with gate, divider and muxes.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/clk/meson/gxbb.c | 292 +++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 292 insertions(+)
+
+diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
+index 92168348..86cb5af 100644
+--- a/drivers/clk/meson/gxbb.c
++++ b/drivers/clk/meson/gxbb.c
+@@ -1131,6 +1131,253 @@ static struct clk_gate gxbb_sd_emmc_c_clk0 = {
+ 	},
+ };
+ 
++/* VPU Clock */
++
++static u32 mux_table_vpu[] = {0, 1, 2, 3};
++static const char * const gxbb_vpu_parent_names[] = {
++	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
++};
++
++static struct clk_mux gxbb_vpu_0_sel = {
++	.reg = (void *)HHI_VPU_CLK_CNTL,
++	.mask = 0x3,
++	.shift = 9,
++	.lock = &clk_lock,
++	.table = mux_table_vpu,
++	.hw.init = &(struct clk_init_data){
++		.name = "vpu_0_sel",
++		.ops = &clk_mux_ops,
++		/*
++		 * bits 9:10 selects from 4 possible parents:
++		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
++		 */
++		.parent_names = gxbb_vpu_parent_names,
++		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
++		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_divider gxbb_vpu_0_div = {
++	.reg = (void *)HHI_VPU_CLK_CNTL,
++	.shift = 0,
++	.width = 7,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data){
++		.name = "vpu_0_div",
++		.ops = &clk_divider_ops,
++		.parent_names = (const char *[]){ "vpu_0_sel" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_gate gxbb_vpu_0 = {
++	.reg = (void *)HHI_VPU_CLK_CNTL,
++	.bit_idx = 8,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data) {
++		.name = "vpu_0",
++		.ops = &clk_gate_ops,
++		.parent_names = (const char *[]){ "vpu_0_div" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_mux gxbb_vpu_1_sel = {
++	.reg = (void *)HHI_VPU_CLK_CNTL,
++	.mask = 0x3,
++	.shift = 25,
++	.lock = &clk_lock,
++	.table = mux_table_vpu,
++	.hw.init = &(struct clk_init_data){
++		.name = "vpu_1_sel",
++		.ops = &clk_mux_ops,
++		/*
++		 * bits 25:26 selects from 4 possible parents:
++		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
++		 */
++		.parent_names = gxbb_vpu_parent_names,
++		.num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
++		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_divider gxbb_vpu_1_div = {
++	.reg = (void *)HHI_VPU_CLK_CNTL,
++	.shift = 16,
++	.width = 7,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data){
++		.name = "vpu_1_div",
++		.ops = &clk_divider_ops,
++		.parent_names = (const char *[]){ "vpu_1_sel" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_gate gxbb_vpu_1 = {
++	.reg = (void *)HHI_VPU_CLK_CNTL,
++	.bit_idx = 24,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data) {
++		.name = "vpu_1",
++		.ops = &clk_gate_ops,
++		.parent_names = (const char *[]){ "vpu_1_div" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_mux gxbb_vpu = {
++	.reg = (void *)HHI_VPU_CLK_CNTL,
++	.mask = 1,
++	.shift = 31,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data){
++		.name = "vpu",
++		.ops = &clk_mux_ops,
++		/*
++		 * bit 31 selects from 2 possible parents:
++		 * vpu_0 or vpu_1
++		 */
++		.parent_names = (const char *[]){ "vpu_0", "vpu_1" },
++		.num_parents = 2,
++		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++/* VAPB Clock */
++
++static u32 mux_table_vapb[] = {0, 1, 2, 3};
++static const char * const gxbb_vapb_parent_names[] = {
++	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
++};
++
++static struct clk_mux gxbb_vapb_0_sel = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.mask = 0x3,
++	.shift = 9,
++	.lock = &clk_lock,
++	.table = mux_table_vapb,
++	.hw.init = &(struct clk_init_data){
++		.name = "vapb_0_sel",
++		.ops = &clk_mux_ops,
++		/*
++		 * bits 9:10 selects from 4 possible parents:
++		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
++		 */
++		.parent_names = gxbb_vapb_parent_names,
++		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
++		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_divider gxbb_vapb_0_div = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.shift = 0,
++	.width = 7,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data){
++		.name = "vapb_0_div",
++		.ops = &clk_divider_ops,
++		.parent_names = (const char *[]){ "vapb_0_sel" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_gate gxbb_vapb_0 = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.bit_idx = 8,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data) {
++		.name = "vapb_0",
++		.ops = &clk_gate_ops,
++		.parent_names = (const char *[]){ "vapb_0_div" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_mux gxbb_vapb_1_sel = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.mask = 0x3,
++	.shift = 25,
++	.lock = &clk_lock,
++	.table = mux_table_vapb,
++	.hw.init = &(struct clk_init_data){
++		.name = "vapb_1_sel",
++		.ops = &clk_mux_ops,
++		/*
++		 * bits 25:26 selects from 4 possible parents:
++		 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
++		 */
++		.parent_names = gxbb_vapb_parent_names,
++		.num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
++		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_divider gxbb_vapb_1_div = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.shift = 16,
++	.width = 7,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data){
++		.name = "vapb_1_div",
++		.ops = &clk_divider_ops,
++		.parent_names = (const char *[]){ "vapb_1_sel" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_gate gxbb_vapb_1 = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.bit_idx = 24,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data) {
++		.name = "vapb_1",
++		.ops = &clk_gate_ops,
++		.parent_names = (const char *[]){ "vapb_1_div" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_mux gxbb_vapb_sel = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.mask = 1,
++	.shift = 31,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data){
++		.name = "vapb_sel",
++		.ops = &clk_mux_ops,
++		/*
++		 * bit 31 selects from 2 possible parents:
++		 * vapb_0 or vapb_1
++		 */
++		.parent_names = (const char *[]){ "vapb_0", "vapb_1" },
++		.num_parents = 2,
++		.flags = CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
++static struct clk_gate gxbb_vapb = {
++	.reg = (void *)HHI_VAPBCLK_CNTL,
++	.bit_idx = 30,
++	.lock = &clk_lock,
++	.hw.init = &(struct clk_init_data) {
++		.name = "vapb",
++		.ops = &clk_gate_ops,
++		.parent_names = (const char *[]){ "vapb_sel" },
++		.num_parents = 1,
++		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
++	},
++};
++
+ /* Everything Else (EE) domain gates */
+ static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
+ static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
+@@ -1349,6 +1596,21 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
+ 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
+ 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
+ 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
++		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
++		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
++		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
++		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
++		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
++		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
++		[CLKID_VPU]		    = &gxbb_vpu.hw,
++		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
++		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
++		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
++		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
++		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
++		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
++		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
++		[CLKID_VAPB]		    = &gxbb_vapb.hw,
+ 		[NR_CLKS]		    = NULL,
+ 	},
+ 	.num = NR_CLKS,
+@@ -1481,6 +1743,21 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
+ 		[CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
+ 		[CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
+ 		[CLKID_SD_EMMC_C_CLK0]	    = &gxbb_sd_emmc_c_clk0.hw,
++		[CLKID_VPU_0_SEL]	    = &gxbb_vpu_0_sel.hw,
++		[CLKID_VPU_0_DIV]	    = &gxbb_vpu_0_div.hw,
++		[CLKID_VPU_0]		    = &gxbb_vpu_0.hw,
++		[CLKID_VPU_1_SEL]	    = &gxbb_vpu_1_sel.hw,
++		[CLKID_VPU_1_DIV]	    = &gxbb_vpu_1_div.hw,
++		[CLKID_VPU_1]		    = &gxbb_vpu_1.hw,
++		[CLKID_VPU]		    = &gxbb_vpu.hw,
++		[CLKID_VAPB_0_SEL]	    = &gxbb_vapb_0_sel.hw,
++		[CLKID_VAPB_0_DIV]	    = &gxbb_vapb_0_div.hw,
++		[CLKID_VAPB_0]		    = &gxbb_vapb_0.hw,
++		[CLKID_VAPB_1_SEL]	    = &gxbb_vapb_1_sel.hw,
++		[CLKID_VAPB_1_DIV]	    = &gxbb_vapb_1_div.hw,
++		[CLKID_VAPB_1]		    = &gxbb_vapb_1.hw,
++		[CLKID_VAPB_SEL]	    = &gxbb_vapb_sel.hw,
++		[CLKID_VAPB]		    = &gxbb_vapb.hw,
+ 		[NR_CLKS]		    = NULL,
+ 	},
+ 	.num = NR_CLKS,
+@@ -1600,6 +1877,11 @@ static struct clk_gate *const gxbb_clk_gates[] = {
+ 	&gxbb_sd_emmc_a_clk0,
+ 	&gxbb_sd_emmc_b_clk0,
+ 	&gxbb_sd_emmc_c_clk0,
++	&gxbb_vpu_0,
++	&gxbb_vpu_1,
++	&gxbb_vapb_0,
++	&gxbb_vapb_1,
++	&gxbb_vapb,
+ };
+ 
+ static struct clk_mux *const gxbb_clk_muxes[] = {
+@@ -1615,6 +1897,12 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
+ 	&gxbb_sd_emmc_a_clk0_sel,
+ 	&gxbb_sd_emmc_b_clk0_sel,
+ 	&gxbb_sd_emmc_c_clk0_sel,
++	&gxbb_vpu_0_sel,
++	&gxbb_vpu_1_sel,
++	&gxbb_vpu,
++	&gxbb_vapb_0_sel,
++	&gxbb_vapb_1_sel,
++	&gxbb_vapb_sel,
+ };
+ 
+ static struct clk_divider *const gxbb_clk_dividers[] = {
+@@ -1627,6 +1915,10 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
+ 	&gxbb_sd_emmc_a_clk0_div,
+ 	&gxbb_sd_emmc_b_clk0_div,
+ 	&gxbb_sd_emmc_c_clk0_div,
++	&gxbb_vpu_0_div,
++	&gxbb_vpu_1_div,
++	&gxbb_vapb_0_div,
++	&gxbb_vapb_1_div,
+ };
+ 
+ static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0016-drm-meson-dw_hdmi-Add-support-for-an-optional-extern.patch

@@ -0,0 +1,56 @@
+From fc742b3d9f1b79f9e3e695f0e4bfc6a35c7ed7e3 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Mon, 16 Oct 2017 15:35:00 +0200
+Subject: [PATCH 16/39] drm/meson: dw_hdmi: Add support for an optional
+ external 5V regulator
+
+On reference boards and derivatives, the HDMI Logic is powered by an external
+5V regulator.
+This regulator was set by the Vendor U-Boot, add optional support for it.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/gpu/drm/meson/meson_dw_hdmi.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+index cef4144..17de3af 100644
+--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+@@ -23,6 +23,7 @@
+ #include <linux/of_graph.h>
+ #include <linux/reset.h>
+ #include <linux/clk.h>
++#include <linux/regulator/consumer.h>
+ 
+ #include <drm/drmP.h>
+ #include <drm/drm_edid.h>
+@@ -137,6 +138,7 @@ struct meson_dw_hdmi {
+ 	struct reset_control *hdmitx_phy;
+ 	struct clk *hdmi_pclk;
+ 	struct clk *venci_clk;
++	struct regulator *hdmi_supply;
+ 	u32 irq_stat;
+ };
+ #define encoder_to_meson_dw_hdmi(x) \
+@@ -751,6 +753,17 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
+ 	dw_plat_data = &meson_dw_hdmi->dw_plat_data;
+ 	encoder = &meson_dw_hdmi->encoder;
+ 
++	meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi");
++	if (IS_ERR(meson_dw_hdmi->hdmi_supply)) {
++		if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++		meson_dw_hdmi->hdmi_supply = NULL;
++	} else {
++		ret = regulator_enable(meson_dw_hdmi->hdmi_supply);
++		if (ret)
++			return ret;
++	}
++
+ 	meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev,
+ 						"hdmitx_apb");
+ 	if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) {
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0017-drm-meson-Add-missing-VPU-init.patch

@@ -0,0 +1,58 @@
+From 253dbcb48f94e172873878262d19338bcc9aa108 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Mon, 16 Oct 2017 15:34:21 +0200
+Subject: [PATCH 17/39] drm/meson: Add missing VPU init
+
+The VPU init misses these configurations values.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/gpu/drm/meson/meson_drv.c       | 9 +++++++++
+ drivers/gpu/drm/meson/meson_registers.h | 4 ++++
+ 2 files changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
+index 7742c7d..19a0d8d 100644
+--- a/drivers/gpu/drm/meson/meson_drv.c
++++ b/drivers/gpu/drm/meson/meson_drv.c
+@@ -150,6 +150,14 @@ static struct regmap_config meson_regmap_config = {
+ 	.max_register   = 0x1000,
+ };
+ 
++static void meson_vpu_init(struct meson_drm *priv)
++{
++	writel_relaxed(0x210000, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
++	writel_relaxed(0x10000, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
++	writel_relaxed(0x900000, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
++	writel_relaxed(0x20000, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
++}
++
+ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ {
+ 	struct platform_device *pdev = to_platform_device(dev);
+@@ -221,6 +229,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
+ 
+ 	/* Hardware Initialization */
+ 
++	meson_vpu_init(priv);
+ 	meson_venc_init(priv);
+ 	meson_vpp_init(priv);
+ 	meson_viu_init(priv);
+diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
+index 2847381..bca8714 100644
+--- a/drivers/gpu/drm/meson/meson_registers.h
++++ b/drivers/gpu/drm/meson/meson_registers.h
+@@ -1363,6 +1363,10 @@
+ #define VPU_PROT3_STAT_1 0x277a
+ #define VPU_PROT3_STAT_2 0x277b
+ #define VPU_PROT3_REQ_ONOFF 0x277c
++#define VPU_RDARB_MODE_L1C1 0x2790
++#define VPU_RDARB_MODE_L1C2 0x2799
++#define VPU_RDARB_MODE_L2C1 0x279d
++#define VPU_WRARB_MODE_L2C1 0x27a2
+ 
+ /* osd super scale */
+ #define OSDSR_HV_SIZEIN 0x3130
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0018-reset-meson-add-level-reset-support-for-GX-SoC-famil.patch

@@ -0,0 +1,132 @@
+From 0689a4eaecae2831fe2cb614e102bb4ef43484a4 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Fri, 13 Oct 2017 14:05:01 +0200
+Subject: [PATCH 18/39] reset: meson: add level reset support for GX SoC family
+
+The Amlogic GX SoC family embeds alternate registers to drive the reset
+levels next to the pulse registers.
+
+This patch adds support for level reset handling on the GX family only.
+
+The Meson8 family has an alternate way to handle level reset.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/reset/reset-meson.c | 62 ++++++++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 58 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
+index a8b915e..f3b9d69 100644
+--- a/drivers/reset/reset-meson.c
++++ b/drivers/reset/reset-meson.c
+@@ -62,13 +62,16 @@
+ #include <linux/reset-controller.h>
+ #include <linux/slab.h>
+ #include <linux/types.h>
++#include <linux/of_device.h>
+ 
+ #define REG_COUNT	8
+ #define BITS_PER_REG	32
++#define LEVEL_OFFSET	0x7c
+ 
+ struct meson_reset {
+ 	void __iomem *reg_base;
+ 	struct reset_controller_dev rcdev;
++	spinlock_t lock;
+ };
+ 
+ static int meson_reset_reset(struct reset_controller_dev *rcdev,
+@@ -88,18 +91,63 @@ static int meson_reset_reset(struct reset_controller_dev *rcdev,
+ 	return 0;
+ }
+ 
+-static const struct reset_control_ops meson_reset_ops = {
++static int meson_reset_level(struct reset_controller_dev *rcdev,
++			    unsigned long id, bool assert)
++{
++	struct meson_reset *data =
++		container_of(rcdev, struct meson_reset, rcdev);
++	unsigned int bank = id / BITS_PER_REG;
++	unsigned int offset = id % BITS_PER_REG;
++	void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
++	unsigned long flags;
++	u32 reg;
++
++	spin_lock_irqsave(&data->lock, flags);
++
++	reg = readl(reg_addr);
++	if (assert)
++		writel(reg & ~BIT(offset), reg_addr);
++	else
++		writel(reg | BIT(offset), reg_addr);
++
++	spin_unlock_irqrestore(&data->lock, flags);
++
++	return 0;
++}
++
++static int meson_reset_assert(struct reset_controller_dev *rcdev,
++			      unsigned long id)
++{
++	return meson_reset_level(rcdev, id, true);
++}
++
++static int meson_reset_deassert(struct reset_controller_dev *rcdev,
++				unsigned long id)
++{
++	return meson_reset_level(rcdev, id, false);
++}
++
++static const struct reset_control_ops meson_reset_meson8_ops = {
+ 	.reset		= meson_reset_reset,
+ };
+ 
++static const struct reset_control_ops meson_reset_gx_ops = {
++	.reset		= meson_reset_reset,
++	.assert		= meson_reset_assert,
++	.deassert	= meson_reset_deassert,
++};
++
+ static const struct of_device_id meson_reset_dt_ids[] = {
+-	 { .compatible = "amlogic,meson8b-reset", },
+-	 { .compatible = "amlogic,meson-gxbb-reset", },
++	 { .compatible = "amlogic,meson8b-reset",
++	   .data = &meson_reset_meson8_ops, },
++	 { .compatible = "amlogic,meson-gxbb-reset",
++	   .data = &meson_reset_gx_ops, },
+ 	 { /* sentinel */ },
+ };
+ 
+ static int meson_reset_probe(struct platform_device *pdev)
+ {
++	const struct reset_control_ops *ops;
+ 	struct meson_reset *data;
+ 	struct resource *res;
+ 
+@@ -107,6 +155,10 @@ static int meson_reset_probe(struct platform_device *pdev)
+ 	if (!data)
+ 		return -ENOMEM;
+ 
++	ops = of_device_get_match_data(&pdev->dev);
++	if (!ops)
++		return -EINVAL;
++
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	data->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ 	if (IS_ERR(data->reg_base))
+@@ -114,9 +166,11 @@ static int meson_reset_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, data);
+ 
++	spin_lock_init(&data->lock);
++
+ 	data->rcdev.owner = THIS_MODULE;
+ 	data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
+-	data->rcdev.ops = &meson_reset_ops;
++	data->rcdev.ops = ops;
+ 	data->rcdev.of_node = pdev->dev.of_node;
+ 
+ 	return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/odroid-c2/patches/linux/0019-soc-amlogic-add-Meson-GX-VPU-Domains-driver.patch

@@ -0,0 +1,286 @@
+From 58d5e73046ca5c28eb835c1a98f936193de5d4d0 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Fri, 13 Oct 2017 17:05:00 +0200
+Subject: [PATCH 19/39] soc: amlogic: add Meson GX VPU Domains driver
+
+The Video Processing Unit needs a specific Power Domain powering scheme
+this driver handles this as a PM Power Domain driver.
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ drivers/soc/amlogic/Kconfig             |  10 ++
+ drivers/soc/amlogic/Makefile            |   1 +
+ drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 234 ++++++++++++++++++++++++++++++++
+ 3 files changed, 245 insertions(+)
+ create mode 100644 drivers/soc/amlogic/meson-gx-pwrc-vpu.c
+
+diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
+index 22acf06..c2c0513 100644
+--- a/drivers/soc/amlogic/Kconfig
++++ b/drivers/soc/amlogic/Kconfig
+@@ -8,5 +8,15 @@ config MESON_GX_SOCINFO
+ 	help
+ 	  Say yes to support decoding of Amlogic Meson GX SoC family
+ 	  information about the type, package and version.
++ 
++config MESON_GX_PM_DOMAINS
++	bool "Amlogic Meson GX Power Domains driver"
++	depends on ARCH_MESON || COMPILE_TEST
++	default ARCH_MESON
++	select PM_GENERIC_DOMAINS
++	select PM_GENERIC_DOMAINS_OF
++	help
++	  Say yes to expose Amlogic Meson GX Power Domains as
++	  Generic Power Domains.
+ 
+ endmenu
+diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
+index 3e85fc4..3174e93 100644
+--- a/drivers/soc/amlogic/Makefile
++++ b/drivers/soc/amlogic/Makefile
+@@ -1 +1,2 @@
+ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
++obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
+diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
+new file mode 100644
+index 0000000..bf5190b
+--- /dev/null
++++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c
+@@ -0,0 +1,234 @@
++/*
++ * Copyright (c) 2017 BayLibre, SAS
++ * Author: Neil Armstrong <narmstrong@baylibre.com>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <linux/of_address.h>
++#include <linux/platform_device.h>
++#include <linux/pm_domain.h>
++#include <linux/bitfield.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/reset.h>
++#include <linux/clk.h>
++
++/* AO Offsets */
++
++#define AO_RTI_GEN_PWR_SLEEP0		(0x3a << 2)
++
++#define GEN_PWR_VPU_HDMI		BIT(8)
++#define GEN_PWR_VPU_HDMI_ISO		BIT(9)
++
++/* HHI Offsets */
++
++#define HHI_MEM_PD_REG0			(0x40 << 2)
++#define HHI_VPU_MEM_PD_REG0		(0x41 << 2)
++#define HHI_VPU_MEM_PD_REG1		(0x42 << 2)
++
++struct meson_gx_pwrc_vpu {
++	struct generic_pm_domain genpd;
++	struct regmap *regmap_ao;
++	struct regmap *regmap_hhi;
++	struct reset_control *rstc;
++	struct clk *vpu_clk;
++	struct clk *vapb_clk;
++	bool powered;
++};
++
++static inline
++struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
++{
++	return container_of(d, struct meson_gx_pwrc_vpu, genpd);
++}
++
++static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
++{
++	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
++	int i;
++
++	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
++			   GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
++	udelay(20);
++
++	/* Power Down Memories */
++	for (i = 0; i < 32; i += 2) {
++		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
++				   0x2 << i, 0x3 << i);
++		udelay(5);
++	}
++	for (i = 0; i < 32; i += 2) {
++		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
++				   0x2 << i, 0x3 << i);
++		udelay(5);
++	}
++	for (i = 8; i < 16; i++) {
++		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
++				   BIT(i), BIT(i));
++		udelay(5);
++	}
++	udelay(20);
++
++	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
++			   GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
++
++	msleep(20);
++
++	clk_disable_unprepare(pd->vpu_clk);
++	clk_disable_unprepare(pd->vapb_clk);
++
++	pd->powered = false;
++
++	return 0;
++}
++
++static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
++{
++	int ret;
++
++	ret = clk_prepare_enable(pd->vpu_clk);
++	if (ret)
++		return ret;
++
++	return clk_prepare_enable(pd->vapb_clk);
++}
++
++static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
++{
++	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
++	int ret;
++	int i;
++
++	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
++			   GEN_PWR_VPU_HDMI, 0);
++	udelay(20);
++
++	/* Power Up Memories */
++	for (i = 0; i < 32; i += 2) {
++		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
++				   0x2 << i, 0);
++		udelay(5);
++	}
++
++	for (i = 0; i < 32; i += 2) {
++		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
++				   0x2 << i, 0);
++		udelay(5);
++	}
++
++	for (i = 8; i < 16; i++) {
++		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
++				   BIT(i), 0);
++		udelay(5);
++	}
++	udelay(20);
++
++	ret = reset_control_assert(pd->rstc);
++	if (ret)
++		return ret;
++
++	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
++			   GEN_PWR_VPU_HDMI_ISO, 0);
++
++	ret = reset_control_deassert(pd->rstc);
++	if (ret)
++		return ret;
++
++	ret = meson_gx_pwrc_vpu_setup_clk(pd);
++	if (ret)
++		return ret;
++
++	pd->powered = true;
++
++	return 0;
++}
++
++static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
++{
++	u32 reg;
++
++	regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, &reg);
++
++	return (reg & GEN_PWR_VPU_HDMI);
++}
++
++static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
++	.genpd = {
++		.name = "vpu_hdmi",
++		.power_off = meson_gx_pwrc_vpu_power_off,
++		.power_on = meson_gx_pwrc_vpu_power_on,
++	},
++};
++
++static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
++{
++	struct regmap *regmap_ao, *regmap_hhi;
++	struct reset_control *rstc;
++	struct clk *vpu_clk;
++	struct clk *vapb_clk;
++
++	regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
++	if (IS_ERR(regmap_ao)) {
++		dev_err(&pdev->dev, "failed to get regmap\n");
++		return PTR_ERR(regmap_ao);
++	}
++
++	regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++						     "amlogic,hhi-sysctrl");
++	if (IS_ERR(regmap_hhi)) {
++		dev_err(&pdev->dev, "failed to get HHI regmap\n");
++		return PTR_ERR(regmap_hhi);
++	}
++
++	rstc = devm_reset_control_array_get(&pdev->dev, false, false);
++	if (IS_ERR(rstc)) {
++		dev_err(&pdev->dev, "failed to get reset lines\n");
++		return PTR_ERR(rstc);
++	}
++
++	vpu_clk = devm_clk_get(&pdev->dev, "vpu");
++	if (IS_ERR(vpu_clk)) {
++		dev_err(&pdev->dev, "vpu clock request failed\n");
++		return PTR_ERR(vpu_clk);
++	}
++
++	vapb_clk = devm_clk_get(&pdev->dev, "vapb");
++	if (IS_ERR(vapb_clk)) {
++		dev_err(&pdev->dev, "vapb clock request failed\n");
++		return PTR_ERR(vapb_clk);
++	}
++
++	vpu_hdmi_pd.regmap_ao = regmap_ao;
++	vpu_hdmi_pd.regmap_hhi = regmap_hhi;
++	vpu_hdmi_pd.rstc = rstc;
++	vpu_hdmi_pd.vpu_clk = vpu_clk;
++	vpu_hdmi_pd.vapb_clk = vapb_clk;
++
++	pm_genpd_init(&vpu_hdmi_pd.genpd, &simple_qos_governor,
++		      meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd));
++
++	return of_genpd_add_provider_simple(pdev->dev.of_node,
++					    &vpu_hdmi_pd.genpd);
++}
++
++static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
++{
++	if (vpu_hdmi_pd.powered)
++		meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
++}
++
++static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
++	{ .compatible = "amlogic,meson-gx-pwrc-vpu" },
++	{ /* sentinel */ }
++};
++
++static struct platform_driver meson_gx_pwrc_vpu_driver = {
++	.probe	= meson_gx_pwrc_vpu_probe,
++	.shutdown = meson_gx_pwrc_vpu_shutdown,
++	.driver = {
++		.name		= "meson_gx_pwrc_vpu",
++		.of_match_table	= meson_gx_pwrc_vpu_match_table,
++	},
++};
++builtin_platform_driver(meson_gx_pwrc_vpu_driver);
+-- 
+2.7.4
+