diff --git a/buildroot-external/board/hardkernel/odroid-xu4/patches/linux/000-arm-exynos_change_the_default_dma_coherent_pool_size.patch b/buildroot-external/board/hardkernel/odroid-xu4/patches/linux/000-arm-exynos_change_the_default_dma_coherent_pool_size.patch
new file mode 100644
index 000000000..26642d590
--- /dev/null
+++ b/buildroot-external/board/hardkernel/odroid-xu4/patches/linux/000-arm-exynos_change_the_default_dma_coherent_pool_size.patch
@@ -0,0 +1,42 @@
+diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
+index bf02dbd9ccda3..8029e21eee149 100644
+--- a/arch/arm/include/asm/dma-mapping.h
++++ b/arch/arm/include/asm/dma-mapping.h
+@@ -5,7 +5,9 @@
+ 
+ #include <linux/mm_types.h>
+ #include <linux/scatterlist.h>
++#include <linux/device.h>
+ #include <linux/dma-debug.h>
++#include <linux/dma-direction.h>
+ 
+ #include <asm/memory.h>
+ 
+diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
+index fd6da5419b510..5b3abc935e7fc 100644
+--- a/arch/arm/mach-exynos/firmware.c
++++ b/arch/arm/mach-exynos/firmware.c
+@@ -13,12 +13,14 @@
+ #include <linux/init.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
++#include <linux/sizes.h>
+ 
+ #include <asm/cacheflush.h>
+ #include <asm/cputype.h>
+ #include <asm/firmware.h>
+ #include <asm/hardware/cache-l2x0.h>
+ #include <asm/suspend.h>
++#include <asm/dma-mapping.h>
+ 
+ #include "common.h"
+ #include "smc.h"
+@@ -225,6 +227,8 @@ void __init exynos_firmware_init(void)
+ 		outer_cache.write_sec = exynos_l2_write_sec;
+ 		outer_cache.configure = exynos_l2_configure;
+ 	}
++
++	init_dma_coherent_pool_size(SZ_1M);
+ }
+ 
+ #define REG_CPU_STATE_ADDR	(sysram_ns_base_addr + 0x28)