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Cap eMMC frequency to 24MHz in U-Boot for ODROID-N2(+) (#1072)

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* Revert "Fix boot from 128GB Micron eMMC on ODROID-N2(+) (#1064)"

This reverts commit 162084082e92384d40c1789457eb574f8790ea87.

This patches seem to cause issue on a ODROID-N2 with 32GB eMMC.

* Cap eMMC frequency to 24MHz in U-Boot for ODROID-N2(+)

Also remove the ODROID-C4 specific patch.
This commit is contained in:
Stefan Agner 2020-12-10 00:45:05 +01:00 committed by GitHub
parent 1a8f9ca2e3
commit e42835f163
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 16 additions and 188 deletions
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4
buildroot-external/board/hardkernel/patches/uboot/0001-ARM-meson-isolate-loading-of-socinfo.patch
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@ -1,8 +1,8 @@
From 526ccae8321b9b48925c44999611c3c5a374328e Mon Sep 17 00:00:00 2001
Message-Id: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
Message-Id: <526ccae8321b9b48925c44999611c3c5a374328e.1607542946.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Mon, 31 Aug 2020 13:40:18 +0200
Subject: [PATCH 1/4] ARM: meson: isolate loading of socinfo
Subject: [PATCH 1/3] ARM: meson: isolate loading of socinfo
Move loading of socinfo into a separate function so the value can be
reused later.

8
buildroot-external/board/hardkernel/patches/uboot/0002-meson-Add-board_rev-to-env.patch
View File

@ -1,10 +1,10 @@
From 2b2ad8c105cbb5fb48c3c5f0512c031f6533d522 Mon Sep 17 00:00:00 2001
Message-Id: <2b2ad8c105cbb5fb48c3c5f0512c031f6533d522.1607361661.git.stefan@agner.ch>
In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
Message-Id: <2b2ad8c105cbb5fb48c3c5f0512c031f6533d522.1607542946.git.stefan@agner.ch>
In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607542946.git.stefan@agner.ch>
References: <526ccae8321b9b48925c44999611c3c5a374328e.1607542946.git.stefan@agner.ch>
From: Pascal Vizeli <pvizeli@syshack.ch>
Date: Tue, 4 Aug 2020 13:50:57 +0000
Subject: [PATCH 2/4] meson: Add board_rev to env
Subject: [PATCH 2/3] meson: Add board_rev to env
Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
Signed-off-by: Stefan Agner <stefan@agner.ch>

14
buildroot-external/board/hardkernel/odroid-c4/patches/uboot/0001-HACK-mmc-meson-gx-limit-to-24MHz.patch → buildroot-external/board/hardkernel/patches/uboot/0003-HACK-mmc-meson-gx-limit-to-24MHz.patch
View File

@ -1,4 +1,7 @@
From 64017a2cc9e501329016d50b701c5e9a9488991d Mon Sep 17 00:00:00 2001
From 0077176ac369a1125c3fb22f7ba8e5d53576a1b3 Mon Sep 17 00:00:00 2001
Message-Id: <0077176ac369a1125c3fb22f7ba8e5d53576a1b3.1607542946.git.stefan@agner.ch>
In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607542946.git.stefan@agner.ch>
References: <526ccae8321b9b48925c44999611c3c5a374328e.1607542946.git.stefan@agner.ch>
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Mon, 2 Sep 2019 15:42:04 +0200
Subject: [PATCH 3/3] HACK: mmc: meson-gx: limit to 24MHz
@ -9,10 +12,10 @@ Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index b5f5122b..00bfa324 100644
index 719dd1e5e5..dd3dd7c08c 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -252,7 +252,7 @@ static int meson_mmc_probe(struct udevice *dev)
@@ -265,7 +265,7 @@ static int meson_mmc_probe(struct udevice *dev)
cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
@ -20,6 +23,7 @@ index b5f5122b..00bfa324 100644
+ cfg->f_max = SD_EMMC_CLKSRC_24M;
cfg->b_max = 511; /* max 512 - 1 blocks */
cfg->name = dev->name;
--
2.29.2
--
2.22.0

103
buildroot-external/board/hardkernel/patches/uboot/0003-mmc-meson-gx-change-clock-phase-value-on-SM1-SoCs.patch
View File

@ -1,103 +0,0 @@
From 77241850a471015eb18e1b3cb124fce71c7b59c8 Mon Sep 17 00:00:00 2001
Message-Id: <77241850a471015eb18e1b3cb124fce71c7b59c8.1607361661.git.stefan@agner.ch>
In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Wed, 11 Nov 2020 08:22:10 +0900
Subject: [PATCH 3/4] mmc: meson-gx: change clock phase value on SM1 SoCs
Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's
working fine over 50MHz on Amlogic SM1 SoCs.
Since Other Amlogic SoCs doens't report an issue, phase value is using
to 180' by default.
To distinguish which value is used adds an u-boot only sm1 compatible.
In future, it needs to find what value is a proper about each SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 5 +++++
drivers/mmc/meson_gx_mmc.c | 27 +++++++++++++++++++----
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index 1e9f8cf498..cb16f75fc6 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -12,6 +12,11 @@
#endif
+enum meson_gx_mmc_compatible {
+ MMC_COMPATIBLE_GX,
+ MMC_COMPATIBLE_SM1,
+};
+
#define SDIO_PORT_A 0
#define SDIO_PORT_B 1
#define SDIO_PORT_C 2
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 719dd1e5e5..5facbfdd9a 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -17,6 +17,14 @@
#include <linux/delay.h>
#include <linux/log2.h>
+bool meson_gx_mmc_is_compatible(struct udevice *dev,
+ enum meson_gx_mmc_compatible family)
+{
+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
+
+ return compat == family;
+}
+
static inline void *get_regbase(const struct mmc *mmc)
{
struct meson_mmc_platdata *pdata = mmc->priv;
@@ -42,6 +50,8 @@ static void meson_mmc_config_clock(struct mmc *mmc)
if (!mmc->clock)
return;
+ /* TOFIX This should use the proper clock taken from DT */
+
/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
if (mmc->clock > 16000000) {
clk = SD_EMMC_CLKSRC_DIV2;
@@ -52,8 +62,16 @@ static void meson_mmc_config_clock(struct mmc *mmc)
}
clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /* 180 phase core clock */
- meson_mmc_clk |= CLK_CO_PHASE_180;
+ /*
+ * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
+ * If CLK_CO_PHASE_270 is used, it's more stable than other.
+ * Other SoCs use CLK_CO_PHASE_180 by default.
+ * It needs to find what is a proper value about each SoCs.
+ */
+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
+ meson_mmc_clk |= CLK_CO_PHASE_270;
+ else
+ meson_mmc_clk |= CLK_CO_PHASE_180;
/* 180 phase tx clock */
meson_mmc_clk |= CLK_TX_PHASE_000;
@@ -308,8 +326,9 @@ int meson_mmc_bind(struct udevice *dev)
}
static const struct udevice_id meson_mmc_match[] = {
- { .compatible = "amlogic,meson-gx-mmc" },
- { .compatible = "amlogic,meson-axg-mmc" },
+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
{ /* sentinel */ }
};
--
2.29.2

73
buildroot-external/board/hardkernel/patches/uboot/0004-mmc-meson-gx-change-clock-phase-value-on-AGX-SoCs.patch
View File

@ -1,73 +0,0 @@
From 179546705437886904fd8215bf2e6fbe7d731fb9 Mon Sep 17 00:00:00 2001
Message-Id: <179546705437886904fd8215bf2e6fbe7d731fb9.1607361661.git.stefan@agner.ch>
In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
From: Stefan Agner <stefan@agner.ch>
Date: Mon, 7 Dec 2020 17:55:28 +0100
Subject: [PATCH 4/4] mmc: meson-gx: change clock phase value on AGX SoCs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Amlogic AGX SoCs seem to have issue communicating with some eMMC
devices (in particular with a Micron 128GB eMMC 5.1). The device
is detected with 1-bit bus width, and at higher temperature loading
pretty much anything from the storage fails: (e.g. fs_devread read error
- block).
When phase is set to 270° it is detected with 8-bit bus width and is
working fine accross all temperatures.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 1 +
drivers/mmc/meson_gx_mmc.c | 9 +++++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
index cb16f75fc6..db5e058098 100644
--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -14,6 +14,7 @@
enum meson_gx_mmc_compatible {
MMC_COMPATIBLE_GX,
+ MMC_COMPATIBLE_AGX,
MMC_COMPATIBLE_SM1,
};
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 5facbfdd9a..2c27113c10 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -64,14 +64,15 @@ static void meson_mmc_config_clock(struct mmc *mmc)
/*
* SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
+ * AGX SoCs don't work reliable with some eMMCs with CLK_CO_PHASE_180
* If CLK_CO_PHASE_270 is used, it's more stable than other.
* Other SoCs use CLK_CO_PHASE_180 by default.
* It needs to find what is a proper value about each SoCs.
*/
- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
- meson_mmc_clk |= CLK_CO_PHASE_270;
- else
+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_GX))
meson_mmc_clk |= CLK_CO_PHASE_180;
+ else
+ meson_mmc_clk |= CLK_CO_PHASE_270;
/* 180 phase tx clock */
meson_mmc_clk |= CLK_TX_PHASE_000;
@@ -327,7 +328,7 @@ int meson_mmc_bind(struct udevice *dev)
static const struct udevice_id meson_mmc_match[] = {
{ .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AGX },
{ .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
{ /* sentinel */ }
};
--
2.29.2

2
buildroot-external/configs/odroid_c4_defconfig
View File

@ -2,7 +2,7 @@ BR2_aarch64=y
BR2_DL_DIR="/cache/dl"
BR2_CCACHE=y
BR2_CCACHE_DIR="/cache/cc"
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_HASSOS_PATH)/patches $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/patches $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/odroid-c4/patches"
BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_HASSOS_PATH)/patches $(BR2_EXTERNAL_HASSOS_PATH)/board/hardkernel/patches"
BR2_TOOLCHAIN_BUILDROOT_GLIBC=y
BR2_GCC_VERSION_9_X=y
BR2_OPTIMIZE_2=y