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https://github.com/home-assistant/operating-system.git
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Cap eMMC frequency to 24MHz in U-Boot for ODROID-N2(+) (#1068)
* Revert "Fix boot from 128GB Micron eMMC on ODROID-N2(+) (#1064)" This reverts commit b4f2208363a73a4ccfe2006c1ecc4db9b966fc82. * Cap eMMC frequency to 24MHz in U-Boot for ODROID-N2(+) as well
This commit is contained in:
Stefan Agner
GitHub
parent
a619faf6c6
commit
e6843b2fce
@ -0,0 +1,29 @@
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From 88650de0cd71c3d75fda780fad2827432516d780 Mon Sep 17 00:00:00 2001
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Message-Id: <88650de0cd71c3d75fda780fad2827432516d780.1607441248.git.stefan@agner.ch>
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In-Reply-To: <c12338d22649e46aed12ebe60d897112f045fda9.1607441248.git.stefan@agner.ch>
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References: <c12338d22649e46aed12ebe60d897112f045fda9.1607441248.git.stefan@agner.ch>
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Mon, 2 Sep 2019 15:42:04 +0200
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Subject: [PATCH 4/4] HACK: mmc: meson-gx: limit to 24MHz
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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---
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drivers/mmc/meson_gx_mmc.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
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index b5f5122b1b..00bfa3249e 100644
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--- a/drivers/mmc/meson_gx_mmc.c
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+++ b/drivers/mmc/meson_gx_mmc.c
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@@ -252,7 +252,7 @@ static int meson_mmc_probe(struct udevice *dev)
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cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
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MMC_MODE_HS_52MHz | MMC_MODE_HS;
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cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
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- cfg->f_max = 100000000; /* 100 MHz */
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+ cfg->f_max = SD_EMMC_CLKSRC_24M;
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cfg->b_max = 511; /* max 512 - 1 blocks */
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cfg->name = dev->name;
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--
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2.29.2
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@ -1,103 +0,0 @@
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From 68d89f37f4793b8d59525725cb882130cbd42433 Mon Sep 17 00:00:00 2001
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Message-Id: <68d89f37f4793b8d59525725cb882130cbd42433.1607375763.git.stefan@agner.ch>
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In-Reply-To: <c12338d22649e46aed12ebe60d897112f045fda9.1607375763.git.stefan@agner.ch>
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References: <c12338d22649e46aed12ebe60d897112f045fda9.1607375763.git.stefan@agner.ch>
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Wed, 11 Nov 2020 08:22:10 +0900
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Subject: [PATCH 4/5] mmc: meson-gx: change clock phase value on SM1 SoCs
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Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's
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working fine over 50MHz on Amlogic SM1 SoCs.
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Since Other Amlogic SoCs doens't report an issue, phase value is using
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to 180' by default.
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To distinguish which value is used adds an u-boot only sm1 compatible.
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In future, it needs to find what value is a proper about each SoCs.
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
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Tested-by: Anand Moon <linux.amoon@gmail.com>
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---
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arch/arm/include/asm/arch-meson/sd_emmc.h | 5 +++++
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drivers/mmc/meson_gx_mmc.c | 27 +++++++++++++++++++----
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2 files changed, 28 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
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index e3a72c8b66..a9dbb0884b 100644
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--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
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+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
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@@ -8,6 +8,11 @@
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#include <mmc.h>
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+enum meson_gx_mmc_compatible {
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+ MMC_COMPATIBLE_GX,
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+ MMC_COMPATIBLE_SM1,
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+};
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+
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#define SDIO_PORT_A 0
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#define SDIO_PORT_B 1
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#define SDIO_PORT_C 2
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diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
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index b5f5122b1b..b5d22dca1e 100644
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--- a/drivers/mmc/meson_gx_mmc.c
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+++ b/drivers/mmc/meson_gx_mmc.c
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@@ -15,6 +15,14 @@
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#include <asm/arch/sd_emmc.h>
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#include <linux/log2.h>
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+bool meson_gx_mmc_is_compatible(struct udevice *dev,
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+ enum meson_gx_mmc_compatible family)
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+{
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+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
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+
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+ return compat == family;
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+}
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+
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static inline void *get_regbase(const struct mmc *mmc)
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{
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struct meson_mmc_platdata *pdata = mmc->priv;
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@@ -40,6 +48,8 @@ static void meson_mmc_config_clock(struct mmc *mmc)
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if (!mmc->clock)
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return;
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+ /* TOFIX This should use the proper clock taken from DT */
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+
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/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
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if (mmc->clock > 16000000) {
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clk = SD_EMMC_CLKSRC_DIV2;
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@@ -50,8 +60,16 @@ static void meson_mmc_config_clock(struct mmc *mmc)
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}
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clk_div = DIV_ROUND_UP(clk, mmc->clock);
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- /* 180 phase core clock */
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- meson_mmc_clk |= CLK_CO_PHASE_180;
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+ /*
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+ * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
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+ * If CLK_CO_PHASE_270 is used, it's more stable than other.
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+ * Other SoCs use CLK_CO_PHASE_180 by default.
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+ * It needs to find what is a proper value about each SoCs.
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+ */
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+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
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+ meson_mmc_clk |= CLK_CO_PHASE_270;
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+ else
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+ meson_mmc_clk |= CLK_CO_PHASE_180;
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/* 180 phase tx clock */
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meson_mmc_clk |= CLK_TX_PHASE_000;
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@@ -295,8 +313,9 @@ int meson_mmc_bind(struct udevice *dev)
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}
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static const struct udevice_id meson_mmc_match[] = {
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- { .compatible = "amlogic,meson-gx-mmc" },
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- { .compatible = "amlogic,meson-axg-mmc" },
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+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
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+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
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+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
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{ /* sentinel */ }
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};
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--
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2.29.2
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@ -1,73 +0,0 @@
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From c91d9f6f8137d82d5afe02a33954b322e310d902 Mon Sep 17 00:00:00 2001
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Message-Id: <c91d9f6f8137d82d5afe02a33954b322e310d902.1607375763.git.stefan@agner.ch>
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In-Reply-To: <c12338d22649e46aed12ebe60d897112f045fda9.1607375763.git.stefan@agner.ch>
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References: <c12338d22649e46aed12ebe60d897112f045fda9.1607375763.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Mon, 7 Dec 2020 17:55:28 +0100
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Subject: [PATCH 5/5] mmc: meson-gx: change clock phase value on AGX SoCs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Amlogic AGX SoCs seem to have issue communicating with some eMMC
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devices (in particular with a Micron 128GB eMMC 5.1). The device
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is detected with 1-bit bus width, and at higher temperature loading
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pretty much anything from the storage fails: (e.g. fs_devread read error
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- block).
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When phase is set to 270° it is detected with 8-bit bus width and is
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working fine accross all temperatures.
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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---
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arch/arm/include/asm/arch-meson/sd_emmc.h | 1 +
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drivers/mmc/meson_gx_mmc.c | 9 +++++----
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2 files changed, 6 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
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index a9dbb0884b..f706761b46 100644
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--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
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+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
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@@ -10,6 +10,7 @@
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enum meson_gx_mmc_compatible {
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MMC_COMPATIBLE_GX,
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+ MMC_COMPATIBLE_AGX,
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MMC_COMPATIBLE_SM1,
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};
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diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
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index b5d22dca1e..e2f9583014 100644
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--- a/drivers/mmc/meson_gx_mmc.c
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+++ b/drivers/mmc/meson_gx_mmc.c
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@@ -62,14 +62,15 @@ static void meson_mmc_config_clock(struct mmc *mmc)
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/*
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* SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
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+ * AGX SoCs don't work reliable with some eMMCs with CLK_CO_PHASE_180
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* If CLK_CO_PHASE_270 is used, it's more stable than other.
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* Other SoCs use CLK_CO_PHASE_180 by default.
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* It needs to find what is a proper value about each SoCs.
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*/
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- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
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- meson_mmc_clk |= CLK_CO_PHASE_270;
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- else
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+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_GX))
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meson_mmc_clk |= CLK_CO_PHASE_180;
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+ else
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+ meson_mmc_clk |= CLK_CO_PHASE_270;
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/* 180 phase tx clock */
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meson_mmc_clk |= CLK_TX_PHASE_000;
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@@ -314,7 +315,7 @@ int meson_mmc_bind(struct udevice *dev)
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static const struct udevice_id meson_mmc_match[] = {
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{ .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
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- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
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+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AGX },
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{ .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
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{ /* sentinel */ }
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};
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--
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2.29.2
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