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Fix patches

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This commit is contained in:
Pascal Vizeli 2018-05-19 17:45:35 +02:00
parent 7882d2a63f
commit e6c9a97ce8
3 changed files with 41 additions and 159 deletions
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5
buildroot-external/board/rpi3/barebox.config
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@ -14,6 +14,7 @@ CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y CONFIG_MENU=y
# CONFIG_TIMESTAMP is not set # CONFIG_TIMESTAMP is not set
CONFIG_BOOTM_SHOW_TYPE=y CONFIG_BOOTM_SHOW_TYPE=y
CONFIG_BOOTM_OFTREE=y
CONFIG_FLEXIBLE_BOOTARGS=y CONFIG_FLEXIBLE_BOOTARGS=y
# CONFIG_PARTITION_DISK_DOS is not set # CONFIG_PARTITION_DISK_DOS is not set
CONFIG_PARTITION_DISK_EFI=y CONFIG_PARTITION_DISK_EFI=y
@ -38,9 +39,13 @@ CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_DETECT=y CONFIG_CMD_DETECT=y
CONFIG_CMD_STATE=y CONFIG_CMD_STATE=y
CONFIG_CMD_BOOTCHOOSER=y CONFIG_CMD_BOOTCHOOSER=y
CONFIG_MCI=y
CONFIG_MCI_BCM283X=y
# CONFIG_SPI is not set # CONFIG_SPI is not set
CONFIG_DISK=y CONFIG_DISK=y
CONFIG_DISK_WRITE=y CONFIG_DISK_WRITE=y
# CONFIG_PINCTRL is not set
CONFIG_REGULATOR=y
CONFIG_FS_FAT=y CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y CONFIG_FS_FAT_LFN=y

162
buildroot-external/board/rpi3/patches/barebox/0004-add-file-for-HYP-mode-related-setup.patch
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@ -1,153 +1,34 @@
This adds routines to add hyp mode vectors and switch back to HYP From 9afaacdda672452b52a95b9bcea259646c3b5850 Mon Sep 17 00:00:00 2001
mode from SVC. This is needed in both the PBL and Barebox proper. From: Pascal Vizeli <pvizeli@syshack.ch>
Date: Sat, 19 May 2018 17:35:26 +0200
Subject: [PATCH 1/1] p2
Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
--- ---
arch/arm/cpu/Makefile | 4 ++ arch/arm/cpu/Makefile | 7 +++++++
arch/arm/cpu/hyp.S | 115 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/sm_as.S | 11 -----------
arch/arm/cpu/sm_as.S | 11 ---- arch/arm/include/asm/secure.h | 2 ++
arch/arm/include/asm/secure.h | 2 + 3 files changed, 9 insertions(+), 11 deletions(-)
4 files changed, 121 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/cpu/hyp.S
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 13fe12c31f6f..537fe5b9bb8d 100644 index 0316d25..6d67b42 100644
--- a/arch/arm/cpu/Makefile --- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile
@@ -9,6 +9,10 @@ obj-$(CONFIG_ARM_EXCEPTIONS) += exceptions.o @@ -9,6 +9,13 @@ obj-y += start.o entry.o
obj-$(CONFIG_MMU) += mmu.o mmu-early.o
pbl-$(CONFIG_MMU) += mmu-early.o obj-pbl-y += setupc$(S64).o cache$(S64).o
lwl-y += lowlevel.o
+ifeq ($(CONFIG_CPU_64v8),)
+obj-y += hyp.o +obj-y += hyp.o
+AFLAGS_hyp.o :=-Wa,-march=armv7-a +AFLAGS_hyp.o :=-Wa,-march=armv7-a
+pbl-y += hyp.o +pbl-y += hyp.o
+AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a +AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a
endif +endif
obj-$(CONFIG_ARM_EXCEPTIONS) += interrupts.o
diff --git a/arch/arm/cpu/hyp.S b/arch/arm/cpu/hyp.S
new file mode 100644
index 000000000000..435d416f980a
--- /dev/null
+++ b/arch/arm/cpu/hyp.S
@@ -0,0 +1,115 @@
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/opcodes-virt.h>
+ +
+.arch_extension sec #
+.arch_extension virt # Any variants can be called as start-armxyz.S
+ #
+.section ".text_bare_init_","ax"
+
+.data
+ .align 2
+ENTRY(__boot_cpu_mode)
+ .long 0
+.text
+
+ENTRY(__hyp_install)
+ mrs r12, cpsr
+ and r12, r12, #MODE_MASK
+
+ @ Save the initial CPU state
+ adr r0, .L__boot_cpu_mode_offset
+ ldr r1, [r0]
+ str r12, [r0, r1]
+
+ cmp r12, #HYP_MODE
+ movne pc, lr @ give up if the CPU is not in HYP mode
+
+ @ Now install the hypervisor stub:
+ adr r12, __hyp_vectors
+ mcr p15, 4, r12, c12, c0, 0 @ set hypervisor vector base (HVBAR)
+
+ @ Disable all traps, so we don't get any nasty surprise
+ mov r12, #0
+ mcr p15, 4, r12, c1, c1, 0 @ HCR
+ mcr p15, 4, r12, c1, c1, 2 @ HCPTR
+ mcr p15, 4, r12, c1, c1, 3 @ HSTR
+
+THUMB( orr r12, #(1 << 30) ) @ HSCTLR.TE
+ mcr p15, 4, r12, c1, c0, 0 @ HSCTLR
+
+ mrc p15, 4, r12, c1, c1, 1 @ HDCR
+ and r12, #0x1f @ Preserve HPMN
+ mcr p15, 4, r12, c1, c1, 1 @ HDCR
+
+ @ Make sure NS-SVC is initialised appropriately
+ mrc p15, 0, r12, c1, c0, 0 @ SCTLR
+ orr r12, #(1 << 5) @ CP15 barriers enabled
+ bic r12, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
+ bic r12, #(3 << 19) @ WXN and UWXN disabled
+ mcr p15, 0, r12, c1, c0, 0 @ SCTLR
+
+ mrc p15, 0, r12, c0, c0, 0 @ MIDR
+ mcr p15, 4, r12, c0, c0, 0 @ VPIDR
+
+ mrc p15, 0, r12, c0, c0, 5 @ MPIDR
+ mcr p15, 4, r12, c0, c0, 5 @ VMPIDR
+ bx lr
+ENDPROC(__hyp_install)
+
+ENTRY(armv7_hyp_install)
+ mov r2, lr
+
+ bl __hyp_install
+
+ /* set the cpu to SVC32 mode, mask irq and fiq */
+ mrs r12 , cpsr
+ eor r12, r12, #HYP_MODE
+ tst r12, #MODE_MASK
+ bic r12 , r12 , #MODE_MASK
+ orr r12 , r12 , #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
+THUMB( orr r12 , r12 , #PSR_T_BIT )
+ bne 1f
+ orr r12, r12, #PSR_A_BIT
+ adr lr, 2f
+ msr spsr_cxsf, r12
+ __MSR_ELR_HYP(14)
+ __ERET
+1: msr cpsr_c, r12
+2:
+ mov pc, r2
+ENDPROC(armv7_hyp_install)
+
+ENTRY(armv7_switch_to_hyp)
+ mov r0, lr
+ mov r1, sp @ save SVC copy of LR and SP
+ isb
+ hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
+ mov sp, r1
+ mov lr, r0 @ restore SVC copy of LR and SP
+
+ bx lr
+ENDPROC(armv7_switch_to_hyp)
+
+.align 2
+.L__boot_cpu_mode_offset:
+ .long __boot_cpu_mode - .
+
+/* The HYP trap is crafted to match armv7_switch_to_hyp() */
+__hyp_do_trap:
+ mov lr, r0
+ mov sp, r1
+ bx lr
+ENDPROC(__hyp_do_trap)
+
+.align 5
+__hyp_vectors:
+__hyp_reset: W(b) .
+__hyp_und: W(b) .
+__hyp_svc: W(b) .
+__hyp_pabort: W(b) .
+__hyp_dabort: W(b) .
+__hyp_trap: W(b) __hyp_do_trap
+__hyp_irq: W(b) .
+__hyp_fiq: W(b) .
+ENDPROC(__hyp_vectors)
diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S diff --git a/arch/arm/cpu/sm_as.S b/arch/arm/cpu/sm_as.S
index 0d01e1bf2435..de6cd0406f4f 100644 index 0d01e1b..de6cd04 100644
--- a/arch/arm/cpu/sm_as.S --- a/arch/arm/cpu/sm_as.S
+++ b/arch/arm/cpu/sm_as.S +++ b/arch/arm/cpu/sm_as.S
@@ -148,17 +148,6 @@ hyp_trap: @@ -148,17 +148,6 @@ hyp_trap:
@ -169,7 +50,7 @@ index 0d01e1bf2435..de6cd0406f4f 100644
mrc p15, 0, r0, c1, c0, 1 @ ACTLR mrc p15, 0, r0, c1, c0, 1 @ ACTLR
orr r0, r0, #(1 << 6) @ Set SMP bit orr r0, r0, #(1 << 6) @ Set SMP bit
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index a4cb1f6c1c44..54cc052b0cf9 100644 index a4cb1f6..54cc052 100644
--- a/arch/arm/include/asm/secure.h --- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h
@@ -6,8 +6,10 @@ @@ -6,8 +6,10 @@
@ -184,4 +65,5 @@ index a4cb1f6c1c44..54cc052b0cf9 100644
enum arm_security_state { enum arm_security_state {
ARM_STATE_SECURE, ARM_STATE_SECURE,
-- --
2.15.1 2.7.4

33
buildroot-external/board/rpi3/patches/barebox/0007-install-HYP-vectors-at-PBL-and-Barebox-entry.patch
View File

@ -1,14 +1,8 @@
If the CPU was already in HYP mode when entering the PBL, install a From f984f8cf4c07f24af7855a4fd69afa3e656238c2 Mon Sep 17 00:00:00 2001
simple trap handler to allow to get back from SVC to HYP before From: Pascal Vizeli <pvizeli@syshack.ch>
switching to HYP mode. Date: Sat, 19 May 2018 17:24:42 +0200
Subject: [PATCH 1/1] p4
As the vectors are part of the currently running binary, we need to
do the same setup when starting the real Barebox binary, as the PBL
setup vectors might get overwritten. To do this we trap into HYP mode
just before jumping to Barebox and then re-do the vector setup and
SVC switch as the first thing in Barebox proper.
Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
--- ---
arch/arm/cpu/lowlevel.S | 3 +++ arch/arm/cpu/lowlevel.S | 3 +++
arch/arm/cpu/start-pbl.c | 3 +++ arch/arm/cpu/start-pbl.c | 3 +++
@ -17,7 +11,7 @@ Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
4 files changed, 13 insertions(+) 4 files changed, 13 insertions(+)
diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 194ce0e7c274..28ad8508726f 100644 index 194ce0e..28ad850 100644
--- a/arch/arm/cpu/lowlevel.S --- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S +++ b/arch/arm/cpu/lowlevel.S
@@ -8,6 +8,9 @@ ENTRY(arm_cpu_lowlevel_init) @@ -8,6 +8,9 @@ ENTRY(arm_cpu_lowlevel_init)
@ -31,10 +25,10 @@ index 194ce0e7c274..28ad8508726f 100644
mrs r12 , cpsr mrs r12 , cpsr
eor r12, r12, #HYP_MODE eor r12, r12, #HYP_MODE
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index e851b4a2da5e..cea1cb200b6f 100644 index 16159d7..3f9959e 100644
--- a/arch/arm/cpu/start-pbl.c --- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c +++ b/arch/arm/cpu/start-pbl.c
@@ -100,5 +100,8 @@ __noreturn void barebox_single_pbl_start(unsigned long membase, @@ -98,5 +98,8 @@ __noreturn void barebox_single_pbl_start(unsigned long membase,
else else
barebox = (void *)barebox_base; barebox = (void *)barebox_base;
@ -44,7 +38,7 @@ index e851b4a2da5e..cea1cb200b6f 100644
barebox(membase, memsize, boarddata); barebox(membase, memsize, boarddata);
} }
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 171e6ad0eb7a..a0db6436f387 100644 index 68fff89..1ee13c0 100644
--- a/arch/arm/cpu/start.c --- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c
@@ -24,6 +24,7 @@ @@ -24,6 +24,7 @@
@ -54,7 +48,7 @@ index 171e6ad0eb7a..a0db6436f387 100644
+#include <asm/secure.h> +#include <asm/secure.h>
#include <asm/unaligned.h> #include <asm/unaligned.h>
#include <asm/cache.h> #include <asm/cache.h>
#include <memory.h> #include <asm/mmu.h>
@@ -145,6 +146,8 @@ __noreturn void barebox_non_pbl_start(unsigned long membase, @@ -145,6 +146,8 @@ __noreturn void barebox_non_pbl_start(unsigned long membase,
unsigned long malloc_start, malloc_end; unsigned long malloc_start, malloc_end;
unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE; unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
@ -65,7 +59,7 @@ index 171e6ad0eb7a..a0db6436f387 100644
unsigned long barebox_base = arm_mem_barebox_image(membase, unsigned long barebox_base = arm_mem_barebox_image(membase,
endmem, endmem,
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 9d7fe0e921a9..28636aa8101f 100644 index b07087e..57f324b 100644
--- a/arch/arm/cpu/uncompress.c --- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c
@@ -27,6 +27,7 @@ @@ -27,6 +27,7 @@
@ -73,10 +67,10 @@ index 9d7fe0e921a9..28636aa8101f 100644
#include <asm-generic/memory_layout.h> #include <asm-generic/memory_layout.h>
#include <asm/sections.h> #include <asm/sections.h>
+#include <asm/secure.h> +#include <asm/secure.h>
#include <asm/pgtable.h>
#include <asm/cache.h> #include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/unaligned.h> #include <asm/unaligned.h>
@@ -109,5 +110,8 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase, @@ -108,5 +109,8 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase,
pr_debug("jumping to uncompressed image at 0x%p\n", barebox); pr_debug("jumping to uncompressed image at 0x%p\n", barebox);
@ -86,4 +80,5 @@ index 9d7fe0e921a9..28636aa8101f 100644
barebox(membase, memsize, boarddata); barebox(membase, memsize, boarddata);
} }
-- --
2.15.1 2.7.4