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Merge pull request #6772 from jernejsk/cleanup
[LE11] Allwinner: Cleanup patches and fix boot issue
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@ -1,273 +0,0 @@
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From f1c04148f8cc62bf99cb06e348f04452d307ebc8 Mon Sep 17 00:00:00 2001
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From: Roman Stratiienko <roman.stratiienko@globallogic.com>
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Date: Sat, 28 Dec 2019 22:28:17 +0200
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Subject: [PATCH 35/44] drm/sun4i: Reimplement plane z position setting logic
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To set blending channel order register software needs to know state and
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position of each channel, which impossible at plane commit stage.
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Move this procedure to atomic_flush stage, where all necessary information
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is available.
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Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/gpu/drm/sun4i/sun8i_mixer.c | 43 ++++++++++++++++++++++++--
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drivers/gpu/drm/sun4i/sun8i_mixer.h | 5 +++
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drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 42 ++++---------------------
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drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 39 +++--------------------
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4 files changed, 57 insertions(+), 72 deletions(-)
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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@@ -250,8 +250,45 @@ int sun8i_mixer_drm_format_to_hw(u32 for
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static void sun8i_mixer_commit(struct sunxi_engine *engine)
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{
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- DRM_DEBUG_DRIVER("Committing changes\n");
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+ struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
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+ int channel_by_zpos[SUN8I_MIXER_MAX_CHANNELS];
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+ u32 base = sun8i_blender_base(mixer);
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+ u32 route = 0, pipe_ctl = 0;
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+ unsigned int channel_count;
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+ int i, j;
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+
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+ channel_count = mixer->cfg->vi_num + mixer->cfg->ui_num;
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+
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+ DRM_DEBUG_DRIVER("Update blender routing\n");
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+
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+ for (i = 0; i < SUN8I_MIXER_MAX_CHANNELS; i++)
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+ channel_by_zpos[i] = -1;
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+
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+ for (i = 0; i < channel_count; i++) {
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+ int zpos = mixer->channel_zpos[i];
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+
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+ if (zpos >= 0 && zpos < channel_count)
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+ channel_by_zpos[zpos] = i;
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+ }
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+ j = 0;
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+ for (i = 0; i < channel_count; i++) {
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+ int ch = channel_by_zpos[i];
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+
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+ if (ch >= 0) {
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+ pipe_ctl |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(j);
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+ route |= ch << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(j);
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+ j++;
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+ }
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+ }
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+
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+ regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
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+ SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, pipe_ctl);
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+
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+ regmap_write(mixer->engine.regs,
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+ SUN8I_MIXER_BLEND_ROUTE(base), route);
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+
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+ DRM_DEBUG_DRIVER("Committing changes\n");
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regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
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SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
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}
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@@ -489,10 +526,12 @@ static int sun8i_mixer_bind(struct devic
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SUN8I_MIXER_BLEND_COLOR_BLACK);
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plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
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- for (i = 0; i < plane_cnt; i++)
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+ for (i = 0; i < plane_cnt; i++) {
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_MODE(base, i),
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SUN8I_MIXER_BLEND_MODE_DEF);
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+ mixer->channel_zpos[i] = -1;
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+ }
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regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
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SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
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@@ -12,6 +12,8 @@
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#include "sunxi_engine.h"
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+#define SUN8I_MIXER_MAX_CHANNELS 5
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+
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#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
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#define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
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@@ -177,6 +179,9 @@ struct sun8i_mixer {
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struct clk *bus_clk;
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struct clk *mod_clk;
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+
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+ /* -1 means that layer is disabled */
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+ int channel_zpos[SUN8I_MIXER_MAX_CHANNELS];
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};
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static inline struct sun8i_mixer *
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--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
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@@ -24,12 +24,10 @@
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#include "sun8i_ui_scaler.h"
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static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel,
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- int overlay, bool enable, unsigned int zpos,
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- unsigned int old_zpos)
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+ int overlay, bool enable, unsigned int zpos)
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{
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- u32 val, bld_base, ch_base;
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+ u32 val, ch_base;
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- bld_base = sun8i_blender_base(mixer);
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ch_base = sun8i_channel_base(mixer, channel);
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DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
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@@ -44,32 +42,7 @@ static void sun8i_ui_layer_enable(struct
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
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- if (!enable || zpos != old_zpos) {
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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- SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
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- 0);
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-
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_ROUTE(bld_base),
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- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
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- 0);
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- }
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-
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- if (enable) {
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- val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
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-
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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- val, val);
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-
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- val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
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-
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_ROUTE(bld_base),
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- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
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- val);
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- }
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+ mixer->channel_zpos[channel] = enable ? zpos : -1;
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}
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static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
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@@ -294,11 +267,9 @@ static void sun8i_ui_layer_atomic_disabl
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struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
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plane);
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struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
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- unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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- sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
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- old_zpos);
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+ sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0);
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}
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static void sun8i_ui_layer_atomic_update(struct drm_plane *plane,
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@@ -310,12 +281,11 @@ static void sun8i_ui_layer_atomic_update
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plane);
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struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane);
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unsigned int zpos = new_state->normalized_zpos;
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- unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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if (!new_state->visible) {
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sun8i_ui_layer_enable(mixer, layer->channel,
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- layer->overlay, false, 0, old_zpos);
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+ layer->overlay, false, 0);
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return;
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}
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@@ -328,7 +298,7 @@ static void sun8i_ui_layer_atomic_update
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sun8i_ui_layer_update_buffer(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay,
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- true, zpos, old_zpos);
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+ true, zpos);
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}
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static const struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = {
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--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
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@@ -18,8 +18,7 @@
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#include "sun8i_vi_scaler.h"
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static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
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- int overlay, bool enable, unsigned int zpos,
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- unsigned int old_zpos)
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+ int overlay, bool enable, unsigned int zpos)
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{
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u32 val, bld_base, ch_base;
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@@ -38,32 +37,7 @@ static void sun8i_vi_layer_enable(struct
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
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- if (!enable || zpos != old_zpos) {
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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- SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
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- 0);
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-
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_ROUTE(bld_base),
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- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
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- 0);
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- }
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-
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- if (enable) {
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- val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
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-
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
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- val, val);
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-
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- val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
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-
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- regmap_update_bits(mixer->engine.regs,
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- SUN8I_MIXER_BLEND_ROUTE(bld_base),
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- SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
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- val);
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- }
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+ mixer->channel_zpos[channel] = enable ? zpos : -1;
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}
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static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
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@@ -398,11 +372,9 @@ static void sun8i_vi_layer_atomic_disabl
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struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
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plane);
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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- unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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- sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
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- old_zpos);
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+ sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0);
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}
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static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
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@@ -414,12 +386,11 @@ static void sun8i_vi_layer_atomic_update
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plane);
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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unsigned int zpos = new_state->normalized_zpos;
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- unsigned int old_zpos = old_state->normalized_zpos;
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struct sun8i_mixer *mixer = layer->mixer;
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if (!new_state->visible) {
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sun8i_vi_layer_enable(mixer, layer->channel,
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- layer->overlay, false, 0, old_zpos);
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+ layer->overlay, false, 0);
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return;
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}
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@@ -432,7 +403,7 @@ static void sun8i_vi_layer_atomic_update
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sun8i_vi_layer_update_buffer(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
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- true, zpos, old_zpos);
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+ true, zpos);
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}
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static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
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@ -1,55 +0,0 @@
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From 144ad308ded7c5617d9574e174b68cbcb622cf4c Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Sun, 19 Jul 2020 11:28:49 +0200
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Subject: [PATCH 36/44] drm/sun4i: Don't use update regmap variant for blend
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pipe register
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Readout might return invalid value, so always write it.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/gpu/drm/sun4i/sun8i_mixer.c | 19 ++++++++-----------
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1 file changed, 8 insertions(+), 11 deletions(-)
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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@@ -282,8 +282,14 @@ static void sun8i_mixer_commit(struct su
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}
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}
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- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
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- SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, pipe_ctl);
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+ /*
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+ * Set fill color of bottom plane to black. Generally not needed
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+ * except when VI plane is at bottom (zpos = 0) and enabled.
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+ */
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+ pipe_ctl |= SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0);
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+
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+ regmap_write(mixer->engine.regs,
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+ SUN8I_MIXER_BLEND_PIPE_CTL(base), pipe_ctl);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ROUTE(base), route);
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@@ -516,12 +522,6 @@ static int sun8i_mixer_bind(struct devic
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
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SUN8I_MIXER_BLEND_COLOR_BLACK);
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- /*
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- * Set fill color of bottom plane to black. Generally not needed
|
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- * except when VI plane is at bottom (zpos = 0) and enabled.
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- */
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- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
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- SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
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SUN8I_MIXER_BLEND_COLOR_BLACK);
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@@ -533,9 +533,6 @@ static int sun8i_mixer_bind(struct devic
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mixer->channel_zpos[i] = -1;
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}
|
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- regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
|
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- SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
|
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-
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return 0;
|
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err_disable_bus_clk:
|
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@ -1,50 +0,0 @@
|
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From b10b474925447933bf1d718e6d064190b15b56d9 Mon Sep 17 00:00:00 2001
|
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From: Jernej Skrabec <jernej.skrabec@siol.net>
|
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Date: Thu, 14 Jan 2021 19:26:03 +0100
|
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Subject: [PATCH 42/44] ASoC: sun4i-i2s: Add parenthesis around macro arguments
|
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|
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Several macro arguments are not put inside parenthesis, which may cause
|
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subtle issues.
|
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|
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Fix those macros.
|
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|
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
sound/soc/sunxi/sun4i-i2s.c | 12 ++++++------
|
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1 file changed, 6 insertions(+), 6 deletions(-)
|
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|
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--- a/sound/soc/sunxi/sun4i-i2s.c
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+++ b/sound/soc/sunxi/sun4i-i2s.c
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@@ -116,16 +116,16 @@
|
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|
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#define SUN8I_I2S_CHAN_CFG_REG 0x30
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#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(7, 4)
|
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-#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
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+#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) (((chan) - 1) << 4)
|
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#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(3, 0)
|
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-#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
|
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+#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) ((chan) - 1)
|
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|
||||
#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
|
||||
#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
|
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#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
|
||||
-#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
|
||||
+#define SUN8I_I2S_TX_CHAN_OFFSET(offset) ((offset) << 12)
|
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#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
|
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-#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
|
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+#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << (num_chan)) - 1) << 4)
|
||||
|
||||
#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
|
||||
#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
|
||||
@@ -134,9 +134,9 @@
|
||||
#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
|
||||
#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
|
||||
#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
|
||||
-#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
|
||||
+#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) (((chan) - 1) << 16)
|
||||
#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
|
||||
-#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
|
||||
+#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << (num_chan)) - 1))
|
||||
|
||||
#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
|
||||
#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
|
||||
@ -5,9 +5,8 @@ Subject: [PATCH] HACK: Disable MBUS due to fw_devlink=on
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/sun8i-r40.dtsi | 1 +
|
||||
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 +
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
|
||||
3 files changed, 3 insertions(+)
|
||||
arch/arm/boot/dts/sun8i-h3.dtsi | 1 +
|
||||
2 files changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
|
||||
index 291f4784e86c..173edaff4c9b 100644
|
||||
@ -21,30 +20,15 @@ index 291f4784e86c..173edaff4c9b 100644
|
||||
};
|
||||
|
||||
tcon_top: tcon-top@1c70000 {
|
||||
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
||||
index c7428df9469e..1cbb871b6628 100644
|
||||
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
||||
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
||||
@@ -575,6 +575,7 @@ mbus: dram-controller@1c62000 {
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
|
||||
#interconnect-cells = <1>;
|
||||
+ status = "disabled";
|
||||
};
|
||||
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
|
||||
index eac2349a2380..3c08f5ee2780 100644
|
||||
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
|
||||
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
|
||||
@@ -297,6 +297,7 @@ &display_clocks {
|
||||
|
||||
spi0: spi@1c68000 {
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
index 6ddb717f2f98..f0ec62b4170b 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
|
||||
@@ -1135,6 +1135,7 @@ mbus: dram-controller@1c62000 {
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
|
||||
#interconnect-cells = <1>;
|
||||
+ status = "disabled";
|
||||
};
|
||||
&mbus {
|
||||
compatible = "allwinner,sun8i-h3-mbus";
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
csi: csi@1cb0000 {
|
||||
--
|
||||
2.33.0
|
||||
|
||||
&mmc0 {
|
||||
|
||||
@ -0,0 +1,49 @@
|
||||
From: Da Xue <da@libre.computer>
|
||||
Date: Thu, 21 Jul 2022 18:08:21 -0400
|
||||
|
||||
Some users experienced problems booting u-boot from SPL hanging here:
|
||||
|
||||
Trying to boot from MMC1 or Trying to boot from MMC2
|
||||
|
||||
This seems to occur with both MicroSD and eMMC modules on ALL-H3-CC.
|
||||
Increasing the delay after mmc reset fixes these boot problems.
|
||||
Some MicroSD cards are impacted more than others so it is possible that
|
||||
MicroSD internals need time to stabilize. Below is some failure data.
|
||||
|
||||
sandisk ultra 64gb 9/20 with 1ms, 20/20 with 10ms
|
||||
sandisk ultra 16gb 2/20 with 1ms, 20/20 with 10ms
|
||||
sandisk extreme 16gb 6/20 with 10ms, 20/20 with 20ms
|
||||
|
||||
A quick comparison of schematics show series resistors for ESD
|
||||
protection on the MicroSD GPIOs not present on all H3/H5 boards.
|
||||
It is not known if this is related to the issue.
|
||||
|
||||
This patch adds a fixed 20ms delay to mmc init to mitigate the problem.
|
||||
If boot time optimization is required and the platform does not require
|
||||
the delay. The delay can be replaced with:
|
||||
|
||||
writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
|
||||
if (wait_for_bit_le32( &priv->reg->gctrl,
|
||||
SUNXI_MMC_GCTRL_RESET, false, 20, false)) {
|
||||
printf("%s: Timeout\n", __func__);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
Signed-off-by: Da Xue <da@libre.computer>
|
||||
---
|
||||
drivers/mmc/sunxi_mmc.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
|
||||
index 1bb7b6d0e9..f7942b69ce 100644
|
||||
--- a/drivers/mmc/sunxi_mmc.c
|
||||
+++ b/drivers/mmc/sunxi_mmc.c
|
||||
@@ -297,7 +297,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
|
||||
|
||||
/* Reset controller */
|
||||
writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
|
||||
- udelay(1000);
|
||||
+ udelay(20000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user