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TinkerBoard: new device
This commit is contained in:
Jonas Karlman
parent
8578fbac02
commit
0f55cb2aed
@ -4,6 +4,8 @@ This project is for Rockchip SoC devices
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## Devices
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* [ASUS Tinker Board](devices/TinkerBoard)
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**My single-board computer is not listed, will it be added in the future?**<br />
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If your single-board computer uses a current generation SoC listed on http://opensource.rock-chips.com/wiki_Main_Page the odds are in your favor.
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46
projects/Rockchip/devices/TinkerBoard/README.md
Normal file
46
projects/Rockchip/devices/TinkerBoard/README.md
Normal file
@ -0,0 +1,46 @@
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# ASUS Tinker Board
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This is an experimental project for the ASUS Tinker Board
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**Progress**
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* [x] LEDs
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* [ ] ~~CEC~~
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* [ ] Audio
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* [x] HDMI Stereo L-PCM
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* [x] HDMI Multi-channel L-PCM
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* [x] HDA 3.5 mm jack
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* [ ] HDMI NL-PCM (AC3/E-AC3/DTS)
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* [ ] HDMI HBR (TrueHD/DTS-HD)
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* [ ] Video
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* [x] Software decoding
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* [ ] Hardware decoding
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* [x] h264 / hevc / vp8
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* [ ] mpeg4 / mpeg2
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* [ ] HDMI Video Format
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* [x] RGB 4:4:4 Limited Range
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* [ ] RGB 4:4:4 Full Range
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* [ ] YCbCr 4:4:4
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* [ ] YCbCr 4:2:0
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* [x] WiFi
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* [x] Bluetooth
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**Known Issues/Limitations**
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* Video output is RGB 4:4:4 8-bit limited range
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* Video aspect ratio / zoom is not working for all modes
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* Generic USB-Audio do not work due to a custom alsa config
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* 4K resolution is limited to 30hz due to failed compliance test
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* CEC is not connected to SoC
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**Serial Console**
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* UART2 on GPIO pin 32/33 with baud rate 115200
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**Build**
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* `PROJECT=Rockchip DEVICE=TinkerBoard ARCH=arm make image`
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## Links
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* Community Forum: https://tinkerboarding.co.uk/forum/
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@ -0,0 +1,21 @@
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#
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# Configuration for ALC4040
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#
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USB-Audio.pcm.default {
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@args [ CARD ]
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@args.CARD { type string }
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type hw
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card $CARD
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device 2
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}
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<confdir:pcm/front.conf>
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USB-Audio.pcm.front.0 {
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@args [ CARD ]
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@args.CARD { type string }
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type hw
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card $CARD
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device 2
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}
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32
projects/Rockchip/devices/TinkerBoard/options
Normal file
32
projects/Rockchip/devices/TinkerBoard/options
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@ -0,0 +1,32 @@
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################################################################################
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# setup device defaults
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################################################################################
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# The TARGET_CPU variable controls which processor should be targeted for
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# generated code.
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case $TARGET_ARCH in
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arm)
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TARGET_FLOAT="hard"
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TARGET_CPU="cortex-a17"
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TARGET_FPU="neon-vfpv4"
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TARGET_FEATURES="32bit neon"
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;;
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esac
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# Configuration for u-boot
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UBOOT_SYSTEM="rk3288"
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# Kernel target
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KERNEL_TARGET="zImage"
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# Additional kernel make parameters (for example to specify the u-boot loadaddress)
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KERNEL_MAKE_EXTRACMD="rk3288-miniarm.dtb"
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# Mali GPU family
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MALI_FAMILY="t760"
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# kernel image name
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KERNEL_NAME="zImage"
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# kernel serial console
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EXTRA_CMDLINE="console=uart8250,mmio32,0xff690000 console=tty0"
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@ -0,0 +1,220 @@
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From d2e1807b0248e9b0068a6f5f018bee44d5519797 Mon Sep 17 00:00:00 2001
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From: Ziyuan Xu <xzy.xu@rock-chips.com>
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Date: Fri, 23 Sep 2016 13:43:18 +0800
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Subject: [PATCH 1/5] MINIARM: HACK: switch vccio_sd to 3.3v while shutdowning
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Change-Id: I80d6d2b61b31f16b6b42b9ffcaab077231a7a91c
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Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
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---
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drivers/mmc/host/dw_mmc-rockchip.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
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index 29e3ae99edbc..531ad93ff912 100644
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--- a/drivers/mmc/host/dw_mmc-rockchip.c
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+++ b/drivers/mmc/host/dw_mmc-rockchip.c
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@@ -13,6 +13,7 @@
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/of_address.h>
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+#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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@@ -285,6 +286,15 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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+static void dw_mci_rockchip_platfm_shutdown(struct platform_device *pdev)
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+{
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+ struct dw_mci *host = platform_get_drvdata(pdev);
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+ struct mmc_host *mmc = host->cur_slot->mmc;
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+
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+ if (!IS_ERR(mmc->supply.vqmmc))
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+ regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
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+}
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+
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#ifdef CONFIG_PM_SLEEP
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static int dw_mci_rockchip_suspend(struct device *dev)
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{
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@@ -308,6 +318,7 @@ static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
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static struct platform_driver dw_mci_rockchip_pltfm_driver = {
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.probe = dw_mci_rockchip_probe,
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.remove = dw_mci_pltfm_remove,
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+ .shutdown = dw_mci_rockchip_platfm_shutdown,
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.driver = {
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.name = "dwmmc_rockchip",
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.of_match_table = dw_mci_rockchip_match,
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From 6683b1dea673b2747a4c20611f058f8a584e5e19 Mon Sep 17 00:00:00 2001
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From: Ziyuan Xu <xzy.xu@rock-chips.com>
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Date: Mon, 6 Feb 2017 08:39:46 +0800
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Subject: [PATCH 2/5] MINIARM: HACK: mmc: dw_mmc-rockchip: enable vmmc supply
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for reboot
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Mmc core has already power off the vmmc since shutdown, re-enable it so
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that card is active in next reboot.
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Change-Id: Id64ed02844db9d834c820ed5b8c5bf7a0afe4ed5
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Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
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---
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drivers/mmc/host/dw_mmc-rockchip.c | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
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index 531ad93ff912..eae304077e17 100644
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--- a/drivers/mmc/host/dw_mmc-rockchip.c
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+++ b/drivers/mmc/host/dw_mmc-rockchip.c
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@@ -15,6 +15,7 @@
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#include <linux/of_address.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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+#include <linux/delay.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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@@ -290,6 +291,12 @@ static void dw_mci_rockchip_platfm_shutdown(struct platform_device *pdev)
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{
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struct dw_mci *host = platform_get_drvdata(pdev);
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struct mmc_host *mmc = host->cur_slot->mmc;
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+ int ret;
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+
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+ mdelay(20);
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+
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+ if (!IS_ERR(mmc->supply.vmmc))
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+ ret = regulator_enable(mmc->supply.vmmc);
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if (!IS_ERR(mmc->supply.vqmmc))
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regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
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From 9eb1e1e71abe6c2b0f10e3c1bd9dfba7acf2c8c5 Mon Sep 17 00:00:00 2001
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From: Jacob Chen <jacob-chen@iotwrt.com>
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Date: Sat, 22 Jul 2017 19:55:09 +0800
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Subject: [PATCH 3/5] MINIARM: drm/rockchip: update phy settings
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Change-Id: I9e92a4191115e13999183a5d7656d6708adda632
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Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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index bc82b964943c..3585b0c10866 100644
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -268,8 +268,7 @@ static struct dw_hdmi_phy_config rockchip_phy_config[] = {
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/*pixelclk symbol term vlev*/
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{ 74250000, 0x8009, 0x0004, 0x0272},
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{ 165000000, 0x802b, 0x0004, 0x0209},
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- { 297000000, 0x8039, 0x0005, 0x028d},
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- { 594000000, 0x8039, 0x0000, 0x019d},
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+ { 297000000, 0x802d, 0x0001, 0x0149},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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From e764ad67f5cf429a368cd406a1a9a2e5ffe3773c Mon Sep 17 00:00:00 2001
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From: Nickey Yang <nickey.yang@rock-chips.com>
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Date: Mon, 17 Jul 2017 16:35:34 +0800
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Subject: [PATCH 4/5] MINIARM: set npll be used for hdmi only
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Change-Id: I8bebfb2cfb68e3dad172e5547d3886526ad5e912
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Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
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---
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arch/arm/boot/dts/rk3288.dtsi | 4 +++-
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drivers/clk/rockchip/clk-rk3288.c | 6 +++---
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2 files changed, 6 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
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index b6d5dc42aee1..38f7c6dd11ca 100644
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--- a/arch/arm/boot/dts/rk3288.dtsi
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+++ b/arch/arm/boot/dts/rk3288.dtsi
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@@ -979,7 +979,7 @@
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<&cru PCLK_PERI>;
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assigned-clock-rates = <594000000>,
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<500000000>, <300000000>,
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- <150000000>, <75000000>,
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+ <0>, <75000000>,
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<300000000>, <150000000>,
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<75000000>;
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};
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@@ -1199,6 +1199,8 @@
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resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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iommus = <&vopb_mmu>;
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+ assigned-clocks = <&cru DCLK_VOP0>;
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+ assigned-clock-parents = <&cru PLL_NPLL>;
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status = "disabled";
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vopb_out: port {
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index 54ff9e36e0e2..77cc66a501f7 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -211,9 +211,9 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
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[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
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RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates),
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[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
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- RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
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+ RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
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[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
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- RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
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+ RK3288_MODE_CON, 14, 9, 0, rk3288_pll_rates),
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};
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static struct clk_div_table div_hclk_cpu_t[] = {
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@@ -428,7 +428,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK3288_CLKGATE_CON(3), 4, GFLAGS),
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- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
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+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
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RK3288_CLKGATE_CON(3), 1, GFLAGS),
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COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
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From 73f855ba760c9df6eb1203948197f13b41365ba0 Mon Sep 17 00:00:00 2001
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From: Nickey Yang <nickey.yang@rock-chips.com>
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Date: Mon, 24 Jul 2017 09:38:03 +0800
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Subject: [PATCH 5/5] MINIARM: clk: rockchip: add some clock settings
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Change-Id: I5f172106258f9dcb5617b245f729b661feacc92c
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Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
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---
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drivers/clk/rockchip/clk-rk3288.c | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
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index 77cc66a501f7..15d3aeb4448c 100644
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--- a/drivers/clk/rockchip/clk-rk3288.c
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+++ b/drivers/clk/rockchip/clk-rk3288.c
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@@ -100,6 +100,29 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
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RK3066_PLL_RATE( 216000000, 1, 72, 8),
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RK3066_PLL_RATE( 148500000, 2, 99, 8),
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RK3066_PLL_RATE( 126000000, 1, 84, 16),
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+ RK3066_PLL_RATE_NB( 241500000, 2, 161, 8, 1),
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+ RK3066_PLL_RATE( 252000000, 1, 84, 8),
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+ RK3066_PLL_RATE( 216000000, 1, 72, 8),
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+ RK3066_PLL_RATE( 148500000, 8, 693, 14),
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+ RK3066_PLL_RATE( 135000000, 4, 315, 14),
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+ RK3066_PLL_RATE( 126000000, 1, 84, 16),
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+ RK3066_PLL_RATE( 119000000, 3, 238, 16),
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+ RK3066_PLL_RATE( 108000000, 1, 72, 16),
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+ RK3066_PLL_RATE( 88750000, 6, 355, 16),
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+ RK3066_PLL_RATE( 71000000, 3, 142, 16),
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+ RK3066_PLL_RATE( 74250000, 8, 297, 12),
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+ RK3066_PLL_RATE( 78750000, 4, 210, 16),
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+ RK3066_PLL_RATE( 78800000, 15, 788, 16),
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+ RK3066_PLL_RATE( 75000000, 2, 100, 16),
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+ RK3066_PLL_RATE( 65000000, 3, 130, 16),
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+ RK3066_PLL_RATE( 136750000, 8, 547, 12),
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+ RK3066_PLL_RATE( 106500000, 1, 71, 16),
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+ RK3066_PLL_RATE( 88750000, 6, 355, 16),
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+ RK3066_PLL_RATE( 67500000, 8, 315, 14),
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+ RK3066_PLL_RATE( 49500000, 1, 33, 16),
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+ RK3066_PLL_RATE( 40000000, 3, 80, 16),
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+ RK3066_PLL_RATE( 36000000, 1, 24, 16),
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+ RK3066_PLL_RATE( 35500000, 3, 71, 16),
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RK3066_PLL_RATE( 48000000, 1, 64, 32),
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{ /* sentinel */ },
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};
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@ -10,6 +10,7 @@ devices = {
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},
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'Rockchip' : {
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'TinkerBoard' : { 'rk3288' : { 'dtb' : 'rk3288-miniarm.dtb', 'config' : 'tinker-rk3288_config' }, },
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},
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}
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