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linux (RPi): add PR6309 to fix occasional "no signal" after modeswitch
Signed-off-by: Matthias Reichl <hias@horus.com>
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@ -0,0 +1,100 @@
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From 733e7a51a128e950d210ef3652f5427e4179e17a Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Mon, 12 Aug 2024 13:31:58 +0100
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Subject: [PATCH 1/3] drm/vc4: Add a delay after disabling hdmi phy output
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There appears to be a requirement for some devices
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(I'm testing with a 8K VRROOM 40Gbps HDMI switch)
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for a measable delay between removing the hdmi phy output from
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the old mode, to enabling the hdmi phy output for the new mode.
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Without the delay, a mode switch has a small change of getting a permanent
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'no signal', which requires a subsequent mode switch or a unplug/replug
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to redetect.
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Switching between 4kp24/25/30 modes fails about 5% of time in my testing.
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Add a delay to make it impossible to switch faster than this.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
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index 859ac51d06f3a..c85737f2b7f73 100644
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -668,6 +668,7 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
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* someone was waiting it.
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*/
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vc4_crtc_send_vblank(crtc);
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+ msleep(20);
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}
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static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
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From 75c37d08890881c02a5db5ef763ef7e97f4253d3 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Tue, 13 Aug 2024 16:13:16 +0100
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Subject: [PATCH 2/3] drm/vc4: Implement vc6_hdmi_phy_disable
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The body of this function was missing so we don't reset the phy
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when disabling it.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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index 0d55627148327..f36558932f083 100644
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--- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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@@ -1197,4 +1197,9 @@ void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
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void vc6_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
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{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
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+ vc6_hdmi_reset_phy(vc4_hdmi);
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+ spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
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}
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From 1360bf475f7a12392e041bb80b20e21b677dcd4c Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Tue, 13 Aug 2024 17:18:51 +0100
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Subject: [PATCH 3/3] drm/vc4: Also power down the PLL core when resetting PHY
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The current reset code doesn't actually stop the hdmi output.
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That makes it difficult for displays to handle a mode set.
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Powering down the PLL does actually remove the hdmi signal
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and makes mode sets more reliable
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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index f36558932f083..83801c2684250 100644
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--- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
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@@ -137,6 +137,7 @@
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#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS BIT(13)
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#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK VC4_MASK(9, 0)
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+#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN BIT(4)
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#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK VC4_MASK(3, 2)
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#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK VC4_MASK(1, 0)
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@@ -947,6 +948,7 @@ static void vc6_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)
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HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
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HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);
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+ HDMI_WRITE(HDMI_TX_PHY_PLL_POST_KDIV, VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN);
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}
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void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
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