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Rockchip: device tree fixes
Enable FE phy for Beelink A1, since we using this as a "box" image, so that ethernet works on foreign devices which don't have a external GE phy. Also: add cec pinctrl settings for RK3288 miqi.
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@ -690,3 +690,54 @@ index 6ca08854aef3..fb21ad1324bc 100644
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pmic {
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pmic_int_l: pmic-int-l {
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rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Mon, 1 Mar 2021 21:24:15 +0100
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Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board
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---
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arch/arm/boot/dts/rk3288-miqi.dts | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
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index 2420d8e1c66f..55ec4a273f59 100644
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--- a/arch/arm/boot/dts/rk3288-miqi.dts
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+++ b/arch/arm/boot/dts/rk3288-miqi.dts
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@@ -145,6 +145,8 @@ &gpu {
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&hdmi {
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ddc-i2c-bus = <&i2c5>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hdmi_cec_c0>;
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status = "okay";
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};
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Mon, 1 Mar 2021 19:22:15 +0100
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Subject: [PATCH] HACK: ARM64: dts: enable FE phy for Beelink A1 also
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---
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arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
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index 1bb3f4a6e496..99f28dac0791 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
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@@ -142,6 +142,14 @@ rtl8211f: ethernet-phy@0 {
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};
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};
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+&gmac2phy {
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+ clock_in_out = "output";
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+ assigned-clock-rate = <50000000>;
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+ assigned-clocks = <&cru SCLK_MAC2PHY>;
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+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
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+ status = "okay";
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+};
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+
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&gpu {
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mali-supply = <&vdd_logic>;
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};
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