Merge pull request #6210 from heitbaum/linux-5.17

linux: update to 5.17.y

packages/linux-drivers/RTL8192EU/package.mk

@@ -3,12 +3,12 @@
 # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
 
 PKG_NAME="RTL8192EU"
-PKG_VERSION="4c9751be79ef847ef44ef63203278f4f05f21e52"
+PKG_VERSION="e0f967cea1d0037c730246c572f7fef000865ff7"
-PKG_SHA256="09a957d70eeec4042116b95a6614676645346dece3c53a467a1a13e8b33a1c83"
+PKG_SHA256="2e11e26fccba644e4e5576948dbc1a5dd3ccd22f89be3d45eaa7c4276b8e766a"
 PKG_LICENSE="GPL"
 PKG_SITE="https://github.com/Mange/rtl8192eu-linux-driver"
 PKG_URL="https://github.com/Mange/rtl8192eu-linux-driver/archive/${PKG_VERSION}.tar.gz"
-PKG_LONGDESC="Realtek RTL8192EU Linux 3.x driver"
+PKG_LONGDESC="Realtek RTL8192EU Linux driver"
 PKG_IS_KERNEL_PKG="yes"
 
 pre_make_target() {

packages/linux-drivers/RTL8812AU/package.mk

@@ -3,12 +3,12 @@
 # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
 
 PKG_NAME="RTL8812AU"
-PKG_VERSION="307d694076b056588c652c2bdaa543a89eb255d9"
+PKG_VERSION="37e27f9165300c89607144b646545fac576ec510"
-PKG_SHA256="51b8f5835afc95a8645277031a20c840db12959b1761ff730a2c0b986653c812"
+PKG_SHA256="749ba2e77d0364381445e40f7f0b7041d861cf9a356dbe53085e3abaef888c1d"
 PKG_LICENSE="GPL"
 PKG_SITE="https://github.com/aircrack-ng/rtl8812au"
 PKG_URL="https://github.com/aircrack-ng/rtl8812au/archive/${PKG_VERSION}.tar.gz"
-PKG_LONGDESC="Realtek RTL8812AU Linux 3.x driver"
+PKG_LONGDESC="Realtek RTL8812AU Linux driver"
 PKG_IS_KERNEL_PKG="yes"
 
 pre_make_target() {

packages/linux-drivers/bcm_sta/patches/bcm_sta-0600-kernel-5.17-fix.patch

@@ -0,0 +1,26 @@
+--- a/x86-64/src/wl/sys/wl_linux.c	2022-02-19 15:22:05.006428601 +0000
++++ b/x86-64/src/wl/sys/wl_linux.c	2022-02-19 21:55:03.290519415 +0000
+@@ -3287,7 +3287,11 @@
+ static ssize_t
+ wl_proc_read(struct file *filp, char __user *buffer, size_t length, loff_t *offp)
+ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
+ 	wl_info_t * wl = PDE_DATA(file_inode(filp));
++#else
++	wl_info_t * wl = file_inode(filp)->i_private;
++#endif
+ #endif
+ 	int bcmerror, len;
+ 	int to_user = 0;
+@@ -3344,7 +3348,11 @@
+ static ssize_t
+ wl_proc_write(struct file *filp, const char __user *buff, size_t length, loff_t *offp)
+ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
+ 	wl_info_t * wl = PDE_DATA(file_inode(filp));
++#else
++	wl_info_t * wl = file_inode(filp)->i_private;
++#endif
+ #endif
+ 	int from_user = 0;
+ 	int bcmerror;

packages/linux-firmware/iwlwifi-firmware/package.mk

@@ -3,8 +3,8 @@
 # Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv)
 
 PKG_NAME="iwlwifi-firmware"
-PKG_VERSION="fbe2571d45b43ae84abd4841ef50735b59a287c9"
+PKG_VERSION="ccf1a23d7f51e98562664c1ae80f51437b1c39dc"
-PKG_SHA256="f2ff60e3b9309292c74c72154a1da4c3c94bbeaea0cc595fd33edc74e5845be4"
+PKG_SHA256="5e3ca25ceb47571e7639a03d6350179834df90a31eb98a5b37536fec4dbace7e"
 PKG_LICENSE="Free-to-use"
 PKG_SITE="https://github.com/LibreELEC/iwlwifi-firmware"
 PKG_URL="https://github.com/LibreELEC/iwlwifi-firmware/archive/${PKG_VERSION}.tar.gz"

packages/linux-firmware/kernel-firmware/package.mk

@@ -2,8 +2,8 @@
 # Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv)
 
 PKG_NAME="kernel-firmware"
-PKG_VERSION="20211216"
+PKG_VERSION="20220209"
-PKG_SHA256="330ae22410701c00c1174d23e22f1d2a98e7d6d5c0b0ed4e34c70a392ac6ca97"
+PKG_SHA256="2fd289256b6127a6528b2243e0227bfe1750833c725b5c9139fad183e94d4172"
 PKG_LICENSE="other"
 PKG_SITE="https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/"
 PKG_URL="https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/snapshot/${PKG_VERSION}.tar.gz"

packages/linux/package.mk

@@ -28,8 +28,8 @@ case "${LINUX}" in
     PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
     ;;
   *)
-    PKG_VERSION="5.16.14"
+    PKG_VERSION="5.17"
-    PKG_SHA256="7a8ba58659d5e5f0f9e1e0a4fbed39ac520149d24d7aec4636fcf8255d0574f6"
+    PKG_SHA256="555fef61dddb591a83d62dd04e252792f9af4ba9ef14683f64840e46fa20b1b1"
     PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz"
     PKG_PATCH_DIRS="default"
     ;;

packages/linux/patches/default/linux-001-5-16-bluetooth-read-codec-capabilities-only-if-supported.patch

@@ -1,55 +0,0 @@
-From 107fe0482b549a0e43a971e5fd104719c6e495ef Mon Sep 17 00:00:00 2001
-From: Kiran K <kiran.k@intel.com>
-Date: Tue, 5 Oct 2021 20:15:56 +0530
-Subject: Bluetooth: Read codec capabilities only if supported
-
-Read codec capabilities only if HCI_READ_LOCAL_CODEC_CAPABILITIES
-command is supported. If capablities are not supported, then
-cache codec data without caps.
-
-Signed-off-by: Kiran K <kiran.k@intel.com>
-Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
----
- net/bluetooth/hci_codec.c | 18 ++++++++++++++++--
- 1 file changed, 16 insertions(+), 2 deletions(-)
-
-diff --git a/net/bluetooth/hci_codec.c b/net/bluetooth/hci_codec.c
-index f0421d0edaa37..38201532f58e8 100644
---- a/net/bluetooth/hci_codec.c
-+++ b/net/bluetooth/hci_codec.c
-@@ -25,9 +25,11 @@ static int hci_codec_list_add(struct list_head *list,
- 	}
- 	entry->transport = sent->transport;
- 	entry->len = len;
--	entry->num_caps = rp->num_caps;
--	if (rp->num_caps)
-+	entry->num_caps = 0;
-+	if (rp) {
-+		entry->num_caps = rp->num_caps;
- 		memcpy(entry->caps, caps, len);
-+	}
- 	list_add(&entry->list, list);
- 
- 	return 0;
-@@ -58,6 +60,18 @@ static void hci_read_codec_capabilities(struct hci_dev *hdev, __u8 transport,
- 			__u32 len;
- 
- 			cmd->transport = i;
-+
-+			/* If Read_Codec_Capabilities command is not supported
-+			 * then just add codec to the list without caps
-+			 */
-+			if (!(hdev->commands[45] & 0x08)) {
-+				hci_dev_lock(hdev);
-+				hci_codec_list_add(&hdev->local_codecs, cmd,
-+						   NULL, NULL, 0);
-+				hci_dev_unlock(hdev);
-+				continue;
-+			}
-+
- 			skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_CODEC_CAPS,
- 					     sizeof(*cmd), cmd,
- 					     HCI_CMD_TIMEOUT);
--- 
-cgit 1.2.3-1.el7
-

packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.09-kernel-5.17.patch

@@ -0,0 +1,18 @@
+--- a/kernel/nv-linux.h	2022-02-20 00:41:53.585928825 +0000
++++ b/kernel/nv-linux.h	2022-02-20 00:43:04.285797471 +0000
+@@ -2051,11 +2051,15 @@
+         __entry;                                               \
+     })
+ 
++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)
+ #if defined(NV_PDE_DATA_PRESENT)
+ # define NV_PDE_DATA(inode) PDE_DATA(inode)
+ #else
+ # define NV_PDE_DATA(inode) PDE(inode)->data
+ #endif
++#else
++# define NV_PDE_DATA(inode) inode->i_private
++#endif
+ 
+ #if defined(NV_PROC_REMOVE_PRESENT)
+ # define NV_REMOVE_PROC_ENTRY(entry)                           \

projects/Allwinner/linux/linux.aarch64.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.16.2 Kernel Configuration
+# Linux/arm64 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621"
 CONFIG_CC_IS_GCC=y
@@ -227,7 +227,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -440,6 +439,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y
 #
 # ARMv8.2 architectural features
 #
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
 # CONFIG_ARM64_PMEM is not set
 # CONFIG_ARM64_RAS_EXTN is not set
 # CONFIG_ARM64_CNP is not set
@@ -671,6 +672,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -816,13 +818,12 @@ CONFIG_MEMORY_FAILURE=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
 # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 CONFIG_CMA_DEBUGFS=y
 CONFIG_CMA_SYSFS=y
 CONFIG_CMA_AREAS=7
+# CONFIG_ZSWAP is not set
 # CONFIG_ZPOOL is not set
 # CONFIG_ZSMALLOC is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y
@@ -838,6 +839,7 @@ CONFIG_ZONE_DMA32=y
 # CONFIG_READ_ONLY_THP_FOR_FS is not set
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1410,6 +1412,7 @@ CONFIG_HAVE_PCI=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1839,6 +1842,7 @@ CONFIG_NET_VENDOR_CAVIUM=y
 CONFIG_NET_VENDOR_CORTINA=y
 # CONFIG_GEMINI_ETHERNET is not set
 # CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 CONFIG_NET_VENDOR_EZCHIP=y
 # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
 # CONFIG_NET_VENDOR_GOOGLE is not set
@@ -1901,6 +1905,7 @@ CONFIG_DWMAC_SUN8I=m
 # CONFIG_DWMAC_INTEL_PLAT is not set
 CONFIG_NET_VENDOR_SYNOPSYS=y
 # CONFIG_DWC_XLGMAC is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 CONFIG_NET_VENDOR_VIA=y
 # CONFIG_VIA_VELOCITY is not set
 CONFIG_NET_VENDOR_WIZNET=y
@@ -2644,14 +2649,14 @@ CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
 CONFIG_PINCTRL_AXP209=y
-# CONFIG_PINCTRL_MCP23S08 is not set
-CONFIG_PINCTRL_SINGLE=y
-# CONFIG_PINCTRL_SX150X is not set
-# CONFIG_PINCTRL_STMFX is not set
 CONFIG_PINCTRL_MAX77620=y
-# CONFIG_PINCTRL_RK805 is not set
+# CONFIG_PINCTRL_MCP23S08 is not set
-# CONFIG_PINCTRL_OCELOT is not set
 # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_RK805 is not set
+CONFIG_PINCTRL_SINGLE=y
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
 
 #
 # Renesas pinctrl drivers
@@ -2756,6 +2761,7 @@ CONFIG_GPIO_MAX77620=y
 #
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2801,6 +2807,7 @@ CONFIG_AXP20X_POWER=y
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
 # CONFIG_CHARGER_BQ24257 is not set
@@ -2922,6 +2929,7 @@ CONFIG_SENSORS_LM90=m
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -2950,6 +2958,7 @@ CONFIG_SENSORS_LM90=m
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -3136,7 +3145,6 @@ CONFIG_MFD_WL1273_CORE=m
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -3182,6 +3190,7 @@ CONFIG_REGULATOR_MAX77620=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MCP16502 is not set
 # CONFIG_REGULATOR_MP5416 is not set
@@ -3631,6 +3640,7 @@ CONFIG_VIDEO_OV2640=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -3924,8 +3934,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100
 CONFIG_DRM_LOAD_EDID_FIRMWARE=y
 # CONFIG_DRM_DP_CEC is not set
 CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
+CONFIG_DRM_GEM_SHMEM_HELPER=m
-CONFIG_DRM_GEM_SHMEM_HELPER=y
 CONFIG_DRM_SCHED=m
 
 #
@@ -3949,7 +3958,8 @@ CONFIG_DRM_I2C_SIL164=m
 # CONFIG_DRM_VKMS is not set
 # CONFIG_DRM_UDL is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 CONFIG_DRM_SUN4I=y
 # CONFIG_DRM_SUN4I_HDMI is not set
 # CONFIG_DRM_SUN4I_BACKEND is not set
@@ -4045,6 +4055,7 @@ CONFIG_DRM_DW_HDMI_CEC=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -4059,6 +4070,7 @@ CONFIG_DRM_PANFROST=m
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -4196,6 +4208,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -4261,6 +4274,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 CONFIG_SND_SOC_AK4613=m
@@ -4357,6 +4371,7 @@ CONFIG_SND_SOC_SPDIF=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -4477,6 +4492,7 @@ CONFIG_HID_KENSINGTON=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 # CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 # CONFIG_HID_LOGITECH_DJ is not set
 CONFIG_HID_LOGITECH_HIDPP=m
@@ -4902,6 +4918,10 @@ CONFIG_LEDS_TRIGGER_PANIC=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_SUPPORT=y
@@ -5154,6 +5174,7 @@ CONFIG_R8188EU=m
 CONFIG_STAGING_MEDIA=y
 CONFIG_VIDEO_HANTRO=m
 CONFIG_VIDEO_HANTRO_SUNXI=y
+# CONFIG_VIDEO_MAX96712 is not set
 CONFIG_VIDEO_SUNXI=y
 CONFIG_VIDEO_SUNXI_CEDRUS=y
 
@@ -5176,6 +5197,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y
 # CONFIG_GOLDFISH is not set
 # CONFIG_CHROME_PLATFORMS is not set
 # CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CLK_PREPARE=y
 CONFIG_COMMON_CLK=y
@@ -5201,6 +5223,7 @@ CONFIG_COMMON_CLK_SCPI=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 # CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
 # CONFIG_COMMON_CLK_S2MPS11 is not set
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 # CONFIG_COMMON_CLK_XGENE is not set
@@ -5351,6 +5374,7 @@ CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
 #
 # DEVFREQ Drivers
 #
+CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
 # CONFIG_PM_DEVFREQ_EVENT is not set
 CONFIG_EXTCON=y
 
@@ -5490,6 +5514,12 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5547,6 +5577,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5566,6 +5597,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5589,6 +5621,12 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5604,6 +5642,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -5900,8 +5939,10 @@ CONFIG_PHY_SUN50I_USB3=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -5923,6 +5964,7 @@ CONFIG_PHY_SAMSUNG_USB2=y
 CONFIG_ARM_PMU=y
 # CONFIG_ARM_DSU_PMU is not set
 # CONFIG_ARM_SPE_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
 # end of Performance monitor support
 
 CONFIG_RAS=y
@@ -6300,7 +6342,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
 # end of Kernel hardening options
 # end of Security options
 
-CONFIG_XOR_BLOCKS=m
+CONFIG_XOR_BLOCKS=y
 CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y
 CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y
 CONFIG_CRYPTO=y
@@ -6447,6 +6489,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6454,25 +6497,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
 CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_BLAKE2S=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
-CONFIG_CRYPTO_LIB_CURVE25519=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 CONFIG_CRYPTO_DEV_ALLWINNER=y
 # CONFIG_CRYPTO_DEV_SUN4I_SS is not set
@@ -6524,7 +6548,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 # CONFIG_CORDIC is not set
 # CONFIG_PRIME_NUMBERS is not set
 CONFIG_RATIONAL=y
@@ -6533,6 +6556,26 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
 CONFIG_INDIRECT_PIO=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
@@ -6693,11 +6736,21 @@ CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
 # CONFIG_UBSAN is not set
 CONFIG_HAVE_KCSAN_COMPILER=y
+CONFIG_HAVE_ARCH_KCSAN=y
+CONFIG_HAVE_KCSAN_COMPILER=y
+# CONFIG_KCSAN is not set
 # end of Generic Kernel Debugging Instruments
 
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -6840,12 +6893,12 @@ CONFIG_STRICT_DEVMEM=y
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_ARCH_HAS_KCOV=y
 CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
 CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_LKDTM is not set
 # CONFIG_TEST_MIN_HEAP is not set
 # CONFIG_TEST_DIV64 is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_REED_SOLOMON_TEST is not set
 # CONFIG_INTERVAL_TREE_TEST is not set
@@ -6863,7 +6916,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_XARRAY is not set
 # CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_IDA is not set
 # CONFIG_TEST_LKM is not set
 # CONFIG_TEST_BITOPS is not set

projects/Allwinner/linux/linux.arm.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 5.16.5 Kernel Configuration
+# Linux/arm 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0"
 CONFIG_CC_IS_GCC=y
@@ -220,7 +220,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -652,6 +651,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
 CONFIG_HAVE_EXIT_THREAD=y
 CONFIG_ARCH_MMAP_RND_BITS=8
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -790,8 +790,6 @@ CONFIG_CONTIG_ALLOC=y
 CONFIG_BOUNCE=y
 # CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 CONFIG_CMA_DEBUGFS=y
@@ -806,6 +804,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
 # CONFIG_GUP_TEST is not set
 CONFIG_KMAP_LOCAL=y
 CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1338,6 +1337,7 @@ CONFIG_HAVE_PCI=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1536,7 +1536,6 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_ISCSI_BOOT_SYSFS is not set
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_UFS_HWMON is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_DH is not set
 # end of SCSI device support
@@ -1654,6 +1653,7 @@ CONFIG_NET_VENDOR_CORTINA=y
 # CONFIG_GEMINI_ETHERNET is not set
 # CONFIG_DM9000 is not set
 # CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 CONFIG_NET_VENDOR_EZCHIP=y
 # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -1702,6 +1702,7 @@ CONFIG_DWMAC_SUN8I=y
 # CONFIG_DWMAC_INTEL_PLAT is not set
 CONFIG_NET_VENDOR_SYNOPSYS=y
 # CONFIG_DWC_XLGMAC is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_NET_VENDOR_XILINX is not set
@@ -2363,11 +2364,11 @@ CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
 CONFIG_PINCTRL_AXP209=y
 # CONFIG_PINCTRL_MCP23S08 is not set
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PINCTRL_SX150X is not set
-# CONFIG_PINCTRL_STMFX is not set
-# CONFIG_PINCTRL_OCELOT is not set
 # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
 
 #
 # Renesas pinctrl drivers
@@ -2470,6 +2471,7 @@ CONFIG_GPIO_CDEV_V1=y
 #
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2502,6 +2504,7 @@ CONFIG_AXP20X_POWER=y
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
 # CONFIG_CHARGER_BQ24257 is not set
@@ -2622,6 +2625,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -2650,6 +2654,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 # CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -2846,7 +2851,6 @@ CONFIG_MFD_WL1273_CORE=m
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -2888,6 +2892,7 @@ CONFIG_REGULATOR_GPIO=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MCP16502 is not set
 # CONFIG_REGULATOR_MP5416 is not set
@@ -3333,6 +3338,7 @@ CONFIG_VIDEO_ST_MIPID02=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -3634,8 +3640,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100
 CONFIG_DRM_LOAD_EDID_FIRMWARE=y
 # CONFIG_DRM_DP_CEC is not set
 CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
+CONFIG_DRM_GEM_SHMEM_HELPER=m
-CONFIG_DRM_GEM_SHMEM_HELPER=y
 CONFIG_DRM_SCHED=m
 
 #
@@ -3661,7 +3666,8 @@ CONFIG_DRM_SCHED=m
 # CONFIG_DRM_UDL is not set
 # CONFIG_DRM_ARMADA is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 CONFIG_DRM_SUN4I=y
 CONFIG_DRM_SUN4I_HDMI=y
 CONFIG_DRM_SUN4I_HDMI_CEC=y
@@ -3750,6 +3756,7 @@ CONFIG_DRM_DW_HDMI_CEC=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -3766,6 +3773,7 @@ CONFIG_DRM_LIMA=m
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -3876,6 +3884,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -3939,6 +3948,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 # CONFIG_SND_SOC_AK4613 is not set
@@ -4034,6 +4044,7 @@ CONFIG_SND_SOC_SPDIF=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -4154,6 +4165,7 @@ CONFIG_HID_KENSINGTON=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 # CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 # CONFIG_HID_LOGITECH_DJ is not set
 CONFIG_HID_LOGITECH_HIDPP=m
@@ -4581,6 +4593,10 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_ATOMIC_SCRUB=y
@@ -4820,6 +4836,7 @@ CONFIG_R8188EU=m
 
 CONFIG_STAGING_MEDIA=y
 # CONFIG_VIDEO_HANTRO is not set
+# CONFIG_VIDEO_MAX96712 is not set
 CONFIG_VIDEO_SUNXI=y
 CONFIG_VIDEO_SUNXI_CEDRUS=y
 
@@ -4863,6 +4880,7 @@ CONFIG_COMMON_CLK=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 # CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 # CONFIG_COMMON_CLK_PWM is not set
 # CONFIG_COMMON_CLK_VC5 is not set
@@ -4975,6 +4993,7 @@ CONFIG_DEVFREQ_GOV_PASSIVE=y
 #
 # DEVFREQ Drivers
 #
+CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
 CONFIG_PM_DEVFREQ_EVENT=y
 CONFIG_EXTCON=y
 
@@ -5113,6 +5132,12 @@ CONFIG_SUN4I_GPADC=y
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5170,6 +5195,7 @@ CONFIG_SUN4I_GPADC=y
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5189,6 +5215,7 @@ CONFIG_SUN4I_GPADC=y
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5212,6 +5239,11 @@ CONFIG_SUN4I_GPADC=y
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5227,6 +5259,7 @@ CONFIG_SUN4I_GPADC=y
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -5513,8 +5546,10 @@ CONFIG_PHY_SUN50I_USB3=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -6010,6 +6045,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=m
 CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6017,24 +6053,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
 CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_LIB_BLAKE2S=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
-CONFIG_CRYPTO_LIB_CURVE25519=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 CONFIG_CRYPTO_DEV_ALLWINNER=y
 CONFIG_CRYPTO_DEV_SUN4I_SS=m
@@ -6091,6 +6109,25 @@ CONFIG_CORDIC=m
 CONFIG_RATIONAL=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
@@ -6234,6 +6271,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -6261,6 +6305,8 @@ CONFIG_HAVE_ARCH_KASAN=y
 CONFIG_CC_HAS_KASAN_GENERIC=y
 CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
 # CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
 # end of Memory Debugging
 
 # CONFIG_DEBUG_SHIRQ is not set
@@ -6344,6 +6390,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
 CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
 CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
 # CONFIG_SAMPLES is not set
@@ -6356,6 +6403,7 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_UNWINDER_FRAME_POINTER is not set
 CONFIG_UNWINDER_ARM=y
 CONFIG_ARM_UNWIND=y
+# CONFIG_BACKTRACE_VERBOSE is not set
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_LL is not set
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
@@ -6378,6 +6426,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_MIN_HEAP is not set
 # CONFIG_TEST_DIV64 is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_REED_SOLOMON_TEST is not set
 # CONFIG_INTERVAL_TREE_TEST is not set
@@ -6395,7 +6444,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_XARRAY is not set
 # CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_IDA is not set
 # CONFIG_TEST_LKM is not set
 # CONFIG_TEST_BITOPS is not set

projects/Allwinner/patches/linux/0035-ARM-dts-sun8i-Adjust-power-key-nodes.patch

@@ -1,107 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sat, 30 Jan 2021 18:12:26 +0100
-Subject: [PATCH] ARM: dts: sun8i: Adjust power key nodes
-
-Several H3 and one H2+ board have power key nodes, which are slightly
-off. Some are missing wakeup-source property and some have BTN_0 code
-assigned instead of KEY_POWER.
-
-Adjust them, so they can function as intended by designer.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-[BananaPi M2 Zero changes]
-Signed-off-by: Michael Klein <michael@fossekall.de>
----
- arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 3 ++-
- arch/arm/boot/dts/sun8i-h3-nanopi.dtsi               | 1 +
- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts            | 3 ++-
- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts           | 3 ++-
- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi        | 3 ++-
- arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi     | 1 +
- 6 files changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
-index 8e8634ff2f9d..d5c7b7984d85 100644
---- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
-@@ -52,8 +52,9 @@ gpio_keys {
- 
- 		sw4 {
- 			label = "power";
--			linux,code = <BTN_0>;
-+			linux,code = <KEY_POWER>;
- 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+			wakeup-source;
- 		};
- 	};
- 
-diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
-index c7c3e7d8b3c8..fc45d5aaa67f 100644
---- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
-+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
-@@ -81,6 +81,7 @@ k1 {
- 			label = "k1";
- 			linux,code = <KEY_POWER>;
- 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+			wakeup-source;
- 		};
- 	};
- };
-diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
-index 597c425d08ec..9daffd90c12f 100644
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
-@@ -99,8 +99,9 @@ sw2 {
- 
- 		sw4 {
- 			label = "sw4";
--			linux,code = <BTN_0>;
-+			linux,code = <KEY_POWER>;
- 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+			wakeup-source;
- 		};
- 	};
- 
-diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
-index 5aff8ecc66cb..90f75fa85e68 100644
---- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
-@@ -91,8 +91,9 @@ r_gpio_keys {
- 
- 		sw4 {
- 			label = "sw4";
--			linux,code = <BTN_0>;
-+			linux,code = <KEY_POWER>;
- 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+			wakeup-source;
- 		};
- 	};
- };
-diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
-index 7a6af54dd342..d03f5853ef7b 100644
---- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
-+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
-@@ -82,8 +82,9 @@ gpio_keys {
- 
- 		sw4 {
- 			label = "power";
--			linux,code = <BTN_0>;
-+			linux,code = <KEY_POWER>;
- 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+			wakeup-source;
- 		};
- 	};
- 
-diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
-index c44fd726945a..9e14fe5fdcde 100644
---- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
-+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
-@@ -49,6 +49,7 @@ power {
- 			label = "power";
- 			linux,code = <KEY_POWER>;
- 			gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
-+			wakeup-source;
- 		};
- 	};
- 

projects/Allwinner/patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch

@@ -5,14 +5,14 @@ Subject: [PATCH] arm64: dts: allwinner: h6: tanix-tx6: enable ethernet
 
 Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
 ---
- .../dts/allwinner/sun50i-h6-tanix-tx6.dts     | 28 +++++++++++++++++++
+ .../dts/allwinner/sun50i-h6-tanix.dtsi     | 28 +++++++++++++++++++
  1 file changed, 28 insertions(+)
 
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
 @@ -13,6 +13,7 @@
- 	compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6";
  
+ / {
  	aliases {
 +		ethernet0 = &emac;
  		serial0 = &uart0;
@@ -63,7 +63,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
  	pinctrl-names = "default";
  	pinctrl-0 = <&mmc0_pins>;
 @@ -119,6 +143,10 @@
- 	vcc-pc-supply = <&reg_vcc1v8>;
+ 	vcc-pg-supply = <&reg_vcc1v8>;
  };
  
 +&pwm {
@@ -71,5 +71,5 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
 +};
 +
  &r_ir {
- 	linux,rc-map-name = "rc-tanix-tx5max";
  	status = "okay";
+ };

projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch

@@ -1,108 +0,0 @@
-From ba918badf612c19b4e31a57b2ff4baa06e99d7d5 Mon Sep 17 00:00:00 2001
-From: heitbaum <rudi@heitbaum.com>
-Date: Sun, 23 May 2021 06:37:45 +0000
-Subject: [PATCH] Allwinner: linux: enable BT on Tanix TX6 and add wifi node for rtl8822cs (rtw88)
-
-Add and enable dts nodes for both rtw88 (rtl8822cs sdio) and uart rtl8822cs bluetooth.
-
-# udevadm info /sys/bus/sdio/devices/mmc1\:0001\:1/
-P: /devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1
-L: 0
-E:
-DEVPATH=/devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1
-E: OF_NAME=sdio-wifi
-E: OF_FULLNAME=/soc/mmc@4021000/sdio-wifi@1
-E: OF_COMPATIBLE_N=0
-E: SDIO_CLASS=07
-E: SDIO_ID=024C:C822
-E: SDIO_REVISION=0.0
-E: MODALIAS=sdio:c07v024CdC822
-E: SUBSYSTEM=sdio
-
-# dmesg | grep hci0
-Bluetooth: hci0: RTL: examining hci_ver=08 hci_rev=000c subver=8822
-Bluetooth: hci0: RTL: rom_version status=0 version=3
-Bluetooth: hci0: RTL: loading rtl_bt/rtl8822cs_fw.bin
-Bluetooth: hci0: RTL: loading rtl_bt/rtl8822cs_config.bin
-
----
- .../dts/allwinner/sun50i-h6-tanix-tx6.dts     | 32 +++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
-@@ -47,12 +47,29 @@
- 		regulator-max-microvolt = <3300000>;
- 	};
- 
-+	reg_vcc_wifi_io: vcc-wifi-io {
-+		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc-wifi-io";
-+		regulator-min-microvolt = <1800000>;
-+		regulator-max-microvolt = <1800000>;
-+		regulator-always-on;
-+		vin-supply = <&reg_vcc3v3>;
-+	};
-+
- 	reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
- 		compatible = "regulator-fixed";
- 		regulator-name = "vdd-cpu-gpu";
- 		regulator-min-microvolt = <1135000>;
- 		regulator-max-microvolt = <1135000>;
- 	};
-+
-+	wifi_pwrseq: wifi-pwrseq {
-+		compatible = "mmc-pwrseq-simple";
-+		clocks = <&rtc 1>;
-+		clock-names = "ext_clock";
-+		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
-+	};
- };
- 
- &ac200_pwm_clk {
-@@ -122,6 +139,22 @@
- 	status = "okay";
- };
- 
-+&mmc1 {
-+    vmmc-supply = <&reg_vcc3v3>;
-+    vqmmc-supply = <&reg_vcc_wifi_io>;
-+    mmc-pwrseq = <&wifi_pwrseq>;
-+    bus-width = <4>;
-+    non-removable;
-+    status = "okay";
-+
-+    rtl8822cs: sdio-wifi@1 {
-+        reg = <1>;
-+        interrupt-parent = <&r_pio>;
-+        interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
-+        interrupt-names = "host-wake";
-+    };
-+};
-+
- &mmc2 {
- 	vmmc-supply = <&reg_vcc3v3>;
- 	vqmmc-supply = <&reg_vcc1v8>;
-@@ -158,6 +191,21 @@
- 	status = "okay";
- };
- 
-+&uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-+	uart-has-rtscts;
-+	status = "okay";
-+
-+	bluetooth {
-+		//use 8822cs compatible to load hci_h5 and btrtl driver
-+		compatible = "realtek,rtl8822cs-bt";
-+		device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
-+		host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
-+		enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
-+	};
-+};
-+
- &usb2otg {
- 	dr_mode = "host";
- 	status = "okay";

projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-enable-rtw88-wifi-in-dts.patch

@@ -0,0 +1,58 @@
+From ba918badf612c19b4e31a57b2ff4baa06e99d7d5 Mon Sep 17 00:00:00 2001
+From: heitbaum <rudi@heitbaum.com>
+Date: Sun, 23 May 2021 06:37:45 +0000
+Subject: [PATCH] Allwinner: linux: add wifi node for rtl8822cs (rtw88)
+
+Add and enable dts node for rtw88 (rtl8822cs sdio)
+
+# udevadm info /sys/bus/sdio/devices/mmc1\:0001\:1/
+P: /devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1
+L: 0
+E:
+DEVPATH=/devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1
+E: OF_NAME=sdio-wifi
+E: OF_FULLNAME=/soc/mmc@4021000/sdio-wifi@1
+E: OF_COMPATIBLE_N=0
+E: SDIO_CLASS=07
+E: SDIO_ID=024C:C822
+E: SDIO_REVISION=0.0
+E: MODALIAS=sdio:c07v024CdC822
+E: SUBSYSTEM=sdio
+
+---
+ .../dts/allwinner/sun50i-h6-tanix-tx6.dtsi     | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+@@ -52,6 +52,16 @@
+ 		regulator-max-microvolt = <3300000>;
+ 	};
+ 
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
+ 	reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vdd-cpu-gpu";
+@@ -159,6 +169,13 @@
+ 	bus-width = <4>;
+ 	non-removable;
+ 	status = "okay";
++
++	rtl8822cs: sdio-wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
++		interrupt-names = "host-wake";
++	};
+ };
+ 
+ &mmc2 {

projects/Allwinner/patches/linux/0061-arm64-dts-allwinner-h6-tanix-tx6-Add-SPDIF.patch

@@ -1,54 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Mon, 8 Nov 2021 20:48:17 +0100
-Subject: [PATCH] arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF
-
-Tanix TX6 board has SPDIF connector in form of 3.5 mm jack.
-
-Add support for it.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../dts/allwinner/sun50i-h6-tanix-tx6.dts     | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
-index 8f2a80f128de..6c10ff7f4b1c 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
-@@ -52,6 +52,24 @@ reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
- 		regulator-min-microvolt = <1135000>;
- 		regulator-max-microvolt = <1135000>;
- 	};
-+
-+	sound-spdif {
-+		compatible = "simple-audio-card";
-+		simple-audio-card,name = "sun50i-h6-spdif";
-+
-+		simple-audio-card,cpu {
-+			sound-dai = <&spdif>;
-+		};
-+
-+		simple-audio-card,codec {
-+			sound-dai = <&spdif_out>;
-+		};
-+	};
-+
-+	spdif_out: spdif-out {
-+		#sound-dai-cells = <0>;
-+		compatible = "linux,spdif-dit";
-+	};
- };
- 
- &cpu0 {
-@@ -127,6 +145,10 @@ &r_ir {
- 	status = "okay";
- };
- 
-+&spdif {
-+	status = "okay";
-+};
-+
- &uart0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&uart0_ph_pins>;

projects/Allwinner/patches/linux/0062-ASoC-sunxi-sun4i-spdif-Implement-IEC958-control.patch

@@ -1,132 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Tue, 9 Nov 2021 18:52:37 +0100
-Subject: [PATCH] ASoC: sunxi: sun4i-spdif: Implement IEC958 control
-
-SPDIF core is capable of sending custom status.
-
-Implement IEC958 control handling.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- sound/soc/sunxi/sun4i-spdif.c | 95 +++++++++++++++++++++++++++++++++++
- 1 file changed, 95 insertions(+)
-
-diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c
-index a10949bf0ca1..e80982b229ff 100644
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -21,6 +21,7 @@
- #include <linux/platform_device.h>
- #include <linux/pm_runtime.h>
- #include <linux/reset.h>
-+#include <sound/asoundef.h>
- #include <sound/dmaengine_pcm.h>
- #include <sound/pcm_params.h>
- #include <sound/soc.h>
-@@ -385,11 +386,105 @@ static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
- 	return ret;
- }
- 
-+static int sun4i_spdif_info(struct snd_kcontrol *kcontrol,
-+			    struct snd_ctl_elem_info *uinfo)
-+{
-+	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
-+	uinfo->count = 1;
-+
-+	return 0;
-+}
-+
-+static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol,
-+				       struct snd_ctl_elem_value *ucontrol)
-+{
-+	u8 *status = ucontrol->value.iec958.status;
-+
-+	status[0] = 0xff;
-+	status[1] = 0xff;
-+	status[2] = 0xff;
-+	status[3] = 0xff;
-+	status[4] = 0xff;
-+
-+	return 0;
-+}
-+
-+static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
-+				  struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
-+	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
-+	u8 *status = ucontrol->value.iec958.status;
-+	unsigned int reg;
-+
-+	regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, &reg);
-+
-+	status[0] = reg & 0xff;
-+	status[1] = (reg >> 8) & 0xff;
-+	status[2] = (reg >> 16) & 0xff;
-+	status[3] = (reg >> 24) & 0xff;
-+
-+	regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, &reg);
-+
-+	status[4] = reg & 0xff;
-+
-+	return 0;
-+}
-+
-+static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
-+				  struct snd_ctl_elem_value *ucontrol)
-+{
-+	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
-+	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
-+	u8 *status = ucontrol->value.iec958.status;
-+	unsigned int reg;
-+
-+	reg = ((u32)status[3] << 24);
-+	reg |= ((u32)status[2] << 16);
-+	reg |= ((u32)status[1] << 8);
-+	reg |= (u32)status[0];
-+
-+	regmap_write(host->regmap, SUN4I_SPDIF_TXCHSTA0, reg);
-+
-+	reg = status[4];
-+	regmap_write(host->regmap, SUN4I_SPDIF_TXCHSTA1, reg);
-+
-+	reg = SUN4I_SPDIF_TXCFG_CHSTMODE;
-+	if (status[0] & IEC958_AES0_NONAUDIO)
-+		reg |= SUN4I_SPDIF_TXCFG_NONAUDIO;
-+
-+	regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
-+			   SUN4I_SPDIF_TXCFG_CHSTMODE |
-+			   SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
-+
-+	return 0;
-+}
-+
-+static struct snd_kcontrol_new sun4i_spdif_controls[] = {
-+	{
-+		.access = SNDRV_CTL_ELEM_ACCESS_READ,
-+		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
-+		.info = sun4i_spdif_info,
-+		.get = sun4i_spdif_get_status_mask
-+	},
-+	{
-+		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
-+		.name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
-+		.info = sun4i_spdif_info,
-+		.get = sun4i_spdif_get_status,
-+		.put = sun4i_spdif_set_status
-+	}
-+};
-+
- static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
- {
- 	struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
- 
- 	snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
-+	snd_soc_add_dai_controls(dai, sun4i_spdif_controls,
-+				 ARRAY_SIZE(sun4i_spdif_controls));
-+
- 	return 0;
- }
- 

projects/Allwinner/patches/linux/0064-ARM-dts-sun8i-h3-beelink-x2-Add-GPIO-CEC-node.patch

@@ -1,32 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sat, 20 Nov 2021 10:35:25 +0100
-Subject: [PATCH] ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node
-
-Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has
-dedicated GPIO pin for that purpose.
-
-Add a node for it.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
-index f0e591e1c771..4ab4bbf001ba 100644
---- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
-+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
-@@ -57,6 +57,12 @@ aliases {
- 		ethernet1 = &sdiowifi;
- 	};
- 
-+	cec-gpio {
-+		compatible = "cec-gpio";
-+		cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
-+		hdmi-phandle = <&hdmi>;
-+	};
-+
- 	chosen {
- 		stdout-path = "serial0:115200n8";
- 	};

projects/Allwinner/patches/linux/0066-drm-sun4i-virtual-CMA-addresses-are-not-needed.patch

@@ -1,31 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Tue, 5 Oct 2021 17:22:04 +0200
-Subject: [PATCH] drm/sun4i: virtual CMA addresses are not needed
-
-Driver never uses virtual address of DRM CMA buffers. Switch to CMA
-helpers which don't deal with virtual mapping.
-
-This was actually already the case before commit ad408c766cef
-("drm/sun4i: Use DRM_GEM_CMA_VMAP_DRIVER_OPS for GEM operations"),
-but only convenient macro at the time used helpers with virtual
-mapping.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
-index 54dd562e294c..b630614b3d72 100644
---- a/drivers/gpu/drm/sun4i/sun4i_drv.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
-@@ -53,7 +53,7 @@ static const struct drm_driver sun4i_drv_driver = {
- 	.minor			= 0,
- 
- 	/* GEM Operations */
--	DRM_GEM_CMA_DRIVER_OPS_VMAP_WITH_DUMB_CREATE(drm_sun4i_gem_dumb_create),
-+	DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(drm_sun4i_gem_dumb_create),
- };
- 
- static int sun4i_drv_bind(struct device *dev)

projects/Allwinner/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch

@@ -1,42 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:31 +0100
-Subject: [PATCH] hantro: postproc: Fix motion vector space size
-
-When the post-processor hardware block is enabled, the driver
-allocates an internal queue of buffers for the decoder enginer,
-and uses the vb2 queue for the post-processor engine.
-
-For instance, on a G1 core, the decoder engine produces NV12 buffers
-and the post-processor engine can produce YUY2 buffers. The decoder
-engine expects motion vectors to be appended to the NV12 buffers,
-but this is only required for CODECs that need motion vectors,
-such as H.264.
-
-Fix the post-processor logic accordingly.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro_postproc.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index ed8916c950a4..07842152003f 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -132,9 +132,10 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)
- 	unsigned int num_buffers = cap_queue->num_buffers;
- 	unsigned int i, buf_size;
- 
--	buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage +
--		   hantro_h264_mv_size(ctx->dst_fmt.width,
--				       ctx->dst_fmt.height);
-+	buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage;
-+	if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
-+		buf_size += hantro_h264_mv_size(ctx->dst_fmt.width,
-+						ctx->dst_fmt.height);
- 
- 	for (i = 0; i < num_buffers; ++i) {
- 		struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];

projects/Allwinner/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch

@@ -1,229 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:32 +0100
-Subject: [PATCH] hantro: postproc: Introduce struct hantro_postproc_ops
-
-Turns out the post-processor block on the G2 core is substantially
-different from the one on the G1 core. Introduce hantro_postproc_ops
-with .enable and .disable methods, which will allow to support
-the G2 post-processor cleanly.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro.h         |  5 +--
- drivers/staging/media/hantro/hantro_hw.h      | 13 ++++++-
- .../staging/media/hantro/hantro_postproc.c    | 35 +++++++++++++------
- drivers/staging/media/hantro/imx8m_vpu_hw.c   |  2 +-
- .../staging/media/hantro/rockchip_vpu_hw.c    |  6 ++--
- .../staging/media/hantro/sama5d4_vdec_hw.c    |  2 +-
- 6 files changed, 45 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index c2e2dca38628..c2e01959dc00 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -28,6 +28,7 @@
- 
- struct hantro_ctx;
- struct hantro_codec_ops;
-+struct hantro_postproc_ops;
- 
- #define HANTRO_JPEG_ENCODER	BIT(0)
- #define HANTRO_ENCODERS		0x0000ffff
-@@ -59,6 +60,7 @@ struct hantro_irq {
-  * @num_dec_fmts:		Number of decoder formats.
-  * @postproc_fmts:		Post-processor formats.
-  * @num_postproc_fmts:		Number of post-processor formats.
-+ * @postproc_ops:		Post-processor ops.
-  * @codec:			Supported codecs
-  * @codec_ops:			Codec ops.
-  * @init:			Initialize hardware, optional.
-@@ -69,7 +71,6 @@ struct hantro_irq {
-  * @num_clocks:			number of clocks in the array
-  * @reg_names:			array of register range names
-  * @num_regs:			number of register range names in the array
-- * @postproc_regs:		&struct hantro_postproc_regs pointer
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -80,6 +81,7 @@ struct hantro_variant {
- 	unsigned int num_dec_fmts;
- 	const struct hantro_fmt *postproc_fmts;
- 	unsigned int num_postproc_fmts;
-+	const struct hantro_postproc_ops *postproc_ops;
- 	unsigned int codec;
- 	const struct hantro_codec_ops *codec_ops;
- 	int (*init)(struct hantro_dev *vpu);
-@@ -90,7 +92,6 @@ struct hantro_variant {
- 	int num_clocks;
- 	const char * const *reg_names;
- 	int num_regs;
--	const struct hantro_postproc_regs *postproc_regs;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index 267a6d33a47b..2f85430682d8 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -174,6 +174,17 @@ struct hantro_postproc_ctx {
- 	struct hantro_aux_buf dec_q[VB2_MAX_FRAME];
- };
- 
-+/**
-+ * struct hantro_postproc_ops - post-processor operations
-+ *
-+ * @enable:	Enable the post-processor block. Optional.
-+ * @disable:	Disable the post-processor block. Optional.
-+ */
-+struct hantro_postproc_ops {
-+	void (*enable)(struct hantro_ctx *ctx);
-+	void (*disable)(struct hantro_ctx *ctx);
-+};
-+
- /**
-  * struct hantro_codec_ops - codec mode specific operations
-  *
-@@ -221,7 +232,7 @@ extern const struct hantro_variant rk3328_vpu_variant;
- extern const struct hantro_variant rk3399_vpu_variant;
- extern const struct hantro_variant sama5d4_vdec_variant;
- 
--extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
-+extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
- 
- extern const u32 hantro_vp8_dec_mc_filter[8][6];
- 
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 07842152003f..882fb8bc5ddd 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -15,14 +15,14 @@
- #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \
- { \
- 	hantro_reg_write(vpu, \
--			 &(vpu)->variant->postproc_regs->reg_name, \
-+			 &hantro_g1_postproc_regs.reg_name, \
- 			 val); \
- }
- 
- #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \
- { \
- 	hantro_reg_write_s(vpu, \
--			   &(vpu)->variant->postproc_regs->reg_name, \
-+			   &hantro_g1_postproc_regs.reg_name, \
- 			   val); \
- }
- 
-@@ -64,16 +64,13 @@ bool hantro_needs_postproc(const struct hantro_ctx *ctx,
- 	return fmt->fourcc != V4L2_PIX_FMT_NV12;
- }
- 
--void hantro_postproc_enable(struct hantro_ctx *ctx)
-+static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
- 	struct vb2_v4l2_buffer *dst_buf;
- 	u32 src_pp_fmt, dst_pp_fmt;
- 	dma_addr_t dst_dma;
- 
--	if (!vpu->variant->postproc_regs)
--		return;
--
- 	/* Turn on pipeline mode. Must be done first. */
- 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
- 
-@@ -154,12 +151,30 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)
- 	return 0;
- }
- 
--void hantro_postproc_disable(struct hantro_ctx *ctx)
-+static void hantro_postproc_g1_disable(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
- 
--	if (!vpu->variant->postproc_regs)
--		return;
--
- 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
- }
-+
-+void hantro_postproc_disable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+
-+	if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable)
-+		vpu->variant->postproc_ops->disable(ctx);
-+}
-+
-+void hantro_postproc_enable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+
-+	if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable)
-+		vpu->variant->postproc_ops->enable(ctx);
-+}
-+
-+const struct hantro_postproc_ops hantro_g1_postproc_ops = {
-+	.enable = hantro_postproc_g1_enable,
-+	.disable = hantro_postproc_g1_disable,
-+};
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index ea919bfb9891..22fa7d2f3b64 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -262,7 +262,7 @@ const struct hantro_variant imx8mq_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
- 	.postproc_fmts = imx8m_vpu_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
- 		 HANTRO_H264_DECODER,
- 	.codec_ops = imx8mq_vpu_codec_ops,
-diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-index d4f52957cc53..6c1ad5534ce5 100644
---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
-+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-@@ -460,7 +460,7 @@ const struct hantro_variant rk3036_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
- 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
- 		 HANTRO_H264_DECODER,
- 	.codec_ops = rk3036_vpu_codec_ops,
-@@ -485,7 +485,7 @@ const struct hantro_variant rk3066_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
- 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
- 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
- 	.codec_ops = rk3066_vpu_codec_ops,
-@@ -505,7 +505,7 @@ const struct hantro_variant rk3288_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
- 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
- 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
- 	.codec_ops = rk3288_vpu_codec_ops,
-diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-index 9c3b8cd0b239..f3fecc7248c4 100644
---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-@@ -100,7 +100,7 @@ const struct hantro_variant sama5d4_vdec_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts),
- 	.postproc_fmts = sama5d4_vdec_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
- 		 HANTRO_H264_DECODER,
- 	.codec_ops = sama5d4_vdec_codec_ops,

projects/Allwinner/patches/linux/0069-hantro-Simplify-postprocessor.patch

@@ -1,97 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:33 +0100
-Subject: [PATCH] hantro: Simplify postprocessor
-
-Add a 'postprocessed' boolean property to struct hantro_fmt
-to signal that a format is produced by the post-processor.
-This will allow to introduce the G2 post-processor in a simple way.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro.h          | 2 ++
- drivers/staging/media/hantro/hantro_postproc.c | 8 +-------
- drivers/staging/media/hantro/imx8m_vpu_hw.c    | 1 +
- drivers/staging/media/hantro/rockchip_vpu_hw.c | 1 +
- drivers/staging/media/hantro/sama5d4_vdec_hw.c | 1 +
- 5 files changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index c2e01959dc00..dd5e56765d4e 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -263,6 +263,7 @@ struct hantro_ctx {
-  * @max_depth:	Maximum depth, for bitstream formats
-  * @enc_fmt:	Format identifier for encoder registers.
-  * @frmsize:	Supported range of frame sizes (only for bitstream formats).
-+ * @postprocessed: Indicates if this format needs the post-processor.
-  */
- struct hantro_fmt {
- 	char *name;
-@@ -272,6 +273,7 @@ struct hantro_fmt {
- 	int max_depth;
- 	enum hantro_enc_fmt enc_fmt;
- 	struct v4l2_frmsize_stepwise frmsize;
-+	bool postprocessed;
- };
- 
- struct hantro_reg {
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 882fb8bc5ddd..4549aec08feb 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -53,15 +53,9 @@ const struct hantro_postproc_regs hantro_g1_postproc_regs = {
- bool hantro_needs_postproc(const struct hantro_ctx *ctx,
- 			   const struct hantro_fmt *fmt)
- {
--	struct hantro_dev *vpu = ctx->dev;
--
- 	if (ctx->is_encoder)
- 		return false;
--
--	if (!vpu->variant->postproc_fmts)
--		return false;
--
--	return fmt->fourcc != V4L2_PIX_FMT_NV12;
-+	return fmt->postprocessed;
- }
- 
- static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 22fa7d2f3b64..02e61438220a 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -82,6 +82,7 @@ static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_YUYV,
- 		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
- 	},
- };
- 
-diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-index 6c1ad5534ce5..f372f767d4ff 100644
---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
-+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-@@ -62,6 +62,7 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_YUYV,
- 		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
- 	},
- };
- 
-diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-index f3fecc7248c4..b2fc1c5613e1 100644
---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-@@ -15,6 +15,7 @@ static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_YUYV,
- 		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
- 	},
- };
- 

projects/Allwinner/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch

@@ -1,65 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:34 +0100
-Subject: [PATCH] hantro: Add quirk for NV12/NV12_4L4 capture format
-
-The G2 core decoder engine produces NV12_4L4 format,
-which is a simple NV12 4x4 tiled format. The driver currently
-hides this format by always enabling the post-processor engine,
-and therefore offering NV12 directly.
-
-This is done without using the logic in hantro_postproc.c
-and therefore makes it difficult to add VP9 cleanly.
-
-Since fixing this is not easy, add a small quirk to force
-NV12 if HEVC was configured, but otherwise declare NV12_4L4
-as the pixel format in imx8mq_vpu_g2_variant.dec_fmts.
-
-This will be used by the VP9 decoder which will be added soon.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro_v4l2.c  | 14 ++++++++++++++
- drivers/staging/media/hantro/imx8m_vpu_hw.c |  2 +-
- 2 files changed, 15 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
-index bcb0bdff4a9a..d1f060c55fed 100644
---- a/drivers/staging/media/hantro/hantro_v4l2.c
-+++ b/drivers/staging/media/hantro/hantro_v4l2.c
-@@ -150,6 +150,20 @@ static int vidioc_enum_fmt(struct file *file, void *priv,
- 	unsigned int num_fmts, i, j = 0;
- 	bool skip_mode_none;
- 
-+	/*
-+	 * The HEVC decoder on the G2 core needs a little quirk to offer NV12
-+	 * only on the capture side. Once the post-processor logic is used,
-+	 * we will be able to expose NV12_4L4 and NV12 as the other cases,
-+	 * and therefore remove this quirk.
-+	 */
-+	if (capture && ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) {
-+		if (f->index == 0) {
-+			f->pixelformat = V4L2_PIX_FMT_NV12;
-+			return 0;
-+		}
-+		return -EINVAL;
-+	}
-+
- 	/*
- 	 * When dealing with an encoder:
- 	 *  - on the capture side we want to filter out all MODE_NONE formats.
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 02e61438220a..a40b161e5956 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -134,7 +134,7 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
- 
- static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
- 	{
--		.fourcc = V4L2_PIX_FMT_NV12,
-+		.fourcc = V4L2_PIX_FMT_NV12_4L4,
- 		.codec_mode = HANTRO_MODE_NONE,
- 	},
- 	{

projects/Allwinner/patches/linux/0074-media-hantro-Rename-registers.patch

@@ -1,138 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:38 +0100
-Subject: [PATCH] media: hantro: Rename registers
-
-Add more consistency in the way registers are named.
-
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- .../staging/media/hantro/hantro_g2_hevc_dec.c | 40 +++++++++----------
- drivers/staging/media/hantro/hantro_g2_regs.h | 28 ++++++-------
- 2 files changed, 34 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-index 76a921163b9a..abae36f9b418 100644
---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-@@ -448,9 +448,9 @@ static int set_ref(struct hantro_ctx *ctx)
- 		if (dpb[i].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR)
- 			dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);
- 
--		hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr);
--		hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr);
--		hantro_write_addr(vpu, G2_REG_DMV_REF(i), mv_addr);
-+		hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
-+		hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
-+		hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
- 	}
- 
- 	luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val);
-@@ -460,20 +460,20 @@ static int set_ref(struct hantro_ctx *ctx)
- 	chroma_addr = luma_addr + cr_offset;
- 	mv_addr = luma_addr + mv_offset;
- 
--	hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr);
--	hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr);
--	hantro_write_addr(vpu, G2_REG_DMV_REF(i++), mv_addr);
-+	hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
-+	hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
-+	hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr);
- 
--	hantro_write_addr(vpu, G2_ADDR_DST, luma_addr);
--	hantro_write_addr(vpu, G2_ADDR_DST_CHR, chroma_addr);
--	hantro_write_addr(vpu, G2_ADDR_DST_MV, mv_addr);
-+	hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);
-+	hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);
-+	hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);
- 
- 	hantro_hevc_ref_remove_unused(ctx);
- 
- 	for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
--		hantro_write_addr(vpu, G2_REG_ADDR_REF(i), 0);
--		hantro_write_addr(vpu, G2_REG_CHR_REF(i), 0);
--		hantro_write_addr(vpu, G2_REG_DMV_REF(i), 0);
-+		hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);
-+		hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0);
-+		hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0);
- 	}
- 
- 	hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);
-@@ -499,7 +499,7 @@ static void set_buffers(struct hantro_ctx *ctx)
- 	src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
- 	src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0);
- 
--	hantro_write_addr(vpu, G2_ADDR_STR, src_dma);
-+	hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma);
- 	hantro_reg_write(vpu, &g2_stream_len, src_len);
- 	hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);
- 	hantro_reg_write(vpu, &g2_strm_start_offset, 0);
-@@ -508,12 +508,12 @@ static void set_buffers(struct hantro_ctx *ctx)
- 	/* Destination (decoded frame) buffer. */
- 	dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf);
- 
--	hantro_write_addr(vpu, G2_RASTER_SCAN, dst_dma);
--	hantro_write_addr(vpu, G2_RASTER_SCAN_CHR, dst_dma + cr_offset);
--	hantro_write_addr(vpu, G2_ADDR_TILE_SIZE, ctx->hevc_dec.tile_sizes.dma);
--	hantro_write_addr(vpu, G2_TILE_FILTER, ctx->hevc_dec.tile_filter.dma);
--	hantro_write_addr(vpu, G2_TILE_SAO, ctx->hevc_dec.tile_sao.dma);
--	hantro_write_addr(vpu, G2_TILE_BSD, ctx->hevc_dec.tile_bsd.dma);
-+	hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);
-+	hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + cr_offset);
-+	hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);
-+	hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma);
-+	hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma);
-+	hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma);
- }
- 
- static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
-@@ -563,7 +563,7 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
- 			for (k = 0; k < 8; k++)
- 				*p++ = sc->scaling_list_32x32[i][8 * k + j];
- 
--	hantro_write_addr(vpu, HEVC_SCALING_LIST, ctx->hevc_dec.scaling_lists.dma);
-+	hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
- }
- 
- static void hantro_g2_check_idle(struct hantro_dev *vpu)
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index bb22fa921914..24b18f839ff8 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -177,20 +177,20 @@
- #define G2_REG_CONFIG_DEC_CLK_GATE_E		BIT(16)
- #define G2_REG_CONFIG_DEC_CLK_GATE_IDLE_E	BIT(17)
- 
--#define G2_ADDR_DST		(G2_SWREG(65))
--#define G2_REG_ADDR_REF(i)	(G2_SWREG(67)  + ((i) * 0x8))
--#define G2_ADDR_DST_CHR		(G2_SWREG(99))
--#define G2_REG_CHR_REF(i)	(G2_SWREG(101) + ((i) * 0x8))
--#define G2_ADDR_DST_MV		(G2_SWREG(133))
--#define G2_REG_DMV_REF(i)	(G2_SWREG(135) + ((i) * 0x8))
--#define G2_ADDR_TILE_SIZE	(G2_SWREG(167))
--#define G2_ADDR_STR		(G2_SWREG(169))
--#define HEVC_SCALING_LIST	(G2_SWREG(171))
--#define G2_RASTER_SCAN		(G2_SWREG(175))
--#define G2_RASTER_SCAN_CHR	(G2_SWREG(177))
--#define G2_TILE_FILTER		(G2_SWREG(179))
--#define G2_TILE_SAO		(G2_SWREG(181))
--#define G2_TILE_BSD		(G2_SWREG(183))
-+#define G2_OUT_LUMA_ADDR		(G2_SWREG(65))
-+#define G2_REF_LUMA_ADDR(i)		(G2_SWREG(67)  + ((i) * 0x8))
-+#define G2_OUT_CHROMA_ADDR		(G2_SWREG(99))
-+#define G2_REF_CHROMA_ADDR(i)		(G2_SWREG(101) + ((i) * 0x8))
-+#define G2_OUT_MV_ADDR			(G2_SWREG(133))
-+#define G2_REF_MV_ADDR(i)		(G2_SWREG(135) + ((i) * 0x8))
-+#define G2_TILE_SIZES_ADDR		(G2_SWREG(167))
-+#define G2_STREAM_ADDR			(G2_SWREG(169))
-+#define G2_HEVC_SCALING_LIST_ADDR	(G2_SWREG(171))
-+#define G2_RS_OUT_LUMA_ADDR		(G2_SWREG(175))
-+#define G2_RS_OUT_CHROMA_ADDR		(G2_SWREG(177))
-+#define G2_TILE_FILTER_ADDR		(G2_SWREG(179))
-+#define G2_TILE_SAO_ADDR		(G2_SWREG(181))
-+#define G2_TILE_BSD_ADDR		(G2_SWREG(183))
- 
- #define g2_strm_buffer_len	G2_DEC_REG(258, 0, 0xffffffff)
- #define g2_strm_start_offset	G2_DEC_REG(259, 0, 0xffffffff)

projects/Allwinner/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch

@@ -1,178 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:39 +0100
-Subject: [PATCH] media: hantro: Prepare for other G2 codecs
-
-VeriSilicon Hantro G2 core supports other codecs besides hevc.
-Factor out some common code in preparation for vp9 support.
-
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/Makefile         |  1 +
- drivers/staging/media/hantro/hantro.h         |  7 +++++
- drivers/staging/media/hantro/hantro_drv.c     |  5 +++
- drivers/staging/media/hantro/hantro_g2.c      | 26 ++++++++++++++++
- .../staging/media/hantro/hantro_g2_hevc_dec.c | 31 -------------------
- drivers/staging/media/hantro/hantro_g2_regs.h |  7 +++++
- drivers/staging/media/hantro/hantro_hw.h      |  2 ++
- 7 files changed, 48 insertions(+), 31 deletions(-)
- create mode 100644 drivers/staging/media/hantro/hantro_g2.c
-
-diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile
-index 90036831fec4..fe6d84871d07 100644
---- a/drivers/staging/media/hantro/Makefile
-+++ b/drivers/staging/media/hantro/Makefile
-@@ -12,6 +12,7 @@ hantro-vpu-y += \
- 		hantro_g1_mpeg2_dec.o \
- 		hantro_g2_hevc_dec.o \
- 		hantro_g1_vp8_dec.o \
-+		hantro_g2.o \
- 		rockchip_vpu2_hw_jpeg_enc.o \
- 		rockchip_vpu2_hw_h264_dec.o \
- 		rockchip_vpu2_hw_mpeg2_dec.o \
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index dd5e56765d4e..d91eb2b1c509 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -369,6 +369,13 @@ static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
- 	writel(val, vpu->dec_base + reg);
- }
- 
-+static inline void hantro_write_addr(struct hantro_dev *vpu,
-+				     unsigned long offset,
-+				     dma_addr_t addr)
-+{
-+	vdpu_write(vpu, addr & 0xffffffff, offset);
-+}
-+
- static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
- {
- 	u32 val = readl(vpu->dec_base + reg);
-diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
-index fb82b9297a2b..bb72e5e208b7 100644
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -907,6 +907,11 @@ static int hantro_probe(struct platform_device *pdev)
- 	vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
- 	vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
- 
-+	/**
-+	 * TODO: Eventually allow taking advantage of full 64-bit address space.
-+	 * Until then we assume the MSB portion of buffers' base addresses is
-+	 * always 0 due to this masking operation.
-+	 */
- 	ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
- 	if (ret) {
- 		dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
-diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c
-new file mode 100644
-index 000000000000..6f3e1f797f83
---- /dev/null
-+++ b/drivers/staging/media/hantro/hantro_g2.c
-@@ -0,0 +1,26 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Hantro VPU codec driver
-+ *
-+ * Copyright (C) 2021 Collabora Ltd, Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-+ */
-+
-+#include "hantro_hw.h"
-+#include "hantro_g2_regs.h"
-+
-+void hantro_g2_check_idle(struct hantro_dev *vpu)
-+{
-+	int i;
-+
-+	for (i = 0; i < 3; i++) {
-+		u32 status;
-+
-+		/* Make sure the VPU is idle */
-+		status = vdpu_read(vpu, G2_REG_INTERRUPT);
-+		if (status & G2_REG_INTERRUPT_DEC_E) {
-+			dev_warn(vpu->dev, "device still running, aborting");
-+			status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS;
-+			vdpu_write(vpu, status, G2_REG_INTERRUPT);
-+		}
-+	}
-+}
-diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-index abae36f9b418..f62608b0b408 100644
---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-@@ -8,20 +8,6 @@
- #include "hantro_hw.h"
- #include "hantro_g2_regs.h"
- 
--#define HEVC_DEC_MODE	0xC
--
--#define BUS_WIDTH_32		0
--#define BUS_WIDTH_64		1
--#define BUS_WIDTH_128		2
--#define BUS_WIDTH_256		3
--
--static inline void hantro_write_addr(struct hantro_dev *vpu,
--				     unsigned long offset,
--				     dma_addr_t addr)
--{
--	vdpu_write(vpu, addr & 0xffffffff, offset);
--}
--
- static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-@@ -566,23 +552,6 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
- 	hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
- }
- 
--static void hantro_g2_check_idle(struct hantro_dev *vpu)
--{
--	int i;
--
--	for (i = 0; i < 3; i++) {
--		u32 status;
--
--		/* Make sure the VPU is idle */
--		status = vdpu_read(vpu, G2_REG_INTERRUPT);
--		if (status & G2_REG_INTERRUPT_DEC_E) {
--			dev_warn(vpu->dev, "device still running, aborting");
--			status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS;
--			vdpu_write(vpu, status, G2_REG_INTERRUPT);
--		}
--	}
--}
--
- int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index 24b18f839ff8..136ba6d98a1f 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -27,6 +27,13 @@
- #define G2_REG_INTERRUPT_DEC_IRQ_DIS	BIT(4)
- #define G2_REG_INTERRUPT_DEC_E		BIT(0)
- 
-+#define HEVC_DEC_MODE			0xc
-+
-+#define BUS_WIDTH_32			0
-+#define BUS_WIDTH_64			1
-+#define BUS_WIDTH_128			2
-+#define BUS_WIDTH_256			3
-+
- #define g2_strm_swap		G2_DEC_REG(2, 28, 0xf)
- #define g2_dirmv_swap		G2_DEC_REG(2, 20, 0xf)
- 
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index 2f85430682d8..1d869abf90b2 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -312,4 +312,6 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
- void hantro_vp8_prob_update(struct hantro_ctx *ctx,
- 			    const struct v4l2_ctrl_vp8_frame *hdr);
- 
-+void hantro_g2_check_idle(struct hantro_dev *vpu);
-+
- #endif /* HANTRO_HW_H_ */

projects/Allwinner/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch

@@ -1,27 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:41 +0100
-Subject: [PATCH] media: hantro: Staticize a struct in postprocessor code
-
-The struct is not used outside this file, so it can be static.
-
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro_postproc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 4549aec08feb..89de43021779 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -33,7 +33,7 @@
- #define VPU_PP_OUT_RGB			0x0
- #define VPU_PP_OUT_YUYV			0x3
- 
--const struct hantro_postproc_regs hantro_g1_postproc_regs = {
-+static const struct hantro_postproc_regs hantro_g1_postproc_regs = {
- 	.pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1},
- 	.max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
- 	.clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},

projects/Allwinner/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch

@@ -1,161 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:42 +0100
-Subject: [PATCH] media: hantro: Support NV12 on the G2 core
-
-The G2 decoder block produces NV12 4x4 tiled format (NV12_4L4).
-Enable the G2 post-processor block, in order to produce regular NV12.
-
-The logic in hantro_postproc.c is leveraged to take care of allocating
-the extra buffers and configure the post-processor, which is
-significantly simpler than the one on the G1.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- .../staging/media/hantro/hantro_g2_vp9_dec.c  |  6 ++--
- drivers/staging/media/hantro/hantro_hw.h      |  1 +
- .../staging/media/hantro/hantro_postproc.c    | 31 +++++++++++++++++++
- drivers/staging/media/hantro/imx8m_vpu_hw.c   | 11 +++++++
- 4 files changed, 46 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-index fc55b03a8004..e04242d10fa2 100644
---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-@@ -152,7 +152,7 @@ static void config_output(struct hantro_ctx *ctx,
- 	hantro_reg_write(ctx->dev, &g2_out_dis, 0);
- 	hantro_reg_write(ctx->dev, &g2_output_format, 0);
- 
--	luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0);
-+	luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
- 	hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr);
- 
- 	chroma_addr = luma_addr + chroma_offset(ctx, dec_params);
-@@ -191,7 +191,7 @@ static void config_ref(struct hantro_ctx *ctx,
- 	hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width);
- 	hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height);
- 
--	luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0);
-+	luma_addr = hantro_get_dec_buf_addr(ctx, &buf->base.vb.vb2_buf);
- 	hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr);
- 
- 	chroma_addr = luma_addr + chroma_offset(ctx, dec_params);
-@@ -236,7 +236,7 @@ static void config_ref_registers(struct hantro_ctx *ctx,
- 	config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts);
- 	config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts);
- 
--	mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) +
-+	mv_addr = hantro_get_dec_buf_addr(ctx, &mv_ref->base.vb.vb2_buf) +
- 		  mv_offset(ctx, dec_params);
- 	hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr);
- 
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index fe5b51046d33..dbe51303724b 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -310,6 +310,7 @@ extern const struct hantro_variant rk3399_vpu_variant;
- extern const struct hantro_variant sama5d4_vdec_variant;
- 
- extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
-+extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
- 
- extern const u32 hantro_vp8_dec_mc_filter[8][6];
- 
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 89de43021779..a7774ad4c445 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -11,6 +11,7 @@
- #include "hantro.h"
- #include "hantro_hw.h"
- #include "hantro_g1_regs.h"
-+#include "hantro_g2_regs.h"
- 
- #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \
- { \
-@@ -99,6 +100,21 @@ static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
- 	HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
- }
- 
-+static void hantro_postproc_g2_enable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+	struct vb2_v4l2_buffer *dst_buf;
-+	size_t chroma_offset = ctx->dst_fmt.width * ctx->dst_fmt.height;
-+	dma_addr_t dst_dma;
-+
-+	dst_buf = hantro_get_dst_buf(ctx);
-+	dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
-+
-+	hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);
-+	hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset);
-+	hantro_reg_write(vpu, &g2_out_rs_e, 1);
-+}
-+
- void hantro_postproc_free(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-@@ -127,6 +143,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)
- 	if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
- 		buf_size += hantro_h264_mv_size(ctx->dst_fmt.width,
- 						ctx->dst_fmt.height);
-+	else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME)
-+		buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width,
-+					       ctx->dst_fmt.height);
- 
- 	for (i = 0; i < num_buffers; ++i) {
- 		struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
-@@ -152,6 +171,13 @@ static void hantro_postproc_g1_disable(struct hantro_ctx *ctx)
- 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
- }
- 
-+static void hantro_postproc_g2_disable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+
-+	hantro_reg_write(vpu, &g2_out_rs_e, 0);
-+}
-+
- void hantro_postproc_disable(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-@@ -172,3 +198,8 @@ const struct hantro_postproc_ops hantro_g1_postproc_ops = {
- 	.enable = hantro_postproc_g1_enable,
- 	.disable = hantro_postproc_g1_disable,
- };
-+
-+const struct hantro_postproc_ops hantro_g2_postproc_ops = {
-+	.enable = hantro_postproc_g2_enable,
-+	.disable = hantro_postproc_g2_disable,
-+};
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 455a107ffb02..1a43f6fceef9 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -132,6 +132,14 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
- 	},
- };
- 
-+static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = {
-+	{
-+		.fourcc = V4L2_PIX_FMT_NV12,
-+		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
-+	},
-+};
-+
- static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_NV12_4L4,
-@@ -301,6 +309,9 @@ const struct hantro_variant imx8mq_vpu_g2_variant = {
- 	.dec_offset = 0x0,
- 	.dec_fmts = imx8m_vpu_g2_dec_fmts,
- 	.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts),
-+	.postproc_fmts = imx8m_vpu_g2_postproc_fmts,
-+	.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_g2_postproc_fmts),
-+	.postproc_ops = &hantro_g2_postproc_ops,
- 	.codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER,
- 	.codec_ops = imx8mq_vpu_g2_codec_ops,
- 	.init = imx8mq_vpu_hw_init,

projects/Allwinner/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch

@@ -1,92 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sat, 7 Aug 2021 17:29:11 +0200
-Subject: [PATCH] media: hantro: add support for reset lines
-
-Some SoCs like Allwinner H6 use reset lines for resetting Hantro G2. Add
-support for them.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h     |  3 +++
- drivers/staging/media/hantro/hantro_drv.c | 15 ++++++++++++++-
- 2 files changed, 17 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index 7da23f7f207a..33eb3e092cc1 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -16,6 +16,7 @@
- #include <linux/videodev2.h>
- #include <linux/wait.h>
- #include <linux/clk.h>
-+#include <linux/reset.h>
- 
- #include <media/v4l2-ctrls.h>
- #include <media/v4l2-device.h>
-@@ -171,6 +172,7 @@ hantro_vdev_to_func(struct video_device *vdev)
-  * @dev:		Pointer to device for convenient logging using
-  *			dev_ macros.
-  * @clocks:		Array of clock handles.
-+ * @resets:		Array of reset handles.
-  * @reg_bases:		Mapped addresses of VPU registers.
-  * @enc_base:		Mapped address of VPU encoder register for convenience.
-  * @dec_base:		Mapped address of VPU decoder register for convenience.
-@@ -190,6 +192,7 @@ struct hantro_dev {
- 	struct platform_device *pdev;
- 	struct device *dev;
- 	struct clk_bulk_data *clocks;
-+	struct reset_control *resets;
- 	void __iomem **reg_bases;
- 	void __iomem *enc_base;
- 	void __iomem *dec_base;
-diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
-index 3d3107a39dae..770f4ce71d29 100644
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -905,6 +905,10 @@ static int hantro_probe(struct platform_device *pdev)
- 			return PTR_ERR(vpu->clocks[0].clk);
- 	}
- 
-+	vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true);
-+	if (IS_ERR(vpu->resets))
-+		return PTR_ERR(vpu->resets);
-+
- 	num_bases = vpu->variant->num_regs ?: 1;
- 	vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
- 				      sizeof(*vpu->reg_bases), GFP_KERNEL);
-@@ -978,10 +982,16 @@ static int hantro_probe(struct platform_device *pdev)
- 	pm_runtime_use_autosuspend(vpu->dev);
- 	pm_runtime_enable(vpu->dev);
- 
-+	ret = reset_control_deassert(vpu->resets);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to deassert resets\n");
-+		goto err_pm_disable;
-+	}
-+
- 	ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
- 	if (ret) {
- 		dev_err(&pdev->dev, "Failed to prepare clocks\n");
--		goto err_pm_disable;
-+		goto err_rst_assert;
- 	}
- 
- 	ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
-@@ -1037,6 +1047,8 @@ static int hantro_probe(struct platform_device *pdev)
- 	v4l2_device_unregister(&vpu->v4l2_dev);
- err_clk_unprepare:
- 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
-+err_rst_assert:
-+	reset_control_assert(vpu->resets);
- err_pm_disable:
- 	pm_runtime_dont_use_autosuspend(vpu->dev);
- 	pm_runtime_disable(vpu->dev);
-@@ -1056,6 +1068,7 @@ static int hantro_remove(struct platform_device *pdev)
- 	v4l2_m2m_release(vpu->m2m_dev);
- 	v4l2_device_unregister(&vpu->v4l2_dev);
- 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
-+	reset_control_assert(vpu->resets);
- 	pm_runtime_dont_use_autosuspend(vpu->dev);
- 	pm_runtime_disable(vpu->dev);
- 	return 0;

projects/Allwinner/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch

@@ -1,63 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sun, 21 Nov 2021 20:39:11 +0100
-Subject: [PATCH] media: hantro: vp9: use double buffering if needed
-
-Some G2 variants need double buffering to be enabled in order to work
-correctly, like that found in Allwinner H6 SoC.
-
-Add platform quirk for that.
-
-Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h            | 2 ++
- drivers/staging/media/hantro/hantro_g2_regs.h    | 1 +
- drivers/staging/media/hantro/hantro_g2_vp9_dec.c | 2 ++
- 3 files changed, 5 insertions(+)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index 33eb3e092cc1..d03824fa3222 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -73,6 +73,7 @@ struct hantro_irq {
-  * @num_clocks:			number of clocks in the array
-  * @reg_names:			array of register range names
-  * @num_regs:			number of register range names in the array
-+ * @double_buffer:		core needs double buffering
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -94,6 +95,7 @@ struct hantro_variant {
- 	int num_clocks;
- 	const char * const *reg_names;
- 	int num_regs;
-+	unsigned int double_buffer : 1;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index 9c857dd1ad9b..15a391a4650e 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -270,6 +270,7 @@
- #define g2_apf_threshold	G2_DEC_REG(55, 0, 0xffff)
- 
- #define g2_clk_gate_e		G2_DEC_REG(58, 16, 0x1)
-+#define g2_double_buffer_e	G2_DEC_REG(58, 15, 0x1)
- #define g2_buswidth		G2_DEC_REG(58, 8,  0x7)
- #define g2_max_burst		G2_DEC_REG(58, 0,  0xff)
- 
-diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-index e04242d10fa2..d4fc649a4da1 100644
---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-@@ -847,6 +847,8 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p
- 	hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1);
- 	hantro_reg_write(ctx->dev, &g2_max_cb_size, 6);
- 	hantro_reg_write(ctx->dev, &g2_min_cb_size, 3);
-+	if (ctx->dev->variant->double_buffer)
-+		hantro_reg_write(ctx->dev, &g2_double_buffer_e, 1);
- 
- 	config_output(ctx, dst, dec_params);
- 

projects/Allwinner/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch

@@ -1,242 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sun, 26 Sep 2021 19:47:03 +0200
-Subject: [PATCH] media: hantro: vp9: add support for legacy register set
-
-Some older G2 cores uses slightly different register set for HEVC and
-VP9. Since vast majority of registers and logic is the same, it doesn't
-make sense to introduce another drivers.
-
-Add legacy_regs quirk and implement only VP9 changes for now. HEVC
-changes will be introduced later, if needed.
-
-Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h         |  2 +
- drivers/staging/media/hantro/hantro_g2_regs.h | 16 ++++
- .../staging/media/hantro/hantro_g2_vp9_dec.c  | 74 ++++++++++++++-----
- 3 files changed, 75 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index d03824fa3222..83ed25d9657b 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -74,6 +74,7 @@ struct hantro_irq {
-  * @reg_names:			array of register range names
-  * @num_regs:			number of register range names in the array
-  * @double_buffer:		core needs double buffering
-+ * @legacy_regs:		core uses legacy register set
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -96,6 +97,7 @@ struct hantro_variant {
- 	const char * const *reg_names;
- 	int num_regs;
- 	unsigned int double_buffer : 1;
-+	unsigned int legacy_regs : 1;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index 15a391a4650e..b7c6f9877b9d 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -36,7 +36,13 @@
- #define BUS_WIDTH_256			3
- 
- #define g2_strm_swap		G2_DEC_REG(2, 28, 0xf)
-+#define g2_strm_swap_old	G2_DEC_REG(2, 27, 0x1f)
-+#define g2_pic_swap		G2_DEC_REG(2, 22, 0x1f)
- #define g2_dirmv_swap		G2_DEC_REG(2, 20, 0xf)
-+#define g2_dirmv_swap_old	G2_DEC_REG(2, 17, 0x1f)
-+#define g2_tab0_swap_old	G2_DEC_REG(2, 12, 0x1f)
-+#define g2_tab1_swap_old	G2_DEC_REG(2, 7, 0x1f)
-+#define g2_tab2_swap_old	G2_DEC_REG(2, 2, 0x1f)
- 
- #define g2_mode			G2_DEC_REG(3, 27, 0x1f)
- #define g2_compress_swap	G2_DEC_REG(3, 20, 0xf)
-@@ -45,6 +51,8 @@
- #define g2_out_dis		G2_DEC_REG(3, 15, 0x1)
- #define g2_out_filtering_dis	G2_DEC_REG(3, 14, 0x1)
- #define g2_write_mvs_e		G2_DEC_REG(3, 12, 0x1)
-+#define g2_tab3_swap_old	G2_DEC_REG(3, 7, 0x1f)
-+#define g2_rscan_swap		G2_DEC_REG(3, 2, 0x1f)
- 
- #define g2_pic_width_in_cbs	G2_DEC_REG(4, 19, 0x1fff)
- #define g2_pic_height_in_cbs	G2_DEC_REG(4, 6,  0x1fff)
-@@ -58,6 +66,7 @@
- #define g2_tempor_mvp_e		G2_DEC_REG(5, 11, 0x1)
- #define g2_max_cu_qpd_depth	G2_DEC_REG(5, 5,  0x3f)
- #define g2_cu_qpd_e		G2_DEC_REG(5, 4,  0x1)
-+#define g2_pix_shift		G2_DEC_REG(5, 0,  0xf)
- 
- #define g2_stream_len		G2_DEC_REG(6, 0,  0xffffffff)
- 
-@@ -80,21 +89,28 @@
- 
- #define g2_const_intra_e	G2_DEC_REG(8, 31, 0x1)
- #define g2_filt_ctrl_pres	G2_DEC_REG(8, 30, 0x1)
-+#define g2_bit_depth_y		G2_DEC_REG(8, 21, 0xf)
-+#define g2_bit_depth_c		G2_DEC_REG(8, 17, 0xf)
- #define g2_idr_pic_e		G2_DEC_REG(8, 16, 0x1)
- #define g2_bit_depth_pcm_y	G2_DEC_REG(8, 12, 0xf)
- #define g2_bit_depth_pcm_c	G2_DEC_REG(8, 8,  0xf)
- #define g2_bit_depth_y_minus8	G2_DEC_REG(8, 6,  0x3)
- #define g2_bit_depth_c_minus8	G2_DEC_REG(8, 4,  0x3)
-+#define g2_rs_out_bit_depth	G2_DEC_REG(8, 4,  0xf)
- #define g2_output_8_bits	G2_DEC_REG(8, 3,  0x1)
- #define g2_output_format	G2_DEC_REG(8, 0,  0x7)
-+#define g2_pp_pix_shift		G2_DEC_REG(8, 0,  0xf)
- 
- #define g2_refidx1_active	G2_DEC_REG(9, 19, 0x1f)
- #define g2_refidx0_active	G2_DEC_REG(9, 14, 0x1f)
- #define g2_hdr_skip_length	G2_DEC_REG(9, 0,  0x3fff)
- 
- #define g2_start_code_e		G2_DEC_REG(10, 31, 0x1)
-+#define g2_init_qp_old		G2_DEC_REG(10, 25, 0x3f)
- #define g2_init_qp		G2_DEC_REG(10, 24, 0x3f)
-+#define g2_num_tile_cols_old	G2_DEC_REG(10, 20, 0x1f)
- #define g2_num_tile_cols	G2_DEC_REG(10, 19, 0x1f)
-+#define g2_num_tile_rows_old	G2_DEC_REG(10, 15, 0x1f)
- #define g2_num_tile_rows	G2_DEC_REG(10, 14, 0x1f)
- #define g2_tile_e		G2_DEC_REG(10, 1,  0x1)
- #define g2_entropy_sync_e	G2_DEC_REG(10, 0,  0x1)
-diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-index d4fc649a4da1..91c21b634fab 100644
---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-@@ -150,7 +150,8 @@ static void config_output(struct hantro_ctx *ctx,
- 	dma_addr_t luma_addr, chroma_addr, mv_addr;
- 
- 	hantro_reg_write(ctx->dev, &g2_out_dis, 0);
--	hantro_reg_write(ctx->dev, &g2_output_format, 0);
-+	if (!ctx->dev->variant->legacy_regs)
-+		hantro_reg_write(ctx->dev, &g2_output_format, 0);
- 
- 	luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
- 	hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr);
-@@ -327,6 +328,7 @@ config_tiles(struct hantro_ctx *ctx,
- 	struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge;
- 	dma_addr_t addr;
- 	unsigned short *tile_mem;
-+	unsigned int rows, cols;
- 
- 	addr = misc->dma + vp9_ctx->tile_info_offset;
- 	hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr);
-@@ -344,17 +346,24 @@ config_tiles(struct hantro_ctx *ctx,
- 
- 		fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem);
- 
-+		cols = tile_c;
-+		rows = tile_r;
- 		hantro_reg_write(ctx->dev, &g2_tile_e, 1);
--		hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c);
--		hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r);
--
- 	} else {
- 		tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width);
- 		tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height);
- 
-+		cols = 1;
-+		rows = 1;
- 		hantro_reg_write(ctx->dev, &g2_tile_e, 0);
--		hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1);
--		hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1);
-+	}
-+
-+	if (ctx->dev->variant->legacy_regs) {
-+		hantro_reg_write(ctx->dev, &g2_num_tile_cols_old, cols);
-+		hantro_reg_write(ctx->dev, &g2_num_tile_rows_old, rows);
-+	} else {
-+		hantro_reg_write(ctx->dev, &g2_num_tile_cols, cols);
-+		hantro_reg_write(ctx->dev, &g2_num_tile_rows, rows);
- 	}
- 
- 	/* provide aux buffers even if no tiles are used */
-@@ -505,8 +514,22 @@ static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_deco
- static void
- config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)
- {
--	hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8);
--	hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8);
-+	if (ctx->dev->variant->legacy_regs) {
-+		u8 pp_shift = 0;
-+
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth);
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth);
-+		hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth);
-+
-+		if (dec_params->bit_depth > 8)
-+			pp_shift = 16 - dec_params->bit_depth;
-+
-+		hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift);
-+		hantro_reg_write(ctx->dev, &g2_pix_shift, 0);
-+	} else {
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8);
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8);
-+	}
- }
- 
- static inline bool is_lossless(const struct v4l2_vp9_quantization *quant)
-@@ -784,9 +807,13 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para
- 		     + dec_params->compressed_header_size;
- 
- 	stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0);
--	hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base);
- 
- 	tmp_addr = stream_base + headres_size;
-+	if (ctx->dev->variant->legacy_regs)
-+		hantro_write_addr(ctx->dev, G2_STREAM_ADDR, (tmp_addr & ~0xf));
-+	else
-+		hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base);
-+
- 	start_bit = (tmp_addr & 0xf) * 8;
- 	hantro_reg_write(ctx->dev, &g2_start_bit, start_bit);
- 
-@@ -794,10 +821,12 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para
- 	src_len += start_bit / 8 - headres_size;
- 	hantro_reg_write(ctx->dev, &g2_stream_len, src_len);
- 
--	tmp_addr &= ~0xf;
--	hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base);
--	src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0);
--	hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len);
-+	if (!ctx->dev->variant->legacy_regs) {
-+		tmp_addr &= ~0xf;
-+		hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base);
-+		src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0);
-+		hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len);
-+	}
- }
- 
- static void
-@@ -837,13 +866,24 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p
- 
- 	/* configure basic registers */
- 	hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE);
--	hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf);
--	hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf);
--	hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf);
-+	if (!ctx->dev->variant->legacy_regs) {
-+		hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf);
-+		hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf);
-+		hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf);
-+		hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1);
-+	} else {
-+		hantro_reg_write(ctx->dev, &g2_strm_swap_old, 0x1f);
-+		hantro_reg_write(ctx->dev, &g2_pic_swap, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_dirmv_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab0_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab1_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab2_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab3_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_rscan_swap, 0x10);
-+	}
- 	hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128);
- 	hantro_reg_write(ctx->dev, &g2_max_burst, 16);
- 	hantro_reg_write(ctx->dev, &g2_apf_threshold, 8);
--	hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1);
- 	hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1);
- 	hantro_reg_write(ctx->dev, &g2_max_cb_size, 6);
- 	hantro_reg_write(ctx->dev, &g2_min_cb_size, 3);

projects/Allwinner/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch

@@ -1,62 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Mon, 22 Nov 2021 18:33:14 +0100
-Subject: [PATCH] media: hantro: move postproc enablement for old cores
-
-Older G2 cores, like that in Allwinner H6, seem to have issue with
-latching postproc register values if this is first thing done in job.
-Moving that to the end solves the issue.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h     | 2 ++
- drivers/staging/media/hantro/hantro_drv.c | 9 ++++++++-
- 2 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index 83ed25d9657b..06d0f3597694 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -75,6 +75,7 @@ struct hantro_irq {
-  * @num_regs:			number of register range names in the array
-  * @double_buffer:		core needs double buffering
-  * @legacy_regs:		core uses legacy register set
-+ * @late_postproc:		postproc must be set up at the end of the job
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -98,6 +99,7 @@ struct hantro_variant {
- 	int num_regs;
- 	unsigned int double_buffer : 1;
- 	unsigned int legacy_regs : 1;
-+	unsigned int late_postproc : 1;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
-index 770f4ce71d29..33bf78be145b 100644
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -130,7 +130,7 @@ void hantro_start_prepare_run(struct hantro_ctx *ctx)
- 	v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
- 				&ctx->ctrl_handler);
- 
--	if (!ctx->is_encoder) {
-+	if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) {
- 		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
- 			hantro_postproc_enable(ctx);
- 		else
-@@ -142,6 +142,13 @@ void hantro_end_prepare_run(struct hantro_ctx *ctx)
- {
- 	struct vb2_v4l2_buffer *src_buf;
- 
-+	if (!ctx->is_encoder && ctx->dev->variant->late_postproc) {
-+		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
-+			hantro_postproc_enable(ctx);
-+		else
-+			hantro_postproc_disable(ctx);
-+	}
-+
- 	src_buf = hantro_get_src_buf(ctx);
- 	v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
- 				   &ctx->ctrl_handler);

projects/Allwinner/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch

@@ -1,92 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Mon, 29 Nov 2021 19:02:17 +0100
-Subject: [PATCH] media: hantro: Convert imx8m_vpu_g2_irq to helper
-
-It turns out that imx8m_vpu_g2_irq() doesn't depend on any platform
-specifics and can be used with other G2 platform drivers too.
-
-Move it to common code.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro_g2.c    | 18 ++++++++++++++++++
- drivers/staging/media/hantro/hantro_hw.h    |  1 +
- drivers/staging/media/hantro/imx8m_vpu_hw.c | 20 +-------------------
- 3 files changed, 20 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c
-index 6f3e1f797f83..ee5f14c5f8f2 100644
---- a/drivers/staging/media/hantro/hantro_g2.c
-+++ b/drivers/staging/media/hantro/hantro_g2.c
-@@ -24,3 +24,21 @@ void hantro_g2_check_idle(struct hantro_dev *vpu)
- 		}
- 	}
- }
-+
-+irqreturn_t hantro_g2_irq(int irq, void *dev_id)
-+{
-+	struct hantro_dev *vpu = dev_id;
-+	enum vb2_buffer_state state;
-+	u32 status;
-+
-+	status = vdpu_read(vpu, G2_REG_INTERRUPT);
-+	state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ?
-+		 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
-+
-+	vdpu_write(vpu, 0, G2_REG_INTERRUPT);
-+	vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG);
-+
-+	hantro_irq_done(vpu, state);
-+
-+	return IRQ_HANDLED;
-+}
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index dbe51303724b..c33b1f5df37b 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -413,5 +413,6 @@ void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx);
- int hantro_vp9_dec_init(struct hantro_ctx *ctx);
- void hantro_vp9_dec_exit(struct hantro_ctx *ctx);
- void hantro_g2_check_idle(struct hantro_dev *vpu);
-+irqreturn_t hantro_g2_irq(int irq, void *dev_id);
- 
- #endif /* HANTRO_HW_H_ */
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 1a43f6fceef9..f5991b8e553a 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -191,24 +191,6 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
- 	return IRQ_HANDLED;
- }
- 
--static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id)
--{
--	struct hantro_dev *vpu = dev_id;
--	enum vb2_buffer_state state;
--	u32 status;
--
--	status = vdpu_read(vpu, G2_REG_INTERRUPT);
--	state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ?
--		 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
--
--	vdpu_write(vpu, 0, G2_REG_INTERRUPT);
--	vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG);
--
--	hantro_irq_done(vpu, state);
--
--	return IRQ_HANDLED;
--}
--
- static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
- {
- 	vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];
-@@ -280,7 +262,7 @@ static const struct hantro_irq imx8mq_irqs[] = {
- };
- 
- static const struct hantro_irq imx8mq_g2_irqs[] = {
--	{ "g2", imx8m_vpu_g2_irq },
-+	{ "g2", hantro_g2_irq },
- };
- 
- static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };

projects/Allwinner/patches/linux/0085-media-hantro-Add-support-for-Allwinner-H6.patch

@@ -1,172 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Thu, 5 Aug 2021 20:43:03 +0200
-Subject: [PATCH] media: hantro: Add support for Allwinner H6
-
-Allwinner H6 has a Hantro G2 core used for VP9 decoding. It's not clear
-at this time if HEVC is also supported or not.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/Kconfig        | 10 ++-
- drivers/staging/media/hantro/Makefile       |  3 +
- drivers/staging/media/hantro/hantro_drv.c   |  3 +
- drivers/staging/media/hantro/hantro_hw.h    |  1 +
- drivers/staging/media/hantro/sunxi_vpu_hw.c | 86 +++++++++++++++++++++
- 5 files changed, 102 insertions(+), 1 deletion(-)
- create mode 100644 drivers/staging/media/hantro/sunxi_vpu_hw.c
-
-diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig
-index 00a57d88c92e..3c5d833322c8 100644
---- a/drivers/staging/media/hantro/Kconfig
-+++ b/drivers/staging/media/hantro/Kconfig
-@@ -1,7 +1,7 @@
- # SPDX-License-Identifier: GPL-2.0
- config VIDEO_HANTRO
- 	tristate "Hantro VPU driver"
--	depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || COMPILE_TEST
-+	depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST
- 	depends on VIDEO_DEV && VIDEO_V4L2
- 	select MEDIA_CONTROLLER
- 	select MEDIA_CONTROLLER_REQUEST_API
-@@ -40,3 +40,11 @@ config VIDEO_HANTRO_ROCKCHIP
- 	default y
- 	help
- 	  Enable support for RK3288, RK3328, and RK3399 SoCs.
-+
-+config VIDEO_HANTRO_SUNXI
-+	bool "Hantro VPU Allwinner support"
-+	depends on VIDEO_HANTRO
-+	depends on ARCH_SUNXI || COMPILE_TEST
-+	default y
-+	help
-+	  Enable support for H6 SoC.
-diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile
-index 28af0a1ee4bf..ebd5ede7bef7 100644
---- a/drivers/staging/media/hantro/Makefile
-+++ b/drivers/staging/media/hantro/Makefile
-@@ -33,3 +33,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \
- 
- hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
- 		rockchip_vpu_hw.o
-+
-+hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \
-+		sunxi_vpu_hw.o
-diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
-index 33bf78be145b..6a51f39dde56 100644
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -620,6 +620,9 @@ static const struct of_device_id of_hantro_match[] = {
- #endif
- #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
- 	{ .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
-+#endif
-+#ifdef CONFIG_VIDEO_HANTRO_SUNXI
-+	{ .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, },
- #endif
- 	{ /* sentinel */ }
- };
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index c33b1f5df37b..c92a6ec4b187 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -308,6 +308,7 @@ extern const struct hantro_variant rk3288_vpu_variant;
- extern const struct hantro_variant rk3328_vpu_variant;
- extern const struct hantro_variant rk3399_vpu_variant;
- extern const struct hantro_variant sama5d4_vdec_variant;
-+extern const struct hantro_variant sunxi_vpu_variant;
- 
- extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
- extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
-diff --git a/drivers/staging/media/hantro/sunxi_vpu_hw.c b/drivers/staging/media/hantro/sunxi_vpu_hw.c
-new file mode 100644
-index 000000000000..90633406c4eb
---- /dev/null
-+++ b/drivers/staging/media/hantro/sunxi_vpu_hw.c
-@@ -0,0 +1,86 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Allwinner Hantro G2 VPU codec driver
-+ *
-+ * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
-+ */
-+
-+#include <linux/clk.h>
-+
-+#include "hantro.h"
-+
-+static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = {
-+	{
-+		.fourcc = V4L2_PIX_FMT_NV12,
-+		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
-+	},
-+};
-+
-+static const struct hantro_fmt sunxi_vpu_dec_fmts[] = {
-+	{
-+		.fourcc = V4L2_PIX_FMT_NV12_4L4,
-+		.codec_mode = HANTRO_MODE_NONE,
-+	},
-+	{
-+		.fourcc = V4L2_PIX_FMT_VP9_FRAME,
-+		.codec_mode = HANTRO_MODE_VP9_DEC,
-+		.max_depth = 2,
-+		.frmsize = {
-+			.min_width = 48,
-+			.max_width = 3840,
-+			.step_width = MB_DIM,
-+			.min_height = 48,
-+			.max_height = 2160,
-+			.step_height = MB_DIM,
-+		},
-+	},
-+};
-+
-+static int sunxi_vpu_hw_init(struct hantro_dev *vpu)
-+{
-+	clk_set_rate(vpu->clocks[0].clk, 300000000);
-+
-+	return 0;
-+}
-+
-+static void sunxi_vpu_reset(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+
-+	reset_control_reset(vpu->resets);
-+}
-+
-+static const struct hantro_codec_ops sunxi_vpu_codec_ops[] = {
-+	[HANTRO_MODE_VP9_DEC] = {
-+		.run = hantro_g2_vp9_dec_run,
-+		.done = hantro_g2_vp9_dec_done,
-+		.reset = sunxi_vpu_reset,
-+		.init = hantro_vp9_dec_init,
-+		.exit = hantro_vp9_dec_exit,
-+	},
-+};
-+
-+static const struct hantro_irq sunxi_irqs[] = {
-+	{ NULL, hantro_g2_irq },
-+};
-+
-+static const char * const sunxi_clk_names[] = { "mod", "bus" };
-+
-+const struct hantro_variant sunxi_vpu_variant = {
-+	.dec_fmts = sunxi_vpu_dec_fmts,
-+	.num_dec_fmts = ARRAY_SIZE(sunxi_vpu_dec_fmts),
-+	.postproc_fmts = sunxi_vpu_postproc_fmts,
-+	.num_postproc_fmts = ARRAY_SIZE(sunxi_vpu_postproc_fmts),
-+	.postproc_ops = &hantro_g2_postproc_ops,
-+	.codec = HANTRO_VP9_DECODER,
-+	.codec_ops = sunxi_vpu_codec_ops,
-+	.init = sunxi_vpu_hw_init,
-+	.irqs = sunxi_irqs,
-+	.num_irqs = ARRAY_SIZE(sunxi_irqs),
-+	.clk_names = sunxi_clk_names,
-+	.num_clocks = ARRAY_SIZE(sunxi_clk_names),
-+	.double_buffer = 1,
-+	.legacy_regs = 1,
-+	.late_postproc = 1,
-+};

projects/Allwinner/patches/linux/0086-arm64-dts-allwinner-h6-Add-Hantro-G2-node.patch

@@ -1,33 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Thu, 5 Aug 2021 22:32:38 +0200
-Subject: [PATCH] arm64: dts: allwinner: h6: Add Hantro G2 node
-
-H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly
-older design, though.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-index 4c4547f7d0c7..878061e75098 100644
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
-@@ -153,6 +153,15 @@ mixer0_out_tcon_top_mixer0: endpoint {
- 			};
- 		};
- 
-+		video-codec-g2@1c00000 {
-+			compatible = "allwinner,sun50i-h6-vpu-g2";
-+			reg = <0x01c00000 0x1000>;
-+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
-+			clock-names = "bus", "mod";
-+			resets = <&ccu RST_BUS_VP9>;
-+		};
-+
- 		video-codec@1c0e000 {
- 			compatible = "allwinner,sun50i-h6-video-engine";
- 			reg = <0x01c0e000 0x2000>;

projects/Allwinner/patches/linux/0091-media-hantro-Fix-G2-HEVC-negotiated-pixelformat.patch

@@ -1,301 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Date: Wed, 8 Dec 2021 17:44:18 +0100
-Subject: [PATCH] media: hantro: Fix G2/HEVC negotiated pixelformat
-
-G2/HEVC is broken because driver capture queue pixelformat ioctl G_FMT
-returns VT12 while G2/HEVC always generate NV12 frames:
-
-video1: VIDIOC_S_FMT: type=vid-out-mplane, width=2560, height=1600, format=S265 little-endian (0x35363253), field=none, colorspace=0, num_planes=1, flags=0x0, ycbcr_enc=0, quantization=0, xfer_func=0
-plane 0: bytesperline=0 sizeimage=6144000
-video1: VIDIOC_S_EXT_CTRLS: which=0x0, count=1, error_idx=0, request_fd=0, name=HEVC Sequence Parameter Set, id/size=0x990cf0/32
-video1: VIDIOC_G_FMT: type=vid-cap-mplane, width=2560, height=1600, format=VT12 little-endian (0x32315456), field=none, colorspace=0, num_planes=1, flags=0x0, ycbcr_enc=0, quantization=0, xfer_func=0
-plane 0: bytesperline=2560 sizeimage=6144000
-video1: VIDIOC_ENUM_FMT: index=0, type=vid-cap-mplane, flags=0x0, pixelformat=NV12 little-endian (0x3231564e), mbus_code=0x0000, description='Y/CbCr 4:2:0'
-video1: VIDIOC_ENUM_FMT: error -22: index=1, type=vid-cap-mplane, flags=0x0, pixelformat=.... little-endian (0x00000000), mbus_code=0x0000, description=''
-video1: VIDIOC_G_FMT: type=vid-cap-mplane, width=2560, height=1600, format=VT12 little-endian (0x32315456), field=none, colorspace=0, num_planes=1, flags=0x0, ycbcr_enc=0, quantization=0, xfer_func=0
-
-Use the postprocessor functions introduced by Hantro G2/VP9 codec series
-to fix the issue and remove duplicated buffer management.
-This allow Hantro G2/HEVC to produce NV12_4L4 and NV12.
-
-Fluster scores are 77/147 for HEVC and 129/303 for VP9 (no regression).
-
-Beauty, Jockey and ShakeNDry bitstreams from UVG (http://ultravideo.fi/)
-set have also been tested.
-
-Fixes: 53a3e71095c5 ("media: hantro: Simplify postprocessor")
-Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
----
- .../staging/media/hantro/hantro_g2_hevc_dec.c | 25 +++---
- drivers/staging/media/hantro/hantro_hevc.c    | 79 +++----------------
- drivers/staging/media/hantro/hantro_hw.h      | 11 +++
- .../staging/media/hantro/hantro_postproc.c    |  3 +
- drivers/staging/media/hantro/hantro_v4l2.c    | 19 ++---
- 5 files changed, 41 insertions(+), 96 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-index f62608b0b408..99d8ea7543da 100644
---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-@@ -354,6 +354,8 @@ static int set_ref(struct hantro_ctx *ctx)
- 	const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
- 	dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
- 	struct hantro_dev *vpu = ctx->dev;
-+	struct vb2_v4l2_buffer *vb2_dst;
-+	struct hantro_decoded_buffer *dst;
- 	size_t cr_offset = hantro_hevc_chroma_offset(sps);
- 	size_t mv_offset = hantro_hevc_motion_vectors_offset(sps);
- 	u32 max_ref_frames;
-@@ -439,10 +441,15 @@ static int set_ref(struct hantro_ctx *ctx)
- 		hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
- 	}
- 
--	luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val);
-+	vb2_dst = hantro_get_dst_buf(ctx);
-+	dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
-+	luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
- 	if (!luma_addr)
- 		return -ENOMEM;
- 
-+	if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr))
-+		return -EINVAL;
-+
- 	chroma_addr = luma_addr + cr_offset;
- 	mv_addr = luma_addr + mv_offset;
- 
-@@ -469,16 +476,12 @@ static int set_ref(struct hantro_ctx *ctx)
- 
- static void set_buffers(struct hantro_ctx *ctx)
- {
--	struct vb2_v4l2_buffer *src_buf, *dst_buf;
-+	struct vb2_v4l2_buffer *src_buf;
- 	struct hantro_dev *vpu = ctx->dev;
--	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
--	const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
--	size_t cr_offset = hantro_hevc_chroma_offset(sps);
--	dma_addr_t src_dma, dst_dma;
-+	dma_addr_t src_dma;
- 	u32 src_len, src_buf_len;
- 
- 	src_buf = hantro_get_src_buf(ctx);
--	dst_buf = hantro_get_dst_buf(ctx);
- 
- 	/* Source (stream) buffer. */
- 	src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
-@@ -491,11 +494,6 @@ static void set_buffers(struct hantro_ctx *ctx)
- 	hantro_reg_write(vpu, &g2_strm_start_offset, 0);
- 	hantro_reg_write(vpu, &g2_write_mvs_e, 1);
- 
--	/* Destination (decoded frame) buffer. */
--	dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf);
--
--	hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);
--	hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + cr_offset);
- 	hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);
- 	hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma);
- 	hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma);
-@@ -588,9 +586,6 @@ int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
- 	/* Don't compress buffers */
- 	hantro_reg_write(vpu, &g2_ref_compress_bypass, 1);
- 
--	/* use NV12 as output format */
--	hantro_reg_write(vpu, &g2_out_rs_e, 1);
--
- 	/* Bus width and max burst */
- 	hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128);
- 	hantro_reg_write(vpu, &g2_max_burst, 16);
-diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c
-index ee03123e7704..b49a41d7ae91 100644
---- a/drivers/staging/media/hantro/hantro_hevc.c
-+++ b/drivers/staging/media/hantro/hantro_hevc.c
-@@ -44,47 +44,6 @@ size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps)
- 	return ALIGN((cr_offset * 3) / 2, G2_ALIGN);
- }
- 
--static size_t hantro_hevc_mv_size(const struct v4l2_ctrl_hevc_sps *sps)
--{
--	u32 min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
--	u32 ctb_log2_size_y = min_cb_log2_size_y + sps->log2_diff_max_min_luma_coding_block_size;
--	u32 pic_width_in_ctbs_y = (sps->pic_width_in_luma_samples + (1 << ctb_log2_size_y) - 1)
--				  >> ctb_log2_size_y;
--	u32 pic_height_in_ctbs_y = (sps->pic_height_in_luma_samples + (1 << ctb_log2_size_y) - 1)
--				   >> ctb_log2_size_y;
--	size_t mv_size;
--
--	mv_size = pic_width_in_ctbs_y * pic_height_in_ctbs_y *
--		  (1 << (2 * (ctb_log2_size_y - 4))) * 16;
--
--	vpu_debug(4, "%dx%d (CTBs) %zu MV bytes\n",
--		  pic_width_in_ctbs_y, pic_height_in_ctbs_y, mv_size);
--
--	return mv_size;
--}
--
--static size_t hantro_hevc_ref_size(struct hantro_ctx *ctx)
--{
--	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
--	const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
--
--	return hantro_hevc_motion_vectors_offset(sps) + hantro_hevc_mv_size(sps);
--}
--
--static void hantro_hevc_ref_free(struct hantro_ctx *ctx)
--{
--	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
--	struct hantro_dev *vpu = ctx->dev;
--	int i;
--
--	for (i = 0;  i < NUM_REF_PICTURES; i++) {
--		if (hevc_dec->ref_bufs[i].cpu)
--			dma_free_coherent(vpu->dev, hevc_dec->ref_bufs[i].size,
--					  hevc_dec->ref_bufs[i].cpu,
--					  hevc_dec->ref_bufs[i].dma);
--	}
--}
--
- static void hantro_hevc_ref_init(struct hantro_ctx *ctx)
- {
- 	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
-@@ -108,37 +67,25 @@ dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx,
- 		}
- 	}
- 
--	/* Allocate a new reference buffer */
-+	return 0;
-+}
-+
-+int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr)
-+{
-+	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
-+	int i;
-+
-+	/* Add a new reference buffer */
- 	for (i = 0; i < NUM_REF_PICTURES; i++) {
- 		if (hevc_dec->ref_bufs_poc[i] == UNUSED_REF) {
--			if (!hevc_dec->ref_bufs[i].cpu) {
--				struct hantro_dev *vpu = ctx->dev;
--
--				/*
--				 * Allocate the space needed for the raw data +
--				 * motion vector data. Optimizations could be to
--				 * allocate raw data in non coherent memory and only
--				 * clear the motion vector data.
--				 */
--				hevc_dec->ref_bufs[i].cpu =
--					dma_alloc_coherent(vpu->dev,
--							   hantro_hevc_ref_size(ctx),
--							   &hevc_dec->ref_bufs[i].dma,
--							   GFP_KERNEL);
--				if (!hevc_dec->ref_bufs[i].cpu)
--					return 0;
--
--				hevc_dec->ref_bufs[i].size = hantro_hevc_ref_size(ctx);
--			}
- 			hevc_dec->ref_bufs_used |= 1 << i;
--			memset(hevc_dec->ref_bufs[i].cpu, 0, hantro_hevc_ref_size(ctx));
- 			hevc_dec->ref_bufs_poc[i] = poc;
--
--			return hevc_dec->ref_bufs[i].dma;
-+			hevc_dec->ref_bufs[i].dma = addr;
-+			return 0;
- 		}
- 	}
- 
--	return 0;
-+	return -EINVAL;
- }
- 
- void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx)
-@@ -314,8 +261,6 @@ void hantro_hevc_dec_exit(struct hantro_ctx *ctx)
- 				  hevc_dec->tile_bsd.cpu,
- 				  hevc_dec->tile_bsd.dma);
- 	hevc_dec->tile_bsd.cpu = NULL;
--
--	hantro_hevc_ref_free(ctx);
- }
- 
- int hantro_hevc_dec_init(struct hantro_ctx *ctx)
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index cff817ca8d22..a018748fc4bf 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -346,6 +346,7 @@ void hantro_hevc_dec_exit(struct hantro_ctx *ctx);
- int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
- int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
- dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, int poc);
-+int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr);
- void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx);
- size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps);
- size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps);
-@@ -395,6 +396,16 @@ hantro_h264_mv_size(unsigned int width, unsigned int height)
- 	return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
- }
- 
-+static inline size_t
-+hantro_hevc_mv_size(unsigned int width, unsigned int height)
-+{
-+	/*
-+	 * A CTB can be 64x64, 32x32 or 16x16.
-+	 * Allocated memory for the "worse" case: 16x16
-+	 */
-+	return width * height / 16;
-+}
-+
- int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
- int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);
- void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index a7774ad4c445..248abe5423f0 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -146,6 +146,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)
- 	else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME)
- 		buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width,
- 					       ctx->dst_fmt.height);
-+	else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE)
-+		buf_size += hantro_hevc_mv_size(ctx->dst_fmt.width,
-+						ctx->dst_fmt.height);
- 
- 	for (i = 0; i < num_buffers; ++i) {
- 		struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
-diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
-index c319f0e5fe60..e595905b3bd7 100644
---- a/drivers/staging/media/hantro/hantro_v4l2.c
-+++ b/drivers/staging/media/hantro/hantro_v4l2.c
-@@ -148,20 +148,6 @@ static int vidioc_enum_fmt(struct file *file, void *priv,
- 	unsigned int num_fmts, i, j = 0;
- 	bool skip_mode_none;
- 
--	/*
--	 * The HEVC decoder on the G2 core needs a little quirk to offer NV12
--	 * only on the capture side. Once the post-processor logic is used,
--	 * we will be able to expose NV12_4L4 and NV12 as the other cases,
--	 * and therefore remove this quirk.
--	 */
--	if (capture && ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) {
--		if (f->index == 0) {
--			f->pixelformat = V4L2_PIX_FMT_NV12;
--			return 0;
--		}
--		return -EINVAL;
--	}
--
- 	/*
- 	 * When dealing with an encoder:
- 	 *  - on the capture side we want to filter out all MODE_NONE formats.
-@@ -302,6 +288,11 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx,
- 			pix_mp->plane_fmt[0].sizeimage +=
- 				hantro_vp9_mv_size(pix_mp->width,
- 						   pix_mp->height);
-+		else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE &&
-+			 !hantro_needs_postproc(ctx, fmt))
-+			pix_mp->plane_fmt[0].sizeimage +=
-+				hantro_hevc_mv_size(pix_mp->width,
-+						    pix_mp->height);
- 	} else if (!pix_mp->plane_fmt[0].sizeimage) {
- 		/*
- 		 * For coded formats the application can specify

projects/Generic/linux/linux.x86_64.conf

@@ -1,15 +1,15 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/x86 5.16.0-rc8 Kernel Configuration
+# Linux/x86 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.3.0 (GCC) 10.3.0"
 CONFIG_CC_IS_GCC=y
 CONFIG_GCC_VERSION=100300
 CONFIG_CLANG_VERSION=0
 CONFIG_AS_IS_GNU=y
-CONFIG_AS_VERSION=23501
+CONFIG_AS_VERSION=23700
 CONFIG_LD_IS_BFD=y
-CONFIG_LD_VERSION=23501
+CONFIG_LD_VERSION=23700
 CONFIG_LLD_VERSION=0
 CONFIG_CC_CAN_LINK=y
 CONFIG_CC_CAN_LINK_STATIC=y
@@ -304,9 +304,6 @@ CONFIG_ARCH_MAY_HAVE_PC_FDC=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_ARCH_HAS_CPU_RELAX=y
 CONFIG_ARCH_HAS_FILTER_PGPROT=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_NR_GPIO=1024
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
@@ -475,7 +472,6 @@ CONFIG_HAVE_LIVEPATCH=y
 
 CONFIG_ARCH_HAS_ADD_PAGES=y
 CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_USE_PERCPU_NUMA_NODE_ID=y
 
 #
 # Power management and ACPI options
@@ -546,6 +542,8 @@ CONFIG_HAVE_ACPI_APEI_NMI=y
 # CONFIG_ACPI_APEI is not set
 # CONFIG_ACPI_DPTF is not set
 # CONFIG_ACPI_CONFIGFS is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_PCC=y
 # CONFIG_PMIC_OPREGION is not set
 CONFIG_X86_PM_TIMER=y
 CONFIG_ACPI_PRMT=y
@@ -573,6 +571,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
 #
 CONFIG_X86_INTEL_PSTATE=y
 CONFIG_X86_PCC_CPUFREQ=m
+# CONFIG_X86_AMD_PSTATE is not set
 CONFIG_X86_ACPI_CPUFREQ=y
 CONFIG_X86_ACPI_CPUFREQ_CPB=y
 CONFIG_X86_POWERNOW_K8=y
@@ -720,6 +719,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
 CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_HAVE_STACK_VALIDATION=y
 CONFIG_HAVE_RELIABLE_STACKTRACE=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -742,6 +742,7 @@ CONFIG_HAVE_STATIC_CALL_INLINE=y
 CONFIG_HAVE_PREEMPT_DYNAMIC=y
 CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
 CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
 CONFIG_ARCH_HAS_ELFCORE_COMPAT=y
 CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
 CONFIG_DYNAMIC_SIGFRAME=y
@@ -776,6 +777,7 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe"
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_BLOCK=y
 CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_ICQ=y
 CONFIG_BLK_DEV_BSGLIB=y
 # CONFIG_BLK_DEV_INTEGRITY is not set
 # CONFIG_BLK_DEV_ZONED is not set
@@ -892,13 +894,16 @@ CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
 CONFIG_ARCH_WANTS_THP_SWAP=y
 CONFIG_THP_SWAP=y
-CONFIG_CLEANCACHE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-# CONFIG_FRONTSWAP is not set
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
 # CONFIG_CMA_SYSFS is not set
 CONFIG_CMA_AREAS=19
+# CONFIG_ZSWAP is not set
 # CONFIG_ZPOOL is not set
 # CONFIG_ZSMALLOC is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y
@@ -919,6 +924,7 @@ CONFIG_ARCH_HAS_PKEYS=y
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 CONFIG_MAPPING_DIRTY_HELPERS=y
 CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1359,6 +1365,7 @@ CONFIG_BT_INTEL=m
 CONFIG_BT_BCM=m
 CONFIG_BT_RTL=m
 CONFIG_BT_QCA=m
+CONFIG_BT_MTK=m
 CONFIG_BT_HCIBTUSB=m
 CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
 CONFIG_BT_HCIBTUSB_BCM=y
@@ -1531,6 +1538,7 @@ CONFIG_AUXILIARY_BUS=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 
@@ -1643,7 +1651,6 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
 # CONFIG_ATA_OVER_ETH is not set
 CONFIG_VIRTIO_BLK=y
 # CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
 
 #
 # NVME Support
@@ -1789,7 +1796,6 @@ CONFIG_MEGARAID_SAS=y
 # CONFIG_SCSI_MPI3MR is not set
 # CONFIG_SCSI_SMARTPQI is not set
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_UFS_HWMON is not set
 # CONFIG_SCSI_HPTIOP is not set
 # CONFIG_SCSI_BUSLOGIC is not set
 # CONFIG_SCSI_MYRB is not set
@@ -2021,6 +2027,7 @@ CONFIG_NET_TULIP=y
 CONFIG_ULI526X=y
 # CONFIG_NET_VENDOR_DLINK is not set
 # CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 CONFIG_NET_VENDOR_EZCHIP=y
 # CONFIG_NET_VENDOR_GOOGLE is not set
 # CONFIG_NET_VENDOR_HUAWEI is not set
@@ -2040,6 +2047,7 @@ CONFIG_IXGBE_HWMON=y
 # CONFIG_I40E is not set
 # CONFIG_I40EVF is not set
 CONFIG_ICE=y
+CONFIG_ICE_HWTS=y
 # CONFIG_FM10K is not set
 CONFIG_IGC=y
 CONFIG_NET_VENDOR_MICROSOFT=y
@@ -2102,6 +2110,7 @@ CONFIG_NET_VENDOR_SYNOPSYS=y
 # CONFIG_DWC_XLGMAC is not set
 # CONFIG_NET_VENDOR_TEHUTI is not set
 # CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 CONFIG_NET_VENDOR_VIA=y
 CONFIG_VIA_RHINE=y
 # CONFIG_VIA_RHINE_MMIO is not set
@@ -2172,7 +2181,6 @@ CONFIG_MDIO_DEVRES=y
 # CONFIG_MDIO_BITBANG is not set
 # CONFIG_MDIO_BCM_UNIMAC is not set
 # CONFIG_MDIO_MVUSB is not set
-# CONFIG_MDIO_MSCC_MIIM is not set
 # CONFIG_MDIO_THUNDER is not set
 
 #
@@ -2766,6 +2774,7 @@ CONFIG_SERIAL_8250_DW=y
 # CONFIG_SERIAL_8250_RT288X is not set
 # CONFIG_SERIAL_8250_LPSS is not set
 CONFIG_SERIAL_8250_MID=y
+# CONFIG_SERIAL_8250_PERICOM is not set
 
 #
 # Non-8250 serial port support
@@ -3055,6 +3064,7 @@ CONFIG_GPIO_CDEV_V1=y
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
 # CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -3081,6 +3091,7 @@ CONFIG_POWER_SUPPLY_HWMON=y
 # CONFIG_CHARGER_MANAGER is not set
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24257 is not set
 # CONFIG_CHARGER_BQ24735 is not set
@@ -3195,12 +3206,12 @@ CONFIG_SENSORS_JC42=m
 # CONFIG_SENSORS_LM95245 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_NTC_THERMISTOR is not set
 # CONFIG_SENSORS_NCT6683 is not set
 # CONFIG_SENSORS_NCT6775 is not set
 # CONFIG_SENSORS_NCT7802 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
 # CONFIG_SENSORS_SBTSI is not set
@@ -3225,6 +3236,7 @@ CONFIG_SENSORS_JC42=m
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 # CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -3255,6 +3267,8 @@ CONFIG_SENSORS_W83627EHF=y
 #
 # CONFIG_SENSORS_ACPI_POWER is not set
 CONFIG_SENSORS_ATK0110=m
+# CONFIG_SENSORS_ASUS_WMI is not set
+# CONFIG_SENSORS_ASUS_WMI_EC is not set
 CONFIG_THERMAL=y
 # CONFIG_THERMAL_NETLINK is not set
 CONFIG_THERMAL_STATISTICS=y
@@ -3343,7 +3357,6 @@ CONFIG_MFD_INTEL_LPSS=y
 CONFIG_MFD_INTEL_LPSS_ACPI=y
 CONFIG_MFD_INTEL_LPSS_PCI=y
 # CONFIG_MFD_INTEL_PMC_BXT is not set
-# CONFIG_MFD_INTEL_PMT is not set
 # CONFIG_MFD_IQS62X is not set
 # CONFIG_MFD_JANZ_CMODIO is not set
 # CONFIG_MFD_KEMPLD is not set
@@ -3426,6 +3439,7 @@ CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_MAX8660 is not set
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MP8859 is not set
 # CONFIG_REGULATOR_MT6311 is not set
@@ -3920,6 +3934,7 @@ CONFIG_SDR_MAX2175=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -4334,6 +4349,7 @@ CONFIG_DRM_PANEL_BRIDGE=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -4552,6 +4568,7 @@ CONFIG_SND_HDA_RECONFIG=y
 CONFIG_SND_HDA_INPUT_BEEP=y
 CONFIG_SND_HDA_INPUT_BEEP_MODE=1
 CONFIG_SND_HDA_PATCH_LOADER=y
+# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
 CONFIG_SND_HDA_CODEC_REALTEK=m
 CONFIG_SND_HDA_CODEC_ANALOG=m
 CONFIG_SND_HDA_CODEC_SIGMATEL=m
@@ -4618,6 +4635,7 @@ CONFIG_SND_SOC_AMD_RENOIR=m
 CONFIG_SND_SOC_AMD_RENOIR_MACH=m
 # CONFIG_SND_SOC_AMD_ACP5x is not set
 # CONFIG_SND_SOC_AMD_ACP6x is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_SOC_AMD_ACP_COMMON is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
@@ -4710,6 +4728,7 @@ CONFIG_SND_SOC_ADAU7002=m
 # CONFIG_SND_SOC_ADAU7118_HW is not set
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 # CONFIG_SND_SOC_AK4613 is not set
@@ -4805,6 +4824,7 @@ CONFIG_SND_SOC_SPDIF=m
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
 # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
@@ -4920,6 +4940,7 @@ CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LCPOWER=y
 # CONFIG_HID_LED is not set
 CONFIG_HID_LENOVO=y
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 CONFIG_HID_LOGITECH_DJ=y
 CONFIG_HID_LOGITECH_HIDPP=y
@@ -5322,6 +5343,10 @@ CONFIG_LEDS_TRIGGERS=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 CONFIG_LEDS_TRIGGER_AUDIO=m
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_ATOMIC_SCRUB=y
@@ -5547,6 +5572,7 @@ CONFIG_WMI_BMOF=y
 # CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
 # CONFIG_XIAOMI_WMI is not set
 # CONFIG_GIGABYTE_WMI is not set
+# CONFIG_YOGABOOK_WMI is not set
 # CONFIG_ACERHDF is not set
 # CONFIG_ACER_WIRELESS is not set
 # CONFIG_ACER_WMI is not set
@@ -5555,6 +5581,7 @@ CONFIG_WMI_BMOF=y
 # CONFIG_APPLE_GMUX is not set
 # CONFIG_ASUS_LAPTOP is not set
 # CONFIG_ASUS_WIRELESS is not set
+# CONFIG_ASUS_TF103C_DOCK is not set
 # CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
 # CONFIG_AMILO_RFKILL is not set
 # CONFIG_FUJITSU_LAPTOP is not set
@@ -5591,6 +5618,7 @@ CONFIG_INTEL_ATOMISP2_PM=y
 # CONFIG_INTEL_SMARTCONNECT is not set
 # CONFIG_INTEL_TURBO_MAX_3 is not set
 # CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set
+# CONFIG_INTEL_VSEC is not set
 # CONFIG_MSI_LAPTOP is not set
 # CONFIG_MSI_WMI is not set
 # CONFIG_PCENGINES_APU2 is not set
@@ -5609,9 +5637,11 @@ CONFIG_INTEL_ATOMISP2_PM=y
 # CONFIG_TOPSTAR_LAPTOP is not set
 # CONFIG_I2C_MULTI_INSTANTIATE is not set
 # CONFIG_MLX_PLATFORM is not set
+# CONFIG_X86_ANDROID_TABLETS is not set
 # CONFIG_INTEL_IPS is not set
 # CONFIG_INTEL_SCU_PCI is not set
 # CONFIG_INTEL_SCU_PLATFORM is not set
+# CONFIG_SIEMENS_SIMATIC_IPC is not set
 CONFIG_PMC_ATOM=y
 # CONFIG_CHROME_PLATFORMS is not set
 # CONFIG_MELLANOX_PLATFORM is not set
@@ -5630,6 +5660,7 @@ CONFIG_COMMON_CLK=y
 # CONFIG_COMMON_CLK_SI544 is not set
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
 # CONFIG_XILINX_VCU is not set
 # CONFIG_HWSPINLOCK is not set
 
@@ -6295,6 +6326,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6302,28 +6334,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
 CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
 # CONFIG_CRYPTO_HW is not set
 CONFIG_ASYMMETRIC_KEY_TYPE=y
 CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
@@ -6356,7 +6366,6 @@ CONFIG_BITREVERSE=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 # CONFIG_CORDIC is not set
 # CONFIG_PRIME_NUMBERS is not set
 CONFIG_RATIONAL=y
@@ -6365,6 +6374,29 @@ CONFIG_GENERIC_IOMAP=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
@@ -6516,12 +6548,20 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
 # CONFIG_PAGE_EXTENSION is not set
 # CONFIG_DEBUG_PAGEALLOC is not set
 # CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_TABLE_CHECK is not set
 # CONFIG_PAGE_POISONING is not set
 # CONFIG_DEBUG_PAGE_REF is not set
 # CONFIG_DEBUG_RODATA_TEST is not set
@@ -6654,6 +6694,8 @@ CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
 CONFIG_HAVE_FENTRY=y
 CONFIG_HAVE_OBJTOOL_MCOUNT=y
 CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
+CONFIG_BUILDTIME_MCOUNT_SORT=y
 CONFIG_TRACER_MAX_TRACE=y
 CONFIG_TRACE_CLOCK=y
 CONFIG_RING_BUFFER=y
@@ -6704,6 +6746,7 @@ CONFIG_FTRACE_MCOUNT_USE_CC=y
 # CONFIG_TRACE_EVAL_MAP_FILE is not set
 # CONFIG_FTRACE_RECORD_RECURSION is not set
 # CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_FTRACE_SORT_STARTUP_TEST is not set
 # CONFIG_RING_BUFFER_STARTUP_TEST is not set
 # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set
 # CONFIG_PREEMPTIRQ_DELAY_TEST is not set
@@ -6757,6 +6800,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_MIN_HEAP is not set
 # CONFIG_TEST_DIV64 is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_REED_SOLOMON_TEST is not set
 # CONFIG_INTERVAL_TREE_TEST is not set
@@ -6774,7 +6818,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_XARRAY is not set
 # CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_IDA is not set
 # CONFIG_TEST_LKM is not set
 # CONFIG_TEST_BITOPS is not set

projects/NXP/devices/iMX6/linux/linux.arm.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 5.16.0-rc8 Kernel Configuration
+# Linux/arm 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0"
 CONFIG_CC_IS_GCC=y
@@ -202,7 +202,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -667,6 +666,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
 CONFIG_HAVE_EXIT_THREAD=y
 CONFIG_ARCH_MMAP_RND_BITS=8
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -783,13 +783,12 @@ CONFIG_CONTIG_ALLOC=y
 CONFIG_BOUNCE=y
 # CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
 # CONFIG_CMA_SYSFS is not set
 CONFIG_CMA_AREAS=7
+# CONFIG_ZSWAP is not set
 # CONFIG_ZPOOL is not set
 # CONFIG_ZSMALLOC is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y
@@ -798,6 +797,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
 # CONFIG_GUP_TEST is not set
 CONFIG_KMAP_LOCAL=y
 CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1032,6 +1032,7 @@ CONFIG_BT_INTEL=m
 CONFIG_BT_BCM=m
 CONFIG_BT_RTL=m
 CONFIG_BT_QCA=m
+CONFIG_BT_MTK=m
 CONFIG_BT_HCIBTUSB=m
 CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
 CONFIG_BT_HCIBTUSB_BCM=y
@@ -1206,6 +1207,7 @@ CONFIG_PCI_IMX6=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 # CONFIG_STANDALONE is not set
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1424,7 +1426,6 @@ CONFIG_BLK_DEV_RAM_SIZE=65536
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
 
 #
 # NVME Support
@@ -1746,6 +1747,7 @@ CONFIG_NET_VENDOR_DLINK=y
 # CONFIG_SUNDANCE is not set
 CONFIG_NET_VENDOR_EMULEX=y
 # CONFIG_BE2NET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 CONFIG_NET_VENDOR_EZCHIP=y
 # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -1866,6 +1868,7 @@ CONFIG_NET_VENDOR_TEHUTI=y
 CONFIG_NET_VENDOR_TI=y
 # CONFIG_TI_CPSW_PHY_SEL is not set
 # CONFIG_TLAN is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 CONFIG_NET_VENDOR_VIA=y
 # CONFIG_VIA_RHINE is not set
 # CONFIG_VIA_VELOCITY is not set
@@ -2567,11 +2570,11 @@ CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
 # CONFIG_PINCTRL_MCP23S08 is not set
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PINCTRL_SX150X is not set
-# CONFIG_PINCTRL_STMFX is not set
-# CONFIG_PINCTRL_OCELOT is not set
 # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
 CONFIG_PINCTRL_IMX=y
 CONFIG_PINCTRL_IMX6Q=y
 CONFIG_PINCTRL_IMX6SL=y
@@ -2583,6 +2586,7 @@ CONFIG_PINCTRL_IMX6UL=y
 # CONFIG_PINCTRL_IMX8MP is not set
 # CONFIG_PINCTRL_IMX8MQ is not set
 # CONFIG_PINCTRL_IMX8ULP is not set
+# CONFIG_PINCTRL_IMXRT1050 is not set
 
 #
 # Renesas pinctrl drivers
@@ -2678,6 +2682,7 @@ CONFIG_GPIO_STMPE=y
 #
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2720,6 +2725,7 @@ CONFIG_POWER_SUPPLY_HWMON=y
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
 # CONFIG_CHARGER_BQ24257 is not set
@@ -2843,6 +2849,7 @@ CONFIG_SENSORS_IIO_HWMON=y
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -2872,6 +2879,7 @@ CONFIG_SENSORS_IIO_HWMON=y
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 # CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -3081,7 +3089,6 @@ CONFIG_MFD_SYSCON=y
 # CONFIG_MFD_WM8350_I2C is not set
 CONFIG_MFD_WM8994=y
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -3124,6 +3131,7 @@ CONFIG_REGULATOR_GPIO=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 CONFIG_REGULATOR_MC13XXX_CORE=y
 CONFIG_REGULATOR_MC13783=y
@@ -3540,6 +3548,7 @@ CONFIG_VIDEO_IR_I2C=y
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -3840,7 +3849,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=100
 # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
 # CONFIG_DRM_DP_CEC is not set
 CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
 CONFIG_DRM_SCHED=y
 
 #
@@ -3871,7 +3879,8 @@ CONFIG_DRM_SCHED=y
 # CONFIG_DRM_MGAG200 is not set
 # CONFIG_DRM_ARMADA is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 # CONFIG_DRM_OMAP is not set
 # CONFIG_DRM_TILCDC is not set
 # CONFIG_DRM_QXL is not set
@@ -3973,6 +3982,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -3989,6 +3999,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -4208,6 +4219,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -4278,6 +4290,7 @@ CONFIG_SND_SOC_WM_HUBS=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 CONFIG_SND_SOC_AK4458=m
 # CONFIG_SND_SOC_AK4554 is not set
 # CONFIG_SND_SOC_AK4613 is not set
@@ -4375,6 +4388,7 @@ CONFIG_SND_SOC_SGTL5000=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 CONFIG_SND_SOC_TLV320AIC23=y
 CONFIG_SND_SOC_TLV320AIC23_I2C=y
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
@@ -4497,6 +4511,7 @@ CONFIG_HID_APPLE=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 # CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
 # CONFIG_HID_LOGITECH is not set
 # CONFIG_HID_MAGICMOUSE is not set
 # CONFIG_HID_MALTRON is not set
@@ -4984,6 +4999,10 @@ CONFIG_LEDS_TRIGGER_GPIO=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_ATOMIC_SCRUB=y
@@ -5288,6 +5307,7 @@ CONFIG_COMMON_CLK=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 CONFIG_COMMON_CLK_CS2000_CP=y
+# CONFIG_COMMON_CLK_LAN966X is not set
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 # CONFIG_COMMON_CLK_PWM is not set
 # CONFIG_COMMON_CLK_VC5 is not set
@@ -5532,6 +5552,12 @@ CONFIG_VF610_ADC=y
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5589,6 +5615,7 @@ CONFIG_VF610_ADC=y
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5608,6 +5635,7 @@ CONFIG_VF610_ADC=y
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5631,6 +5659,11 @@ CONFIG_VF610_ADC=y
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5646,6 +5679,7 @@ CONFIG_VF610_ADC=y
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -5940,8 +5974,10 @@ CONFIG_RESET_CONTROLLER=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -6423,6 +6459,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6431,24 +6468,6 @@ CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 # CONFIG_CRYPTO_STATS is not set
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
 CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
@@ -6508,6 +6527,25 @@ CONFIG_RATIONAL=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_STMP_DEVICE=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
@@ -6659,6 +6697,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -6686,6 +6731,8 @@ CONFIG_HAVE_ARCH_KASAN=y
 CONFIG_CC_HAS_KASAN_GENERIC=y
 CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
 # CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
 # end of Memory Debugging
 
 # CONFIG_DEBUG_SHIRQ is not set
@@ -6779,6 +6826,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
 CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
 CONFIG_TRACE_CLOCK=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
@@ -6797,6 +6845,7 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_UNWINDER_FRAME_POINTER is not set
 CONFIG_UNWINDER_ARM=y
 CONFIG_ARM_UNWIND=y
+# CONFIG_BACKTRACE_VERBOSE is not set
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_LL is not set
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
@@ -6819,6 +6868,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_MIN_HEAP is not set
 # CONFIG_TEST_DIV64 is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_REED_SOLOMON_TEST is not set
 # CONFIG_INTERVAL_TREE_TEST is not set
@@ -6836,7 +6886,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_XARRAY is not set
 # CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_IDA is not set
 # CONFIG_TEST_LKM is not set
 # CONFIG_TEST_BITOPS is not set

projects/NXP/devices/iMX8/linux/linux.aarch64.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.16.0-rc8 Kernel Configuration
+# Linux/arm64 5.17.0-rc6 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621"
 CONFIG_CC_IS_GCC=y
@@ -209,7 +209,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -425,6 +424,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y
 #
 # ARMv8.2 architectural features
 #
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
 # CONFIG_ARM64_PMEM is not set
 # CONFIG_ARM64_RAS_EXTN is not set
 # CONFIG_ARM64_CNP is not set
@@ -647,6 +648,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -699,6 +701,7 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe"
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_BLOCK=y
 CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_ICQ=y
 CONFIG_BLK_DEV_BSGLIB=y
 # CONFIG_BLK_DEV_INTEGRITY is not set
 # CONFIG_BLK_DEV_ZONED is not set
@@ -857,8 +860,6 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
 # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_CLEANCACHE=y
-CONFIG_FRONTSWAP=y
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 CONFIG_CMA_DEBUGFS=y
@@ -879,6 +880,7 @@ CONFIG_ZONE_DMA32=y
 # CONFIG_GUP_TEST is not set
 # CONFIG_READ_ONLY_THP_FOR_FS is not set
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1415,6 +1417,7 @@ CONFIG_HAVE_PCI=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1714,7 +1717,6 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=y
 CONFIG_ISCSI_BOOT_SYSFS=y
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_UFS_HWMON is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_DH is not set
 # end of SCSI device support
@@ -1762,6 +1764,7 @@ CONFIG_ETHERNET=y
 # CONFIG_NET_VENDOR_CAVIUM is not set
 # CONFIG_NET_VENDOR_CORTINA is not set
 # CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 # CONFIG_NET_VENDOR_EZCHIP is not set
 CONFIG_NET_VENDOR_FREESCALE=y
 CONFIG_FEC=y
@@ -1802,6 +1805,7 @@ CONFIG_DWMAC_GENERIC=y
 CONFIG_DWMAC_IMX8=y
 # CONFIG_DWMAC_INTEL_PLAT is not set
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_NET_VENDOR_XILINX=y
@@ -2496,12 +2500,12 @@ CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
 # CONFIG_PINCTRL_MCP23S08 is not set
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PINCTRL_SX150X is not set
-# CONFIG_PINCTRL_STMFX is not set
-# CONFIG_PINCTRL_RK805 is not set
-# CONFIG_PINCTRL_OCELOT is not set
 # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_RK805 is not set
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
 CONFIG_PINCTRL_IMX=y
 CONFIG_PINCTRL_IMX_SCU=y
 CONFIG_PINCTRL_IMX8MM=y
@@ -2512,6 +2516,7 @@ CONFIG_PINCTRL_IMX8QM=y
 CONFIG_PINCTRL_IMX8QXP=y
 # CONFIG_PINCTRL_IMX8DXL is not set
 # CONFIG_PINCTRL_IMX8ULP is not set
+# CONFIG_PINCTRL_IMXRT1050 is not set
 
 #
 # Renesas pinctrl drivers
@@ -2593,6 +2598,7 @@ CONFIG_GPIO_MXC=y
 #
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2632,6 +2638,7 @@ CONFIG_POWER_SUPPLY_HWMON=y
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
 # CONFIG_CHARGER_BQ24257 is not set
@@ -2754,6 +2761,7 @@ CONFIG_SENSORS_GPIO_FAN=m
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -2782,6 +2790,7 @@ CONFIG_SENSORS_PWM_FAN=m
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 # CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -2979,7 +2988,6 @@ CONFIG_MFD_WM5102=y
 # CONFIG_MFD_WM8350_I2C is not set
 CONFIG_MFD_WM8994=y
 CONFIG_MFD_ROHM_BD718XX=y
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -3025,6 +3033,7 @@ CONFIG_REGULATOR_GPIO=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MCP16502 is not set
 # CONFIG_REGULATOR_MP5416 is not set
@@ -3453,6 +3462,7 @@ CONFIG_VIDEO_CX25840=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -3753,7 +3763,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=100
 CONFIG_DRM_LOAD_EDID_FIRMWARE=y
 # CONFIG_DRM_DP_CEC is not set
 CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
 CONFIG_DRM_SCHED=y
 
 #
@@ -3777,7 +3786,8 @@ CONFIG_DRM_SCHED=y
 # CONFIG_DRM_VKMS is not set
 # CONFIG_DRM_UDL is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 CONFIG_DRM_PANEL=y
 
 #
@@ -3870,6 +3880,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -3884,6 +3895,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -3999,6 +4011,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -4067,6 +4080,7 @@ CONFIG_SND_SOC_WM_HUBS=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 CONFIG_SND_SOC_AK4458=y
 # CONFIG_SND_SOC_AK4554 is not set
 # CONFIG_SND_SOC_AK4613 is not set
@@ -4165,9 +4179,10 @@ CONFIG_SND_SOC_SPDIF=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
-# CONFIG_SND_SOC_TLV320AIC31XX is not set
+CONFIG_SND_SOC_TLV320AIC31XX=y
 # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC3X_I2C is not set
@@ -4287,6 +4302,7 @@ CONFIG_HID_KENSINGTON=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 CONFIG_HID_LENOVO=y
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 CONFIG_HID_LOGITECH_DJ=y
 CONFIG_HID_LOGITECH_HIDPP=y
@@ -4736,6 +4752,10 @@ CONFIG_LEDS_TRIGGER_CPU=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_SUPPORT=y
@@ -4997,6 +5017,7 @@ CONFIG_STAGING_MEDIA=y
 CONFIG_VIDEO_HANTRO=m
 CONFIG_VIDEO_HANTRO_IMX8M=y
 # CONFIG_VIDEO_IMX_MEDIA is not set
+# CONFIG_VIDEO_MAX96712 is not set
 
 #
 # Android
@@ -5028,6 +5049,7 @@ CONFIG_CROS_EC_SENSORHUB=y
 CONFIG_CROS_EC_SYSFS=y
 CONFIG_CROS_USBPD_NOTIFY=y
 # CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CLK_PREPARE=y
 CONFIG_COMMON_CLK=y
@@ -5051,6 +5073,7 @@ CONFIG_COMMON_CLK=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 # CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
 # CONFIG_COMMON_CLK_S2MPS11 is not set
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 # CONFIG_COMMON_CLK_XGENE is not set
@@ -5326,6 +5349,12 @@ CONFIG_IIO=y
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5385,6 +5414,7 @@ CONFIG_IIO=y
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5404,6 +5434,7 @@ CONFIG_IIO=y
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5427,6 +5458,12 @@ CONFIG_IIO=y
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5442,6 +5479,7 @@ CONFIG_IIO=y
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -5732,8 +5770,10 @@ CONFIG_GENERIC_PHY=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 CONFIG_PHY_FSL_IMX8MQ_USB=y
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+CONFIG_PHY_FSL_IMX8M_PCIE=y
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -5753,6 +5793,7 @@ CONFIG_ARM_PMU=y
 # CONFIG_ARM_DSU_PMU is not set
 CONFIG_FSL_IMX8_DDR_PMU=y
 # CONFIG_ARM_SPE_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
 # end of Performance monitor support
 
 # CONFIG_RAS is not set
@@ -6099,7 +6140,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
 # end of Kernel hardening options
 # end of Security options
 
-CONFIG_XOR_BLOCKS=m
+CONFIG_XOR_BLOCKS=y
 CONFIG_CRYPTO=y
 
 #
@@ -6132,7 +6173,6 @@ CONFIG_CRYPTO_PCRYPT=y
 CONFIG_CRYPTO_CRYPTD=y
 # CONFIG_CRYPTO_AUTHENC is not set
 # CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_SIMD=y
 
 #
 # Public-key cryptography
@@ -6244,6 +6284,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6251,25 +6292,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
 # CONFIG_CRYPTO_USER_API_AEAD is not set
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_FSL_CAAM is not set
 # CONFIG_CRYPTO_DEV_SAHARA is not set
@@ -6313,7 +6335,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 CONFIG_CORDIC=m
 # CONFIG_PRIME_NUMBERS is not set
 CONFIG_RATIONAL=y
@@ -6322,6 +6343,26 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
 # CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
@@ -6468,12 +6509,21 @@ CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
 # CONFIG_UBSAN is not set
+CONFIG_HAVE_ARCH_KCSAN=y
 CONFIG_HAVE_KCSAN_COMPILER=y
+# CONFIG_KCSAN is not set
 # end of Generic Kernel Debugging Instruments
 
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -6616,7 +6666,6 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_ARCH_HAS_KCOV=y
 CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
 CONFIG_ARCH_USE_MEMTEST=y
 # CONFIG_MEMTEST is not set

projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch

@@ -3653,7 +3653,7 @@ index 17a9e7eb2130..bd013659404f 100644
 --- a/drivers/gpu/drm/rockchip/Makefile
 +++ b/drivers/gpu/drm/rockchip/Makefile
 @@ -8,7 +8,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
- rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
+ 		rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o
  
  rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 -rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o

projects/NXP/devices/iMX8/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch

@@ -1,42 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:31 +0100
-Subject: [PATCH] hantro: postproc: Fix motion vector space size
-
-When the post-processor hardware block is enabled, the driver
-allocates an internal queue of buffers for the decoder enginer,
-and uses the vb2 queue for the post-processor engine.
-
-For instance, on a G1 core, the decoder engine produces NV12 buffers
-and the post-processor engine can produce YUY2 buffers. The decoder
-engine expects motion vectors to be appended to the NV12 buffers,
-but this is only required for CODECs that need motion vectors,
-such as H.264.
-
-Fix the post-processor logic accordingly.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro_postproc.c | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index ed8916c950a4..07842152003f 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -132,9 +132,10 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)
- 	unsigned int num_buffers = cap_queue->num_buffers;
- 	unsigned int i, buf_size;
- 
--	buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage +
--		   hantro_h264_mv_size(ctx->dst_fmt.width,
--				       ctx->dst_fmt.height);
-+	buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage;
-+	if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
-+		buf_size += hantro_h264_mv_size(ctx->dst_fmt.width,
-+						ctx->dst_fmt.height);
- 
- 	for (i = 0; i < num_buffers; ++i) {
- 		struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];

projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch

@@ -1,229 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:32 +0100
-Subject: [PATCH] hantro: postproc: Introduce struct hantro_postproc_ops
-
-Turns out the post-processor block on the G2 core is substantially
-different from the one on the G1 core. Introduce hantro_postproc_ops
-with .enable and .disable methods, which will allow to support
-the G2 post-processor cleanly.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro.h         |  5 +--
- drivers/staging/media/hantro/hantro_hw.h      | 13 ++++++-
- .../staging/media/hantro/hantro_postproc.c    | 35 +++++++++++++------
- drivers/staging/media/hantro/imx8m_vpu_hw.c   |  2 +-
- .../staging/media/hantro/rockchip_vpu_hw.c    |  6 ++--
- .../staging/media/hantro/sama5d4_vdec_hw.c    |  2 +-
- 6 files changed, 45 insertions(+), 18 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index c2e2dca38628..c2e01959dc00 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -28,6 +28,7 @@
- 
- struct hantro_ctx;
- struct hantro_codec_ops;
-+struct hantro_postproc_ops;
- 
- #define HANTRO_JPEG_ENCODER	BIT(0)
- #define HANTRO_ENCODERS		0x0000ffff
-@@ -59,6 +60,7 @@ struct hantro_irq {
-  * @num_dec_fmts:		Number of decoder formats.
-  * @postproc_fmts:		Post-processor formats.
-  * @num_postproc_fmts:		Number of post-processor formats.
-+ * @postproc_ops:		Post-processor ops.
-  * @codec:			Supported codecs
-  * @codec_ops:			Codec ops.
-  * @init:			Initialize hardware, optional.
-@@ -69,7 +71,6 @@ struct hantro_irq {
-  * @num_clocks:			number of clocks in the array
-  * @reg_names:			array of register range names
-  * @num_regs:			number of register range names in the array
-- * @postproc_regs:		&struct hantro_postproc_regs pointer
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -80,6 +81,7 @@ struct hantro_variant {
- 	unsigned int num_dec_fmts;
- 	const struct hantro_fmt *postproc_fmts;
- 	unsigned int num_postproc_fmts;
-+	const struct hantro_postproc_ops *postproc_ops;
- 	unsigned int codec;
- 	const struct hantro_codec_ops *codec_ops;
- 	int (*init)(struct hantro_dev *vpu);
-@@ -90,7 +92,6 @@ struct hantro_variant {
- 	int num_clocks;
- 	const char * const *reg_names;
- 	int num_regs;
--	const struct hantro_postproc_regs *postproc_regs;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index 267a6d33a47b..2f85430682d8 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -174,6 +174,17 @@ struct hantro_postproc_ctx {
- 	struct hantro_aux_buf dec_q[VB2_MAX_FRAME];
- };
- 
-+/**
-+ * struct hantro_postproc_ops - post-processor operations
-+ *
-+ * @enable:	Enable the post-processor block. Optional.
-+ * @disable:	Disable the post-processor block. Optional.
-+ */
-+struct hantro_postproc_ops {
-+	void (*enable)(struct hantro_ctx *ctx);
-+	void (*disable)(struct hantro_ctx *ctx);
-+};
-+
- /**
-  * struct hantro_codec_ops - codec mode specific operations
-  *
-@@ -221,7 +232,7 @@ extern const struct hantro_variant rk3328_vpu_variant;
- extern const struct hantro_variant rk3399_vpu_variant;
- extern const struct hantro_variant sama5d4_vdec_variant;
- 
--extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
-+extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
- 
- extern const u32 hantro_vp8_dec_mc_filter[8][6];
- 
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 07842152003f..882fb8bc5ddd 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -15,14 +15,14 @@
- #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \
- { \
- 	hantro_reg_write(vpu, \
--			 &(vpu)->variant->postproc_regs->reg_name, \
-+			 &hantro_g1_postproc_regs.reg_name, \
- 			 val); \
- }
- 
- #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \
- { \
- 	hantro_reg_write_s(vpu, \
--			   &(vpu)->variant->postproc_regs->reg_name, \
-+			   &hantro_g1_postproc_regs.reg_name, \
- 			   val); \
- }
- 
-@@ -64,16 +64,13 @@ bool hantro_needs_postproc(const struct hantro_ctx *ctx,
- 	return fmt->fourcc != V4L2_PIX_FMT_NV12;
- }
- 
--void hantro_postproc_enable(struct hantro_ctx *ctx)
-+static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
- 	struct vb2_v4l2_buffer *dst_buf;
- 	u32 src_pp_fmt, dst_pp_fmt;
- 	dma_addr_t dst_dma;
- 
--	if (!vpu->variant->postproc_regs)
--		return;
--
- 	/* Turn on pipeline mode. Must be done first. */
- 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
- 
-@@ -154,12 +151,30 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)
- 	return 0;
- }
- 
--void hantro_postproc_disable(struct hantro_ctx *ctx)
-+static void hantro_postproc_g1_disable(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
- 
--	if (!vpu->variant->postproc_regs)
--		return;
--
- 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
- }
-+
-+void hantro_postproc_disable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+
-+	if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable)
-+		vpu->variant->postproc_ops->disable(ctx);
-+}
-+
-+void hantro_postproc_enable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+
-+	if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable)
-+		vpu->variant->postproc_ops->enable(ctx);
-+}
-+
-+const struct hantro_postproc_ops hantro_g1_postproc_ops = {
-+	.enable = hantro_postproc_g1_enable,
-+	.disable = hantro_postproc_g1_disable,
-+};
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index ea919bfb9891..22fa7d2f3b64 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -262,7 +262,7 @@ const struct hantro_variant imx8mq_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
- 	.postproc_fmts = imx8m_vpu_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
- 		 HANTRO_H264_DECODER,
- 	.codec_ops = imx8mq_vpu_codec_ops,
-diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-index d4f52957cc53..6c1ad5534ce5 100644
---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
-+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-@@ -460,7 +460,7 @@ const struct hantro_variant rk3036_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
- 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
- 		 HANTRO_H264_DECODER,
- 	.codec_ops = rk3036_vpu_codec_ops,
-@@ -485,7 +485,7 @@ const struct hantro_variant rk3066_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
- 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
- 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
- 	.codec_ops = rk3066_vpu_codec_ops,
-@@ -505,7 +505,7 @@ const struct hantro_variant rk3288_vpu_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
- 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
- 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
- 	.codec_ops = rk3288_vpu_codec_ops,
-diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-index 9c3b8cd0b239..f3fecc7248c4 100644
---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-@@ -100,7 +100,7 @@ const struct hantro_variant sama5d4_vdec_variant = {
- 	.num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts),
- 	.postproc_fmts = sama5d4_vdec_postproc_fmts,
- 	.num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts),
--	.postproc_regs = &hantro_g1_postproc_regs,
-+	.postproc_ops = &hantro_g1_postproc_ops,
- 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
- 		 HANTRO_H264_DECODER,
- 	.codec_ops = sama5d4_vdec_codec_ops,

projects/NXP/devices/iMX8/patches/linux/0069-hantro-Simplify-postprocessor.patch

@@ -1,97 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:33 +0100
-Subject: [PATCH] hantro: Simplify postprocessor
-
-Add a 'postprocessed' boolean property to struct hantro_fmt
-to signal that a format is produced by the post-processor.
-This will allow to introduce the G2 post-processor in a simple way.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro.h          | 2 ++
- drivers/staging/media/hantro/hantro_postproc.c | 8 +-------
- drivers/staging/media/hantro/imx8m_vpu_hw.c    | 1 +
- drivers/staging/media/hantro/rockchip_vpu_hw.c | 1 +
- drivers/staging/media/hantro/sama5d4_vdec_hw.c | 1 +
- 5 files changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index c2e01959dc00..dd5e56765d4e 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -263,6 +263,7 @@ struct hantro_ctx {
-  * @max_depth:	Maximum depth, for bitstream formats
-  * @enc_fmt:	Format identifier for encoder registers.
-  * @frmsize:	Supported range of frame sizes (only for bitstream formats).
-+ * @postprocessed: Indicates if this format needs the post-processor.
-  */
- struct hantro_fmt {
- 	char *name;
-@@ -272,6 +273,7 @@ struct hantro_fmt {
- 	int max_depth;
- 	enum hantro_enc_fmt enc_fmt;
- 	struct v4l2_frmsize_stepwise frmsize;
-+	bool postprocessed;
- };
- 
- struct hantro_reg {
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 882fb8bc5ddd..4549aec08feb 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -53,15 +53,9 @@ const struct hantro_postproc_regs hantro_g1_postproc_regs = {
- bool hantro_needs_postproc(const struct hantro_ctx *ctx,
- 			   const struct hantro_fmt *fmt)
- {
--	struct hantro_dev *vpu = ctx->dev;
--
- 	if (ctx->is_encoder)
- 		return false;
--
--	if (!vpu->variant->postproc_fmts)
--		return false;
--
--	return fmt->fourcc != V4L2_PIX_FMT_NV12;
-+	return fmt->postprocessed;
- }
- 
- static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 22fa7d2f3b64..02e61438220a 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -82,6 +82,7 @@ static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_YUYV,
- 		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
- 	},
- };
- 
-diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-index 6c1ad5534ce5..f372f767d4ff 100644
---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
-+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
-@@ -62,6 +62,7 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_YUYV,
- 		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
- 	},
- };
- 
-diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-index f3fecc7248c4..b2fc1c5613e1 100644
---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c
-@@ -15,6 +15,7 @@ static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_YUYV,
- 		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
- 	},
- };
- 

projects/NXP/devices/iMX8/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch

@@ -1,65 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Ezequiel Garcia <ezequiel@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:34 +0100
-Subject: [PATCH] hantro: Add quirk for NV12/NV12_4L4 capture format
-
-The G2 core decoder engine produces NV12_4L4 format,
-which is a simple NV12 4x4 tiled format. The driver currently
-hides this format by always enabling the post-processor engine,
-and therefore offering NV12 directly.
-
-This is done without using the logic in hantro_postproc.c
-and therefore makes it difficult to add VP9 cleanly.
-
-Since fixing this is not easy, add a small quirk to force
-NV12 if HEVC was configured, but otherwise declare NV12_4L4
-as the pixel format in imx8mq_vpu_g2_variant.dec_fmts.
-
-This will be used by the VP9 decoder which will be added soon.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro_v4l2.c  | 14 ++++++++++++++
- drivers/staging/media/hantro/imx8m_vpu_hw.c |  2 +-
- 2 files changed, 15 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c
-index bcb0bdff4a9a..d1f060c55fed 100644
---- a/drivers/staging/media/hantro/hantro_v4l2.c
-+++ b/drivers/staging/media/hantro/hantro_v4l2.c
-@@ -150,6 +150,20 @@ static int vidioc_enum_fmt(struct file *file, void *priv,
- 	unsigned int num_fmts, i, j = 0;
- 	bool skip_mode_none;
- 
-+	/*
-+	 * The HEVC decoder on the G2 core needs a little quirk to offer NV12
-+	 * only on the capture side. Once the post-processor logic is used,
-+	 * we will be able to expose NV12_4L4 and NV12 as the other cases,
-+	 * and therefore remove this quirk.
-+	 */
-+	if (capture && ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) {
-+		if (f->index == 0) {
-+			f->pixelformat = V4L2_PIX_FMT_NV12;
-+			return 0;
-+		}
-+		return -EINVAL;
-+	}
-+
- 	/*
- 	 * When dealing with an encoder:
- 	 *  - on the capture side we want to filter out all MODE_NONE formats.
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 02e61438220a..a40b161e5956 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -134,7 +134,7 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
- 
- static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
- 	{
--		.fourcc = V4L2_PIX_FMT_NV12,
-+		.fourcc = V4L2_PIX_FMT_NV12_4L4,
- 		.codec_mode = HANTRO_MODE_NONE,
- 	},
- 	{

projects/NXP/devices/iMX8/patches/linux/0074-media-hantro-Rename-registers.patch

@@ -1,138 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:38 +0100
-Subject: [PATCH] media: hantro: Rename registers
-
-Add more consistency in the way registers are named.
-
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- .../staging/media/hantro/hantro_g2_hevc_dec.c | 40 +++++++++----------
- drivers/staging/media/hantro/hantro_g2_regs.h | 28 ++++++-------
- 2 files changed, 34 insertions(+), 34 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-index 76a921163b9a..abae36f9b418 100644
---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-@@ -448,9 +448,9 @@ static int set_ref(struct hantro_ctx *ctx)
- 		if (dpb[i].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR)
- 			dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);
- 
--		hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr);
--		hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr);
--		hantro_write_addr(vpu, G2_REG_DMV_REF(i), mv_addr);
-+		hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
-+		hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
-+		hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
- 	}
- 
- 	luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val);
-@@ -460,20 +460,20 @@ static int set_ref(struct hantro_ctx *ctx)
- 	chroma_addr = luma_addr + cr_offset;
- 	mv_addr = luma_addr + mv_offset;
- 
--	hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr);
--	hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr);
--	hantro_write_addr(vpu, G2_REG_DMV_REF(i++), mv_addr);
-+	hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
-+	hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
-+	hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr);
- 
--	hantro_write_addr(vpu, G2_ADDR_DST, luma_addr);
--	hantro_write_addr(vpu, G2_ADDR_DST_CHR, chroma_addr);
--	hantro_write_addr(vpu, G2_ADDR_DST_MV, mv_addr);
-+	hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);
-+	hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);
-+	hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);
- 
- 	hantro_hevc_ref_remove_unused(ctx);
- 
- 	for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
--		hantro_write_addr(vpu, G2_REG_ADDR_REF(i), 0);
--		hantro_write_addr(vpu, G2_REG_CHR_REF(i), 0);
--		hantro_write_addr(vpu, G2_REG_DMV_REF(i), 0);
-+		hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);
-+		hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0);
-+		hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0);
- 	}
- 
- 	hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);
-@@ -499,7 +499,7 @@ static void set_buffers(struct hantro_ctx *ctx)
- 	src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
- 	src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0);
- 
--	hantro_write_addr(vpu, G2_ADDR_STR, src_dma);
-+	hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma);
- 	hantro_reg_write(vpu, &g2_stream_len, src_len);
- 	hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);
- 	hantro_reg_write(vpu, &g2_strm_start_offset, 0);
-@@ -508,12 +508,12 @@ static void set_buffers(struct hantro_ctx *ctx)
- 	/* Destination (decoded frame) buffer. */
- 	dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf);
- 
--	hantro_write_addr(vpu, G2_RASTER_SCAN, dst_dma);
--	hantro_write_addr(vpu, G2_RASTER_SCAN_CHR, dst_dma + cr_offset);
--	hantro_write_addr(vpu, G2_ADDR_TILE_SIZE, ctx->hevc_dec.tile_sizes.dma);
--	hantro_write_addr(vpu, G2_TILE_FILTER, ctx->hevc_dec.tile_filter.dma);
--	hantro_write_addr(vpu, G2_TILE_SAO, ctx->hevc_dec.tile_sao.dma);
--	hantro_write_addr(vpu, G2_TILE_BSD, ctx->hevc_dec.tile_bsd.dma);
-+	hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);
-+	hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + cr_offset);
-+	hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma);
-+	hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma);
-+	hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma);
-+	hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma);
- }
- 
- static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
-@@ -563,7 +563,7 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
- 			for (k = 0; k < 8; k++)
- 				*p++ = sc->scaling_list_32x32[i][8 * k + j];
- 
--	hantro_write_addr(vpu, HEVC_SCALING_LIST, ctx->hevc_dec.scaling_lists.dma);
-+	hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
- }
- 
- static void hantro_g2_check_idle(struct hantro_dev *vpu)
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index bb22fa921914..24b18f839ff8 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -177,20 +177,20 @@
- #define G2_REG_CONFIG_DEC_CLK_GATE_E		BIT(16)
- #define G2_REG_CONFIG_DEC_CLK_GATE_IDLE_E	BIT(17)
- 
--#define G2_ADDR_DST		(G2_SWREG(65))
--#define G2_REG_ADDR_REF(i)	(G2_SWREG(67)  + ((i) * 0x8))
--#define G2_ADDR_DST_CHR		(G2_SWREG(99))
--#define G2_REG_CHR_REF(i)	(G2_SWREG(101) + ((i) * 0x8))
--#define G2_ADDR_DST_MV		(G2_SWREG(133))
--#define G2_REG_DMV_REF(i)	(G2_SWREG(135) + ((i) * 0x8))
--#define G2_ADDR_TILE_SIZE	(G2_SWREG(167))
--#define G2_ADDR_STR		(G2_SWREG(169))
--#define HEVC_SCALING_LIST	(G2_SWREG(171))
--#define G2_RASTER_SCAN		(G2_SWREG(175))
--#define G2_RASTER_SCAN_CHR	(G2_SWREG(177))
--#define G2_TILE_FILTER		(G2_SWREG(179))
--#define G2_TILE_SAO		(G2_SWREG(181))
--#define G2_TILE_BSD		(G2_SWREG(183))
-+#define G2_OUT_LUMA_ADDR		(G2_SWREG(65))
-+#define G2_REF_LUMA_ADDR(i)		(G2_SWREG(67)  + ((i) * 0x8))
-+#define G2_OUT_CHROMA_ADDR		(G2_SWREG(99))
-+#define G2_REF_CHROMA_ADDR(i)		(G2_SWREG(101) + ((i) * 0x8))
-+#define G2_OUT_MV_ADDR			(G2_SWREG(133))
-+#define G2_REF_MV_ADDR(i)		(G2_SWREG(135) + ((i) * 0x8))
-+#define G2_TILE_SIZES_ADDR		(G2_SWREG(167))
-+#define G2_STREAM_ADDR			(G2_SWREG(169))
-+#define G2_HEVC_SCALING_LIST_ADDR	(G2_SWREG(171))
-+#define G2_RS_OUT_LUMA_ADDR		(G2_SWREG(175))
-+#define G2_RS_OUT_CHROMA_ADDR		(G2_SWREG(177))
-+#define G2_TILE_FILTER_ADDR		(G2_SWREG(179))
-+#define G2_TILE_SAO_ADDR		(G2_SWREG(181))
-+#define G2_TILE_BSD_ADDR		(G2_SWREG(183))
- 
- #define g2_strm_buffer_len	G2_DEC_REG(258, 0, 0xffffffff)
- #define g2_strm_start_offset	G2_DEC_REG(259, 0, 0xffffffff)

projects/NXP/devices/iMX8/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch

@@ -1,178 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:39 +0100
-Subject: [PATCH] media: hantro: Prepare for other G2 codecs
-
-VeriSilicon Hantro G2 core supports other codecs besides hevc.
-Factor out some common code in preparation for vp9 support.
-
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/Makefile         |  1 +
- drivers/staging/media/hantro/hantro.h         |  7 +++++
- drivers/staging/media/hantro/hantro_drv.c     |  5 +++
- drivers/staging/media/hantro/hantro_g2.c      | 26 ++++++++++++++++
- .../staging/media/hantro/hantro_g2_hevc_dec.c | 31 -------------------
- drivers/staging/media/hantro/hantro_g2_regs.h |  7 +++++
- drivers/staging/media/hantro/hantro_hw.h      |  2 ++
- 7 files changed, 48 insertions(+), 31 deletions(-)
- create mode 100644 drivers/staging/media/hantro/hantro_g2.c
-
-diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile
-index 90036831fec4..fe6d84871d07 100644
---- a/drivers/staging/media/hantro/Makefile
-+++ b/drivers/staging/media/hantro/Makefile
-@@ -12,6 +12,7 @@ hantro-vpu-y += \
- 		hantro_g1_mpeg2_dec.o \
- 		hantro_g2_hevc_dec.o \
- 		hantro_g1_vp8_dec.o \
-+		hantro_g2.o \
- 		rockchip_vpu2_hw_jpeg_enc.o \
- 		rockchip_vpu2_hw_h264_dec.o \
- 		rockchip_vpu2_hw_mpeg2_dec.o \
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index dd5e56765d4e..d91eb2b1c509 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -369,6 +369,13 @@ static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
- 	writel(val, vpu->dec_base + reg);
- }
- 
-+static inline void hantro_write_addr(struct hantro_dev *vpu,
-+				     unsigned long offset,
-+				     dma_addr_t addr)
-+{
-+	vdpu_write(vpu, addr & 0xffffffff, offset);
-+}
-+
- static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
- {
- 	u32 val = readl(vpu->dec_base + reg);
-diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
-index fb82b9297a2b..bb72e5e208b7 100644
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -907,6 +907,11 @@ static int hantro_probe(struct platform_device *pdev)
- 	vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
- 	vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
- 
-+	/**
-+	 * TODO: Eventually allow taking advantage of full 64-bit address space.
-+	 * Until then we assume the MSB portion of buffers' base addresses is
-+	 * always 0 due to this masking operation.
-+	 */
- 	ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
- 	if (ret) {
- 		dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
-diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c
-new file mode 100644
-index 000000000000..6f3e1f797f83
---- /dev/null
-+++ b/drivers/staging/media/hantro/hantro_g2.c
-@@ -0,0 +1,26 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Hantro VPU codec driver
-+ *
-+ * Copyright (C) 2021 Collabora Ltd, Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-+ */
-+
-+#include "hantro_hw.h"
-+#include "hantro_g2_regs.h"
-+
-+void hantro_g2_check_idle(struct hantro_dev *vpu)
-+{
-+	int i;
-+
-+	for (i = 0; i < 3; i++) {
-+		u32 status;
-+
-+		/* Make sure the VPU is idle */
-+		status = vdpu_read(vpu, G2_REG_INTERRUPT);
-+		if (status & G2_REG_INTERRUPT_DEC_E) {
-+			dev_warn(vpu->dev, "device still running, aborting");
-+			status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS;
-+			vdpu_write(vpu, status, G2_REG_INTERRUPT);
-+		}
-+	}
-+}
-diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-index abae36f9b418..f62608b0b408 100644
---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
-@@ -8,20 +8,6 @@
- #include "hantro_hw.h"
- #include "hantro_g2_regs.h"
- 
--#define HEVC_DEC_MODE	0xC
--
--#define BUS_WIDTH_32		0
--#define BUS_WIDTH_64		1
--#define BUS_WIDTH_128		2
--#define BUS_WIDTH_256		3
--
--static inline void hantro_write_addr(struct hantro_dev *vpu,
--				     unsigned long offset,
--				     dma_addr_t addr)
--{
--	vdpu_write(vpu, addr & 0xffffffff, offset);
--}
--
- static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-@@ -566,23 +552,6 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx)
- 	hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma);
- }
- 
--static void hantro_g2_check_idle(struct hantro_dev *vpu)
--{
--	int i;
--
--	for (i = 0; i < 3; i++) {
--		u32 status;
--
--		/* Make sure the VPU is idle */
--		status = vdpu_read(vpu, G2_REG_INTERRUPT);
--		if (status & G2_REG_INTERRUPT_DEC_E) {
--			dev_warn(vpu->dev, "device still running, aborting");
--			status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS;
--			vdpu_write(vpu, status, G2_REG_INTERRUPT);
--		}
--	}
--}
--
- int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index 24b18f839ff8..136ba6d98a1f 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -27,6 +27,13 @@
- #define G2_REG_INTERRUPT_DEC_IRQ_DIS	BIT(4)
- #define G2_REG_INTERRUPT_DEC_E		BIT(0)
- 
-+#define HEVC_DEC_MODE			0xc
-+
-+#define BUS_WIDTH_32			0
-+#define BUS_WIDTH_64			1
-+#define BUS_WIDTH_128			2
-+#define BUS_WIDTH_256			3
-+
- #define g2_strm_swap		G2_DEC_REG(2, 28, 0xf)
- #define g2_dirmv_swap		G2_DEC_REG(2, 20, 0xf)
- 
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index 2f85430682d8..1d869abf90b2 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -312,4 +312,6 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx);
- void hantro_vp8_prob_update(struct hantro_ctx *ctx,
- 			    const struct v4l2_ctrl_vp8_frame *hdr);
- 
-+void hantro_g2_check_idle(struct hantro_dev *vpu);
-+
- #endif /* HANTRO_HW_H_ */

projects/NXP/devices/iMX8/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch

@@ -1,27 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:41 +0100
-Subject: [PATCH] media: hantro: Staticize a struct in postprocessor code
-
-The struct is not used outside this file, so it can be static.
-
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- drivers/staging/media/hantro/hantro_postproc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 4549aec08feb..89de43021779 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -33,7 +33,7 @@
- #define VPU_PP_OUT_RGB			0x0
- #define VPU_PP_OUT_YUYV			0x3
- 
--const struct hantro_postproc_regs hantro_g1_postproc_regs = {
-+static const struct hantro_postproc_regs hantro_g1_postproc_regs = {
- 	.pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1},
- 	.max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
- 	.clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},

projects/NXP/devices/iMX8/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch

@@ -1,161 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Date: Tue, 16 Nov 2021 15:38:42 +0100
-Subject: [PATCH] media: hantro: Support NV12 on the G2 core
-
-The G2 decoder block produces NV12 4x4 tiled format (NV12_4L4).
-Enable the G2 post-processor block, in order to produce regular NV12.
-
-The logic in hantro_postproc.c is leveraged to take care of allocating
-the extra buffers and configure the post-processor, which is
-significantly simpler than the one on the G1.
-
-Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
-Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
----
- .../staging/media/hantro/hantro_g2_vp9_dec.c  |  6 ++--
- drivers/staging/media/hantro/hantro_hw.h      |  1 +
- .../staging/media/hantro/hantro_postproc.c    | 31 +++++++++++++++++++
- drivers/staging/media/hantro/imx8m_vpu_hw.c   | 11 +++++++
- 4 files changed, 46 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-index fc55b03a8004..e04242d10fa2 100644
---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-@@ -152,7 +152,7 @@ static void config_output(struct hantro_ctx *ctx,
- 	hantro_reg_write(ctx->dev, &g2_out_dis, 0);
- 	hantro_reg_write(ctx->dev, &g2_output_format, 0);
- 
--	luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0);
-+	luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
- 	hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr);
- 
- 	chroma_addr = luma_addr + chroma_offset(ctx, dec_params);
-@@ -191,7 +191,7 @@ static void config_ref(struct hantro_ctx *ctx,
- 	hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width);
- 	hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height);
- 
--	luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0);
-+	luma_addr = hantro_get_dec_buf_addr(ctx, &buf->base.vb.vb2_buf);
- 	hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr);
- 
- 	chroma_addr = luma_addr + chroma_offset(ctx, dec_params);
-@@ -236,7 +236,7 @@ static void config_ref_registers(struct hantro_ctx *ctx,
- 	config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts);
- 	config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts);
- 
--	mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) +
-+	mv_addr = hantro_get_dec_buf_addr(ctx, &mv_ref->base.vb.vb2_buf) +
- 		  mv_offset(ctx, dec_params);
- 	hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr);
- 
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index fe5b51046d33..dbe51303724b 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -310,6 +310,7 @@ extern const struct hantro_variant rk3399_vpu_variant;
- extern const struct hantro_variant sama5d4_vdec_variant;
- 
- extern const struct hantro_postproc_ops hantro_g1_postproc_ops;
-+extern const struct hantro_postproc_ops hantro_g2_postproc_ops;
- 
- extern const u32 hantro_vp8_dec_mc_filter[8][6];
- 
-diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
-index 89de43021779..a7774ad4c445 100644
---- a/drivers/staging/media/hantro/hantro_postproc.c
-+++ b/drivers/staging/media/hantro/hantro_postproc.c
-@@ -11,6 +11,7 @@
- #include "hantro.h"
- #include "hantro_hw.h"
- #include "hantro_g1_regs.h"
-+#include "hantro_g2_regs.h"
- 
- #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \
- { \
-@@ -99,6 +100,21 @@ static void hantro_postproc_g1_enable(struct hantro_ctx *ctx)
- 	HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
- }
- 
-+static void hantro_postproc_g2_enable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+	struct vb2_v4l2_buffer *dst_buf;
-+	size_t chroma_offset = ctx->dst_fmt.width * ctx->dst_fmt.height;
-+	dma_addr_t dst_dma;
-+
-+	dst_buf = hantro_get_dst_buf(ctx);
-+	dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
-+
-+	hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma);
-+	hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset);
-+	hantro_reg_write(vpu, &g2_out_rs_e, 1);
-+}
-+
- void hantro_postproc_free(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-@@ -127,6 +143,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx)
- 	if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
- 		buf_size += hantro_h264_mv_size(ctx->dst_fmt.width,
- 						ctx->dst_fmt.height);
-+	else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME)
-+		buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width,
-+					       ctx->dst_fmt.height);
- 
- 	for (i = 0; i < num_buffers; ++i) {
- 		struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
-@@ -152,6 +171,13 @@ static void hantro_postproc_g1_disable(struct hantro_ctx *ctx)
- 	HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
- }
- 
-+static void hantro_postproc_g2_disable(struct hantro_ctx *ctx)
-+{
-+	struct hantro_dev *vpu = ctx->dev;
-+
-+	hantro_reg_write(vpu, &g2_out_rs_e, 0);
-+}
-+
- void hantro_postproc_disable(struct hantro_ctx *ctx)
- {
- 	struct hantro_dev *vpu = ctx->dev;
-@@ -172,3 +198,8 @@ const struct hantro_postproc_ops hantro_g1_postproc_ops = {
- 	.enable = hantro_postproc_g1_enable,
- 	.disable = hantro_postproc_g1_disable,
- };
-+
-+const struct hantro_postproc_ops hantro_g2_postproc_ops = {
-+	.enable = hantro_postproc_g2_enable,
-+	.disable = hantro_postproc_g2_disable,
-+};
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 455a107ffb02..1a43f6fceef9 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -132,6 +132,14 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
- 	},
- };
- 
-+static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = {
-+	{
-+		.fourcc = V4L2_PIX_FMT_NV12,
-+		.codec_mode = HANTRO_MODE_NONE,
-+		.postprocessed = true,
-+	},
-+};
-+
- static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
- 	{
- 		.fourcc = V4L2_PIX_FMT_NV12_4L4,
-@@ -301,6 +309,9 @@ const struct hantro_variant imx8mq_vpu_g2_variant = {
- 	.dec_offset = 0x0,
- 	.dec_fmts = imx8m_vpu_g2_dec_fmts,
- 	.num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts),
-+	.postproc_fmts = imx8m_vpu_g2_postproc_fmts,
-+	.num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_g2_postproc_fmts),
-+	.postproc_ops = &hantro_g2_postproc_ops,
- 	.codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER,
- 	.codec_ops = imx8mq_vpu_g2_codec_ops,
- 	.init = imx8mq_vpu_hw_init,

projects/NXP/devices/iMX8/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch

@@ -1,92 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sat, 7 Aug 2021 17:29:11 +0200
-Subject: [PATCH] media: hantro: add support for reset lines
-
-Some SoCs like Allwinner H6 use reset lines for resetting Hantro G2. Add
-support for them.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h     |  3 +++
- drivers/staging/media/hantro/hantro_drv.c | 15 ++++++++++++++-
- 2 files changed, 17 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index 7da23f7f207a..33eb3e092cc1 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -16,6 +16,7 @@
- #include <linux/videodev2.h>
- #include <linux/wait.h>
- #include <linux/clk.h>
-+#include <linux/reset.h>
- 
- #include <media/v4l2-ctrls.h>
- #include <media/v4l2-device.h>
-@@ -171,6 +172,7 @@ hantro_vdev_to_func(struct video_device *vdev)
-  * @dev:		Pointer to device for convenient logging using
-  *			dev_ macros.
-  * @clocks:		Array of clock handles.
-+ * @resets:		Array of reset handles.
-  * @reg_bases:		Mapped addresses of VPU registers.
-  * @enc_base:		Mapped address of VPU encoder register for convenience.
-  * @dec_base:		Mapped address of VPU decoder register for convenience.
-@@ -190,6 +192,7 @@ struct hantro_dev {
- 	struct platform_device *pdev;
- 	struct device *dev;
- 	struct clk_bulk_data *clocks;
-+	struct reset_control *resets;
- 	void __iomem **reg_bases;
- 	void __iomem *enc_base;
- 	void __iomem *dec_base;
-diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
-index 3d3107a39dae..770f4ce71d29 100644
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -905,6 +905,10 @@ static int hantro_probe(struct platform_device *pdev)
- 			return PTR_ERR(vpu->clocks[0].clk);
- 	}
- 
-+	vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true);
-+	if (IS_ERR(vpu->resets))
-+		return PTR_ERR(vpu->resets);
-+
- 	num_bases = vpu->variant->num_regs ?: 1;
- 	vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
- 				      sizeof(*vpu->reg_bases), GFP_KERNEL);
-@@ -978,10 +982,16 @@ static int hantro_probe(struct platform_device *pdev)
- 	pm_runtime_use_autosuspend(vpu->dev);
- 	pm_runtime_enable(vpu->dev);
- 
-+	ret = reset_control_deassert(vpu->resets);
-+	if (ret) {
-+		dev_err(&pdev->dev, "Failed to deassert resets\n");
-+		goto err_pm_disable;
-+	}
-+
- 	ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
- 	if (ret) {
- 		dev_err(&pdev->dev, "Failed to prepare clocks\n");
--		goto err_pm_disable;
-+		goto err_rst_assert;
- 	}
- 
- 	ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
-@@ -1037,6 +1047,8 @@ static int hantro_probe(struct platform_device *pdev)
- 	v4l2_device_unregister(&vpu->v4l2_dev);
- err_clk_unprepare:
- 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
-+err_rst_assert:
-+	reset_control_assert(vpu->resets);
- err_pm_disable:
- 	pm_runtime_dont_use_autosuspend(vpu->dev);
- 	pm_runtime_disable(vpu->dev);
-@@ -1056,6 +1068,7 @@ static int hantro_remove(struct platform_device *pdev)
- 	v4l2_m2m_release(vpu->m2m_dev);
- 	v4l2_device_unregister(&vpu->v4l2_dev);
- 	clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
-+	reset_control_assert(vpu->resets);
- 	pm_runtime_dont_use_autosuspend(vpu->dev);
- 	pm_runtime_disable(vpu->dev);
- 	return 0;

projects/NXP/devices/iMX8/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch

@@ -1,63 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sun, 21 Nov 2021 20:39:11 +0100
-Subject: [PATCH] media: hantro: vp9: use double buffering if needed
-
-Some G2 variants need double buffering to be enabled in order to work
-correctly, like that found in Allwinner H6 SoC.
-
-Add platform quirk for that.
-
-Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h            | 2 ++
- drivers/staging/media/hantro/hantro_g2_regs.h    | 1 +
- drivers/staging/media/hantro/hantro_g2_vp9_dec.c | 2 ++
- 3 files changed, 5 insertions(+)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index 33eb3e092cc1..d03824fa3222 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -73,6 +73,7 @@ struct hantro_irq {
-  * @num_clocks:			number of clocks in the array
-  * @reg_names:			array of register range names
-  * @num_regs:			number of register range names in the array
-+ * @double_buffer:		core needs double buffering
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -94,6 +95,7 @@ struct hantro_variant {
- 	int num_clocks;
- 	const char * const *reg_names;
- 	int num_regs;
-+	unsigned int double_buffer : 1;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index 9c857dd1ad9b..15a391a4650e 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -270,6 +270,7 @@
- #define g2_apf_threshold	G2_DEC_REG(55, 0, 0xffff)
- 
- #define g2_clk_gate_e		G2_DEC_REG(58, 16, 0x1)
-+#define g2_double_buffer_e	G2_DEC_REG(58, 15, 0x1)
- #define g2_buswidth		G2_DEC_REG(58, 8,  0x7)
- #define g2_max_burst		G2_DEC_REG(58, 0,  0xff)
- 
-diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-index e04242d10fa2..d4fc649a4da1 100644
---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-@@ -847,6 +847,8 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p
- 	hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1);
- 	hantro_reg_write(ctx->dev, &g2_max_cb_size, 6);
- 	hantro_reg_write(ctx->dev, &g2_min_cb_size, 3);
-+	if (ctx->dev->variant->double_buffer)
-+		hantro_reg_write(ctx->dev, &g2_double_buffer_e, 1);
- 
- 	config_output(ctx, dst, dec_params);
- 

projects/NXP/devices/iMX8/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch

@@ -1,242 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Sun, 26 Sep 2021 19:47:03 +0200
-Subject: [PATCH] media: hantro: vp9: add support for legacy register set
-
-Some older G2 cores uses slightly different register set for HEVC and
-VP9. Since vast majority of registers and logic is the same, it doesn't
-make sense to introduce another drivers.
-
-Add legacy_regs quirk and implement only VP9 changes for now. HEVC
-changes will be introduced later, if needed.
-
-Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h         |  2 +
- drivers/staging/media/hantro/hantro_g2_regs.h | 16 ++++
- .../staging/media/hantro/hantro_g2_vp9_dec.c  | 74 ++++++++++++++-----
- 3 files changed, 75 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index d03824fa3222..83ed25d9657b 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -74,6 +74,7 @@ struct hantro_irq {
-  * @reg_names:			array of register range names
-  * @num_regs:			number of register range names in the array
-  * @double_buffer:		core needs double buffering
-+ * @legacy_regs:		core uses legacy register set
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -96,6 +97,7 @@ struct hantro_variant {
- 	const char * const *reg_names;
- 	int num_regs;
- 	unsigned int double_buffer : 1;
-+	unsigned int legacy_regs : 1;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h
-index 15a391a4650e..b7c6f9877b9d 100644
---- a/drivers/staging/media/hantro/hantro_g2_regs.h
-+++ b/drivers/staging/media/hantro/hantro_g2_regs.h
-@@ -36,7 +36,13 @@
- #define BUS_WIDTH_256			3
- 
- #define g2_strm_swap		G2_DEC_REG(2, 28, 0xf)
-+#define g2_strm_swap_old	G2_DEC_REG(2, 27, 0x1f)
-+#define g2_pic_swap		G2_DEC_REG(2, 22, 0x1f)
- #define g2_dirmv_swap		G2_DEC_REG(2, 20, 0xf)
-+#define g2_dirmv_swap_old	G2_DEC_REG(2, 17, 0x1f)
-+#define g2_tab0_swap_old	G2_DEC_REG(2, 12, 0x1f)
-+#define g2_tab1_swap_old	G2_DEC_REG(2, 7, 0x1f)
-+#define g2_tab2_swap_old	G2_DEC_REG(2, 2, 0x1f)
- 
- #define g2_mode			G2_DEC_REG(3, 27, 0x1f)
- #define g2_compress_swap	G2_DEC_REG(3, 20, 0xf)
-@@ -45,6 +51,8 @@
- #define g2_out_dis		G2_DEC_REG(3, 15, 0x1)
- #define g2_out_filtering_dis	G2_DEC_REG(3, 14, 0x1)
- #define g2_write_mvs_e		G2_DEC_REG(3, 12, 0x1)
-+#define g2_tab3_swap_old	G2_DEC_REG(3, 7, 0x1f)
-+#define g2_rscan_swap		G2_DEC_REG(3, 2, 0x1f)
- 
- #define g2_pic_width_in_cbs	G2_DEC_REG(4, 19, 0x1fff)
- #define g2_pic_height_in_cbs	G2_DEC_REG(4, 6,  0x1fff)
-@@ -58,6 +66,7 @@
- #define g2_tempor_mvp_e		G2_DEC_REG(5, 11, 0x1)
- #define g2_max_cu_qpd_depth	G2_DEC_REG(5, 5,  0x3f)
- #define g2_cu_qpd_e		G2_DEC_REG(5, 4,  0x1)
-+#define g2_pix_shift		G2_DEC_REG(5, 0,  0xf)
- 
- #define g2_stream_len		G2_DEC_REG(6, 0,  0xffffffff)
- 
-@@ -80,21 +89,28 @@
- 
- #define g2_const_intra_e	G2_DEC_REG(8, 31, 0x1)
- #define g2_filt_ctrl_pres	G2_DEC_REG(8, 30, 0x1)
-+#define g2_bit_depth_y		G2_DEC_REG(8, 21, 0xf)
-+#define g2_bit_depth_c		G2_DEC_REG(8, 17, 0xf)
- #define g2_idr_pic_e		G2_DEC_REG(8, 16, 0x1)
- #define g2_bit_depth_pcm_y	G2_DEC_REG(8, 12, 0xf)
- #define g2_bit_depth_pcm_c	G2_DEC_REG(8, 8,  0xf)
- #define g2_bit_depth_y_minus8	G2_DEC_REG(8, 6,  0x3)
- #define g2_bit_depth_c_minus8	G2_DEC_REG(8, 4,  0x3)
-+#define g2_rs_out_bit_depth	G2_DEC_REG(8, 4,  0xf)
- #define g2_output_8_bits	G2_DEC_REG(8, 3,  0x1)
- #define g2_output_format	G2_DEC_REG(8, 0,  0x7)
-+#define g2_pp_pix_shift		G2_DEC_REG(8, 0,  0xf)
- 
- #define g2_refidx1_active	G2_DEC_REG(9, 19, 0x1f)
- #define g2_refidx0_active	G2_DEC_REG(9, 14, 0x1f)
- #define g2_hdr_skip_length	G2_DEC_REG(9, 0,  0x3fff)
- 
- #define g2_start_code_e		G2_DEC_REG(10, 31, 0x1)
-+#define g2_init_qp_old		G2_DEC_REG(10, 25, 0x3f)
- #define g2_init_qp		G2_DEC_REG(10, 24, 0x3f)
-+#define g2_num_tile_cols_old	G2_DEC_REG(10, 20, 0x1f)
- #define g2_num_tile_cols	G2_DEC_REG(10, 19, 0x1f)
-+#define g2_num_tile_rows_old	G2_DEC_REG(10, 15, 0x1f)
- #define g2_num_tile_rows	G2_DEC_REG(10, 14, 0x1f)
- #define g2_tile_e		G2_DEC_REG(10, 1,  0x1)
- #define g2_entropy_sync_e	G2_DEC_REG(10, 0,  0x1)
-diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-index d4fc649a4da1..91c21b634fab 100644
---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c
-@@ -150,7 +150,8 @@ static void config_output(struct hantro_ctx *ctx,
- 	dma_addr_t luma_addr, chroma_addr, mv_addr;
- 
- 	hantro_reg_write(ctx->dev, &g2_out_dis, 0);
--	hantro_reg_write(ctx->dev, &g2_output_format, 0);
-+	if (!ctx->dev->variant->legacy_regs)
-+		hantro_reg_write(ctx->dev, &g2_output_format, 0);
- 
- 	luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
- 	hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr);
-@@ -327,6 +328,7 @@ config_tiles(struct hantro_ctx *ctx,
- 	struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge;
- 	dma_addr_t addr;
- 	unsigned short *tile_mem;
-+	unsigned int rows, cols;
- 
- 	addr = misc->dma + vp9_ctx->tile_info_offset;
- 	hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr);
-@@ -344,17 +346,24 @@ config_tiles(struct hantro_ctx *ctx,
- 
- 		fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem);
- 
-+		cols = tile_c;
-+		rows = tile_r;
- 		hantro_reg_write(ctx->dev, &g2_tile_e, 1);
--		hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c);
--		hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r);
--
- 	} else {
- 		tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width);
- 		tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height);
- 
-+		cols = 1;
-+		rows = 1;
- 		hantro_reg_write(ctx->dev, &g2_tile_e, 0);
--		hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1);
--		hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1);
-+	}
-+
-+	if (ctx->dev->variant->legacy_regs) {
-+		hantro_reg_write(ctx->dev, &g2_num_tile_cols_old, cols);
-+		hantro_reg_write(ctx->dev, &g2_num_tile_rows_old, rows);
-+	} else {
-+		hantro_reg_write(ctx->dev, &g2_num_tile_cols, cols);
-+		hantro_reg_write(ctx->dev, &g2_num_tile_rows, rows);
- 	}
- 
- 	/* provide aux buffers even if no tiles are used */
-@@ -505,8 +514,22 @@ static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_deco
- static void
- config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params)
- {
--	hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8);
--	hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8);
-+	if (ctx->dev->variant->legacy_regs) {
-+		u8 pp_shift = 0;
-+
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth);
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth);
-+		hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth);
-+
-+		if (dec_params->bit_depth > 8)
-+			pp_shift = 16 - dec_params->bit_depth;
-+
-+		hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift);
-+		hantro_reg_write(ctx->dev, &g2_pix_shift, 0);
-+	} else {
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8);
-+		hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8);
-+	}
- }
- 
- static inline bool is_lossless(const struct v4l2_vp9_quantization *quant)
-@@ -784,9 +807,13 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para
- 		     + dec_params->compressed_header_size;
- 
- 	stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0);
--	hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base);
- 
- 	tmp_addr = stream_base + headres_size;
-+	if (ctx->dev->variant->legacy_regs)
-+		hantro_write_addr(ctx->dev, G2_STREAM_ADDR, (tmp_addr & ~0xf));
-+	else
-+		hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base);
-+
- 	start_bit = (tmp_addr & 0xf) * 8;
- 	hantro_reg_write(ctx->dev, &g2_start_bit, start_bit);
- 
-@@ -794,10 +821,12 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para
- 	src_len += start_bit / 8 - headres_size;
- 	hantro_reg_write(ctx->dev, &g2_stream_len, src_len);
- 
--	tmp_addr &= ~0xf;
--	hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base);
--	src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0);
--	hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len);
-+	if (!ctx->dev->variant->legacy_regs) {
-+		tmp_addr &= ~0xf;
-+		hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base);
-+		src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0);
-+		hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len);
-+	}
- }
- 
- static void
-@@ -837,13 +866,24 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p
- 
- 	/* configure basic registers */
- 	hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE);
--	hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf);
--	hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf);
--	hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf);
-+	if (!ctx->dev->variant->legacy_regs) {
-+		hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf);
-+		hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf);
-+		hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf);
-+		hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1);
-+	} else {
-+		hantro_reg_write(ctx->dev, &g2_strm_swap_old, 0x1f);
-+		hantro_reg_write(ctx->dev, &g2_pic_swap, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_dirmv_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab0_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab1_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab2_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_tab3_swap_old, 0x10);
-+		hantro_reg_write(ctx->dev, &g2_rscan_swap, 0x10);
-+	}
- 	hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128);
- 	hantro_reg_write(ctx->dev, &g2_max_burst, 16);
- 	hantro_reg_write(ctx->dev, &g2_apf_threshold, 8);
--	hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1);
- 	hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1);
- 	hantro_reg_write(ctx->dev, &g2_max_cb_size, 6);
- 	hantro_reg_write(ctx->dev, &g2_min_cb_size, 3);

projects/NXP/devices/iMX8/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch

@@ -1,62 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Mon, 22 Nov 2021 18:33:14 +0100
-Subject: [PATCH] media: hantro: move postproc enablement for old cores
-
-Older G2 cores, like that in Allwinner H6, seem to have issue with
-latching postproc register values if this is first thing done in job.
-Moving that to the end solves the issue.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro.h     | 2 ++
- drivers/staging/media/hantro/hantro_drv.c | 9 ++++++++-
- 2 files changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
-index 83ed25d9657b..06d0f3597694 100644
---- a/drivers/staging/media/hantro/hantro.h
-+++ b/drivers/staging/media/hantro/hantro.h
-@@ -75,6 +75,7 @@ struct hantro_irq {
-  * @num_regs:			number of register range names in the array
-  * @double_buffer:		core needs double buffering
-  * @legacy_regs:		core uses legacy register set
-+ * @late_postproc:		postproc must be set up at the end of the job
-  */
- struct hantro_variant {
- 	unsigned int enc_offset;
-@@ -98,6 +99,7 @@ struct hantro_variant {
- 	int num_regs;
- 	unsigned int double_buffer : 1;
- 	unsigned int legacy_regs : 1;
-+	unsigned int late_postproc : 1;
- };
- 
- /**
-diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
-index 770f4ce71d29..33bf78be145b 100644
---- a/drivers/staging/media/hantro/hantro_drv.c
-+++ b/drivers/staging/media/hantro/hantro_drv.c
-@@ -130,7 +130,7 @@ void hantro_start_prepare_run(struct hantro_ctx *ctx)
- 	v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
- 				&ctx->ctrl_handler);
- 
--	if (!ctx->is_encoder) {
-+	if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) {
- 		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
- 			hantro_postproc_enable(ctx);
- 		else
-@@ -142,6 +142,13 @@ void hantro_end_prepare_run(struct hantro_ctx *ctx)
- {
- 	struct vb2_v4l2_buffer *src_buf;
- 
-+	if (!ctx->is_encoder && ctx->dev->variant->late_postproc) {
-+		if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
-+			hantro_postproc_enable(ctx);
-+		else
-+			hantro_postproc_disable(ctx);
-+	}
-+
- 	src_buf = hantro_get_src_buf(ctx);
- 	v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
- 				   &ctx->ctrl_handler);

projects/NXP/devices/iMX8/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch

@@ -1,92 +0,0 @@
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Jernej Skrabec <jernej.skrabec@gmail.com>
-Date: Mon, 29 Nov 2021 19:02:17 +0100
-Subject: [PATCH] media: hantro: Convert imx8m_vpu_g2_irq to helper
-
-It turns out that imx8m_vpu_g2_irq() doesn't depend on any platform
-specifics and can be used with other G2 platform drivers too.
-
-Move it to common code.
-
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- drivers/staging/media/hantro/hantro_g2.c    | 18 ++++++++++++++++++
- drivers/staging/media/hantro/hantro_hw.h    |  1 +
- drivers/staging/media/hantro/imx8m_vpu_hw.c | 20 +-------------------
- 3 files changed, 20 insertions(+), 19 deletions(-)
-
-diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c
-index 6f3e1f797f83..ee5f14c5f8f2 100644
---- a/drivers/staging/media/hantro/hantro_g2.c
-+++ b/drivers/staging/media/hantro/hantro_g2.c
-@@ -24,3 +24,21 @@ void hantro_g2_check_idle(struct hantro_dev *vpu)
- 		}
- 	}
- }
-+
-+irqreturn_t hantro_g2_irq(int irq, void *dev_id)
-+{
-+	struct hantro_dev *vpu = dev_id;
-+	enum vb2_buffer_state state;
-+	u32 status;
-+
-+	status = vdpu_read(vpu, G2_REG_INTERRUPT);
-+	state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ?
-+		 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
-+
-+	vdpu_write(vpu, 0, G2_REG_INTERRUPT);
-+	vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG);
-+
-+	hantro_irq_done(vpu, state);
-+
-+	return IRQ_HANDLED;
-+}
-diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
-index dbe51303724b..c33b1f5df37b 100644
---- a/drivers/staging/media/hantro/hantro_hw.h
-+++ b/drivers/staging/media/hantro/hantro_hw.h
-@@ -413,5 +413,6 @@ void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx);
- int hantro_vp9_dec_init(struct hantro_ctx *ctx);
- void hantro_vp9_dec_exit(struct hantro_ctx *ctx);
- void hantro_g2_check_idle(struct hantro_dev *vpu);
-+irqreturn_t hantro_g2_irq(int irq, void *dev_id);
- 
- #endif /* HANTRO_HW_H_ */
-diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-index 1a43f6fceef9..f5991b8e553a 100644
---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
-+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
-@@ -191,24 +191,6 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
- 	return IRQ_HANDLED;
- }
- 
--static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id)
--{
--	struct hantro_dev *vpu = dev_id;
--	enum vb2_buffer_state state;
--	u32 status;
--
--	status = vdpu_read(vpu, G2_REG_INTERRUPT);
--	state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ?
--		 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
--
--	vdpu_write(vpu, 0, G2_REG_INTERRUPT);
--	vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG);
--
--	hantro_irq_done(vpu, state);
--
--	return IRQ_HANDLED;
--}
--
- static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
- {
- 	vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];
-@@ -280,7 +262,7 @@ static const struct hantro_irq imx8mq_irqs[] = {
- };
- 
- static const struct hantro_irq imx8mq_g2_irqs[] = {
--	{ "g2", imx8m_vpu_g2_irq },
-+	{ "g2", hantro_g2_irq },
- };
- 
- static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };

projects/NXP/devices/iMX8/patches/linux/0090-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch

@@ -1,3 +1,109 @@
+From mboxrd@z Thu Jan  1 00:00:00 1970
+Return-Path: <linux-kernel-owner@kernel.org>
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+Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:6592:b6fe:71b1:9f4c])
+        by smtp.gmail.com with ESMTPSA id m14sm8090291iov.0.2022.01.25.09.12.22
+        (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
+        Tue, 25 Jan 2022 09:12:22 -0800 (PST)
+From:   Adam Ford <aford173@gmail.com>
+To:     linux-media@vger.kernel.org
+Cc:     aford@beaconembedded.com, cphealy@gmail.com,
+        Adam Ford <aford173@gmail.com>,
+        Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
+        Philipp Zabel <p.zabel@pengutronix.de>,
+        Mauro Carvalho Chehab <mchehab@kernel.org>,
+        Rob Herring <robh+dt@kernel.org>,
+        Shawn Guo <shawnguo@kernel.org>,
+        Sascha Hauer <s.hauer@pengutronix.de>,
+        Pengutronix Kernel Team <kernel@pengutronix.de>,
+        Fabio Estevam <festevam@gmail.com>,
+        NXP Linux Team <linux-imx@nxp.com>,
+        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
+        Lucas Stach <l.stach@pengutronix.de>,
+        linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
+        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
+        linux-staging@lists.linux.dev
+Subject: [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference
+Date:   Tue, 25 Jan 2022 11:11:18 -0600
+Message-Id: <20220125171129.472775-2-aford173@gmail.com>
+X-Mailer: git-send-email 2.32.0
+In-Reply-To: <20220125171129.472775-1-aford173@gmail.com>
+References: <20220125171129.472775-1-aford173@gmail.com>
+MIME-Version: 1.0
+Content-Transfer-Encoding: 8bit
+Precedence: bulk
+List-ID: <linux-kernel.vger.kernel.org>
+X-Mailing-List: linux-kernel@vger.kernel.org
+
+The vpu is enabled by default, so there is no need to manually
+enable it.
+
+Signed-off-by: Adam Ford <aford173@gmail.com>
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
+index 8aedcddfeab8..38ffcd145b33 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
+@@ -272,10 +272,6 @@ &usdhc1 {
+ 	status = "okay";
+ };
+ 
+-&vpu {
+-	status = "okay";
+-};
+-
+ /* Attention: wdog reset forcing POR needs baseboard support */
+ &wdog1 {
+ 	status = "okay";
+-- 
+2.32.0
+
+
 From mboxrd@z Thu Jan  1 00:00:00 1970
 Return-Path: <linux-media-owner@kernel.org>
 X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
@@ -376,8 +482,8 @@ index 511e74f0db8a..122f9c884b38 100644
 --- a/drivers/soc/imx/imx8m-blk-ctrl.c
 +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
 @@ -15,6 +15,7 @@
- 
  #include <dt-bindings/power/imx8mm-power.h>
+ #include <dt-bindings/power/imx8mn-power.h>
 +#include <dt-bindings/power/imx8mq-power.h>
  
  #define BLK_SFT_RSTN	0x0
@@ -453,12 +559,12 @@ index 511e74f0db8a..122f9c884b38 100644
  	{
  		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
 @@ -599,6 +662,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
- 		.compatible = "fsl,imx8mm-disp-blk-ctrl",
+ 		.compatible = "fsl,imx8mn-disp-blk-ctrl",
- 		.data = &imx8mm_disp_blk_ctl_dev_data
+ 		.data = &imx8mn_disp_blk_ctl_dev_data
- 	} ,{
+ 	}, {
 +		.compatible = "fsl,imx8mq-vpu-blk-ctrl",
 +		.data = &imx8mq_vpu_blk_ctl_dev_data
-+	} ,{
++	}, {
  		/* Sentinel */
  	}
  };

projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.16.0-rc8 Kernel Configuration
+# Linux/arm64 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621"
 CONFIG_CC_IS_GCC=y
@@ -223,7 +223,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -436,6 +435,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y
 #
 # ARMv8.2 architectural features
 #
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
 # CONFIG_ARM64_PMEM is not set
 # CONFIG_ARM64_RAS_EXTN is not set
 # CONFIG_ARM64_CNP is not set
@@ -602,6 +603,7 @@ CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
 CONFIG_HAVE_ACPI_APEI=y
 # CONFIG_ACPI_APEI is not set
 # CONFIG_ACPI_CONFIGFS is not set
+# CONFIG_ACPI_PFRUT is not set
 CONFIG_ACPI_IORT=y
 CONFIG_ACPI_GTDT=y
 CONFIG_ACPI_PPTT=y
@@ -701,6 +703,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -850,7 +853,6 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
 # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-# CONFIG_CLEANCACHE is not set
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
@@ -870,6 +872,7 @@ CONFIG_ZONE_DMA32=y
 # CONFIG_READ_ONLY_THP_FOR_FS is not set
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1018,7 +1021,6 @@ CONFIG_NF_TABLES=m
 # CONFIG_NF_TABLES_NETDEV is not set
 # CONFIG_NFT_NUMGEN is not set
 # CONFIG_NFT_CT is not set
-# CONFIG_NFT_COUNTER is not set
 # CONFIG_NFT_CONNLIMIT is not set
 # CONFIG_NFT_LOG is not set
 # CONFIG_NFT_LIMIT is not set
@@ -1577,6 +1579,7 @@ CONFIG_PCIE_QCOM=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1810,7 +1813,6 @@ CONFIG_XEN_BLKDEV_FRONTEND=y
 # CONFIG_XEN_BLKDEV_BACKEND is not set
 CONFIG_VIRTIO_BLK=y
 # CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
 
 #
 # NVME Support
@@ -2191,6 +2193,7 @@ CONFIG_NET_VENDOR_DLINK=y
 # CONFIG_SUNDANCE is not set
 CONFIG_NET_VENDOR_EMULEX=y
 # CONFIG_BE2NET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 CONFIG_NET_VENDOR_EZCHIP=y
 # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set
 CONFIG_NET_VENDOR_GOOGLE=y
@@ -2328,6 +2331,7 @@ CONFIG_NET_VENDOR_TEHUTI=y
 CONFIG_NET_VENDOR_TI=y
 # CONFIG_TI_CPSW_PHY_SEL is not set
 # CONFIG_TLAN is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 CONFIG_NET_VENDOR_VIA=y
 # CONFIG_VIA_RHINE is not set
 # CONFIG_VIA_VELOCITY is not set
@@ -2787,6 +2791,7 @@ CONFIG_SERIAL_8250_DWLIB=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_DW=y
 # CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_PERICOM is not set
 CONFIG_SERIAL_OF_PLATFORM=y
 
 #
@@ -2843,6 +2848,7 @@ CONFIG_HW_RANDOM_CAVIUM=m
 # CONFIG_HW_RANDOM_CCTRNG is not set
 # CONFIG_HW_RANDOM_XIPHERA is not set
 CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
+# CONFIG_HW_RANDOM_CN10K is not set
 # CONFIG_APPLICOM is not set
 CONFIG_DEVMEM=y
 CONFIG_DEVPORT=y
@@ -3045,13 +3051,13 @@ CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
 # CONFIG_PINCTRL_AMD is not set
-# CONFIG_PINCTRL_MCP23S08 is not set
-CONFIG_PINCTRL_SINGLE=y
-# CONFIG_PINCTRL_SX150X is not set
-# CONFIG_PINCTRL_STMFX is not set
 CONFIG_PINCTRL_MAX77620=y
-# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_MCP23S08 is not set
 # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_SINGLE=y
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
 CONFIG_PINCTRL_MSM=y
 CONFIG_PINCTRL_APQ8064=y
 CONFIG_PINCTRL_APQ8084=y
@@ -3085,9 +3091,11 @@ CONFIG_PINCTRL_QCOM_SSBI_PMIC=y
 # CONFIG_PINCTRL_SM6115 is not set
 # CONFIG_PINCTRL_SM6125 is not set
 # CONFIG_PINCTRL_SM6350 is not set
+# CONFIG_PINCTRL_SDX65 is not set
 # CONFIG_PINCTRL_SM8150 is not set
 # CONFIG_PINCTRL_SM8250 is not set
 # CONFIG_PINCTRL_SM8350 is not set
+# CONFIG_PINCTRL_SM8450 is not set
 # CONFIG_PINCTRL_LPASS_LPI is not set
 
 #
@@ -3182,6 +3190,7 @@ CONFIG_GPIO_MAX77620=y
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
 # CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -3225,6 +3234,7 @@ CONFIG_BATTERY_BQ27XXX_I2C=y
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_QCOM_SMBB is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
@@ -3428,7 +3438,6 @@ CONFIG_MFD_SYSCON=y
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -3470,6 +3479,7 @@ CONFIG_REGULATOR_MAX77620=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MCP16502 is not set
 # CONFIG_REGULATOR_MP5416 is not set
@@ -3792,6 +3802,7 @@ CONFIG_VIDEO_IR_I2C=y
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -3906,7 +3917,8 @@ CONFIG_DRM_I2C_SIL164=m
 # CONFIG_DRM_AST is not set
 # CONFIG_DRM_MGAG200 is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 # CONFIG_DRM_QXL is not set
 # CONFIG_DRM_VIRTIO_GPU is not set
 CONFIG_DRM_MSM=y
@@ -3929,6 +3941,7 @@ CONFIG_DRM_PANEL=y
 # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
 # CONFIG_DRM_PANEL_ARM_VERSATILE is not set
 # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
 # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
 # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
 # CONFIG_DRM_PANEL_DSI_CM is not set
@@ -3943,6 +3956,7 @@ CONFIG_DRM_PANEL_EDP=y
 # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
 # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
 # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
 # CONFIG_DRM_PANEL_KHADAS_TS050 is not set
 # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
 # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
@@ -3952,6 +3966,7 @@ CONFIG_DRM_PANEL_EDP=y
 # CONFIG_DRM_PANEL_LG_LG4573 is not set
 # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
 # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
@@ -3983,6 +3998,7 @@ CONFIG_DRM_PANEL_EDP=y
 # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
 # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
 # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
 # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
 # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
 # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
@@ -4046,6 +4062,7 @@ CONFIG_DRM_I2C_ADV7511_CEC=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -4061,6 +4078,7 @@ CONFIG_DRM_I2C_ADV7511_CEC=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -4277,6 +4295,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y
 CONFIG_SND_SOC=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -4338,6 +4357,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 CONFIG_SND_SOC_AK4613=y
@@ -4434,6 +4454,7 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -4553,6 +4574,7 @@ CONFIG_HID_KENSINGTON=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 # CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=m
 # CONFIG_HID_LOGITECH_HIDPP is not set
 # CONFIG_LOGITECH_FF is not set
@@ -4675,6 +4697,7 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
 # CONFIG_USB_HCD_TEST_MODE is not set
+# CONFIG_USB_XEN_HCD is not set
 
 #
 # USB Device Class drivers
@@ -5071,6 +5094,10 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_SUPPORT=y
@@ -5335,6 +5362,7 @@ CONFIG_COMMON_CLK_SCPI=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 CONFIG_COMMON_CLK_CS2000_CP=y
+# CONFIG_COMMON_CLK_LAN966X is not set
 CONFIG_COMMON_CLK_S2MPS11=y
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 CONFIG_COMMON_CLK_XGENE=y
@@ -5368,6 +5396,7 @@ CONFIG_MSM_MMCC_8960=y
 # CONFIG_MSM_GCC_8953 is not set
 CONFIG_MSM_GCC_8974=y
 CONFIG_MSM_MMCC_8974=y
+# CONFIG_MSM_GCC_8976 is not set
 # CONFIG_MSM_MMCC_8994 is not set
 CONFIG_MSM_GCC_8994=y
 CONFIG_MSM_GCC_8996=y
@@ -5404,12 +5433,14 @@ CONFIG_MSM_MMCC_8996=y
 # CONFIG_SDM_LPASSCC_845 is not set
 # CONFIG_SDX_GCC_55 is not set
 # CONFIG_SM_CAMCC_8250 is not set
+# CONFIG_SDX_GCC_65 is not set
 # CONFIG_SM_GCC_6115 is not set
 # CONFIG_SM_GCC_6125 is not set
 # CONFIG_SM_GCC_6350 is not set
 # CONFIG_SM_GCC_8150 is not set
 # CONFIG_SM_GCC_8250 is not set
 # CONFIG_SM_GCC_8350 is not set
+# CONFIG_SM_GCC_8450 is not set
 # CONFIG_SM_GPUCC_8150 is not set
 # CONFIG_SM_GPUCC_8250 is not set
 # CONFIG_SM_VIDEOCC_8150 is not set
@@ -5717,6 +5748,12 @@ CONFIG_IIO=y
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5772,6 +5809,7 @@ CONFIG_IIO=y
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5791,6 +5829,7 @@ CONFIG_IIO=y
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5814,6 +5853,12 @@ CONFIG_IIO=y
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5829,6 +5874,7 @@ CONFIG_IIO=y
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -6120,12 +6166,15 @@ CONFIG_PHY_XGENE=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
 CONFIG_PHY_QCOM_APQ8064_SATA=y
+# CONFIG_PHY_QCOM_EDP is not set
 # CONFIG_PHY_QCOM_IPQ4019_USB is not set
 CONFIG_PHY_QCOM_IPQ806X_SATA=y
 # CONFIG_PHY_QCOM_PCIE2 is not set
@@ -6158,7 +6207,9 @@ CONFIG_ARM_PMU_ACPI=y
 # CONFIG_QCOM_L3_PMU is not set
 # CONFIG_ARM_SPE_PMU is not set
 # CONFIG_ARM_DMC620_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
 # CONFIG_HISI_PMU is not set
+# CONFIG_HISI_PCIE_PMU is not set
 # end of Performance monitor support
 
 CONFIG_RAS=y
@@ -6650,6 +6701,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6658,25 +6710,6 @@ CONFIG_CRYPTO_USER_API_RNG=y
 CONFIG_CRYPTO_USER_API_AEAD=y
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_BLAKE2S=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
-CONFIG_CRYPTO_LIB_CURVE25519=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
 # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
@@ -6726,7 +6759,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 # CONFIG_CORDIC is not set
 # CONFIG_PRIME_NUMBERS is not set
 CONFIG_RATIONAL=y
@@ -6735,6 +6767,26 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
 # CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
@@ -6903,6 +6955,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -7059,12 +7118,12 @@ CONFIG_CORESIGHT_SOURCE_ETM4X=y
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_ARCH_HAS_KCOV=y
 CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
 CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_LKDTM is not set
 # CONFIG_TEST_MIN_HEAP is not set
 # CONFIG_TEST_DIV64 is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_REED_SOLOMON_TEST is not set
 # CONFIG_INTERVAL_TREE_TEST is not set
@@ -7082,7 +7141,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_XARRAY is not set
 # CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_IDA is not set
 # CONFIG_TEST_LKM is not set
 # CONFIG_TEST_BITOPS is not set

projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 5.16.0-rc8 Kernel Configuration
+# Linux/arm 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0"
 CONFIG_CC_IS_GCC=y
@@ -217,7 +217,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -660,6 +659,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
 CONFIG_HAVE_EXIT_THREAD=y
 CONFIG_ARCH_MMAP_RND_BITS=8
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -802,13 +802,12 @@ CONFIG_CONTIG_ALLOC=y
 CONFIG_BOUNCE=y
 # CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
 # CONFIG_CMA_SYSFS is not set
 CONFIG_CMA_AREAS=7
+# CONFIG_ZSWAP is not set
 # CONFIG_ZPOOL is not set
 # CONFIG_ZSMALLOC is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y
@@ -817,6 +816,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
 # CONFIG_GUP_TEST is not set
 CONFIG_KMAP_LOCAL=y
 CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1103,6 +1103,7 @@ CONFIG_HAVE_PCI=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1408,7 +1409,6 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_ISCSI_BOOT_SYSFS is not set
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_UFS_HWMON is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_VIRTIO is not set
 # CONFIG_SCSI_DH is not set
@@ -1485,6 +1485,7 @@ CONFIG_ETHERNET=y
 # CONFIG_NET_VENDOR_CORTINA is not set
 # CONFIG_DM9000 is not set
 # CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 # CONFIG_NET_VENDOR_EZCHIP is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 CONFIG_NET_VENDOR_GOOGLE=y
@@ -1520,6 +1521,7 @@ CONFIG_DWMAC_GENERIC=y
 CONFIG_DWMAC_ROCKCHIP=y
 # CONFIG_DWMAC_INTEL_PLAT is not set
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_NET_VENDOR_XILINX is not set
@@ -2009,7 +2011,6 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_8250_DWLIB=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_EM=y
 # CONFIG_SERIAL_8250_RT288X is not set
 CONFIG_SERIAL_OF_PLATFORM=y
 
@@ -2222,14 +2223,14 @@ CONFIG_GENERIC_PINCONF=y
 CONFIG_PINCTRL_AS3722=y
 # CONFIG_PINCTRL_AXP209 is not set
 # CONFIG_PINCTRL_MCP23S08 is not set
-CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
-# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_OCELOT is not set
-# CONFIG_PINCTRL_SX150X is not set
-# CONFIG_PINCTRL_STMFX is not set
 CONFIG_PINCTRL_PALMAS=y
 # CONFIG_PINCTRL_RK805 is not set
-# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_ROCKCHIP=y
-# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
 
 #
 # Renesas pinctrl drivers
@@ -2318,6 +2319,7 @@ CONFIG_GPIO_TPS65910=y
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
 # CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2352,6 +2354,7 @@ CONFIG_BATTERY_CPCAP=y
 # CONFIG_CHARGER_MAX14577 is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
 # CONFIG_CHARGER_MAX77693 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_MAX8997 is not set
 # CONFIG_CHARGER_MAX8998 is not set
 # CONFIG_CHARGER_BQ2415X is not set
@@ -2479,6 +2482,7 @@ CONFIG_SENSORS_LM90=y
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -2507,6 +2511,7 @@ CONFIG_SENSORS_PWM_FAN=m
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -2711,7 +2716,6 @@ CONFIG_MFD_WL1273_CORE=m
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -2766,6 +2770,7 @@ CONFIG_REGULATOR_MAX8907=y
 # CONFIG_REGULATOR_MAX8973 is not set
 CONFIG_REGULATOR_MAX8997=m
 CONFIG_REGULATOR_MAX8998=m
+# CONFIG_REGULATOR_MAX20086 is not set
 CONFIG_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_MAX77693=m
 CONFIG_REGULATOR_MAX77802=m
@@ -3191,6 +3196,7 @@ CONFIG_VIDEO_OV2640=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -3478,7 +3484,8 @@ CONFIG_ROCKCHIP_DW_HDMI=y
 # CONFIG_DRM_ARMADA is not set
 # CONFIG_DRM_ATMEL_HLCDC is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 # CONFIG_DRM_OMAP is not set
 # CONFIG_DRM_TILCDC is not set
 # CONFIG_DRM_VIRTIO_GPU is not set
@@ -3495,6 +3502,7 @@ CONFIG_DRM_PANEL=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_DRM_PANEL_EDP=y
 # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
 # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
 # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
 # CONFIG_DRM_PANEL_LG_LB035Q02 is not set
@@ -3571,6 +3579,7 @@ CONFIG_DRM_DW_HDMI_CEC=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -3587,6 +3596,7 @@ CONFIG_DRM_PANFROST=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -3714,6 +3724,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -3776,6 +3787,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 # CONFIG_SND_SOC_AK4613 is not set
@@ -3879,6 +3891,7 @@ CONFIG_SND_SOC_STI_SAS=m
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -4001,6 +4014,7 @@ CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LCPOWER=y
 # CONFIG_HID_LED is not set
 CONFIG_HID_LENOVO=y
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 CONFIG_HID_LOGITECH_DJ=y
 CONFIG_HID_LOGITECH_HIDPP=y
@@ -4483,6 +4497,10 @@ CONFIG_LEDS_TRIGGER_CAMERA=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_ATOMIC_SCRUB=y
@@ -4749,6 +4767,7 @@ CONFIG_R8188EU=m
 CONFIG_STAGING_MEDIA=y
 CONFIG_VIDEO_HANTRO=m
 CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+# CONFIG_VIDEO_MAX96712 is not set
 CONFIG_VIDEO_ROCKCHIP_VDEC=m
 
 #
@@ -4807,6 +4826,7 @@ CONFIG_COMMON_CLK_SCPI=m
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 # CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
 CONFIG_COMMON_CLK_S2MPS11=m
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 # CONFIG_COMMON_CLK_PALMAS is not set
@@ -5101,6 +5121,12 @@ CONFIG_VF610_ADC=m
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5161,6 +5187,7 @@ CONFIG_VF610_ADC=m
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5180,6 +5207,7 @@ CONFIG_VF610_ADC=m
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5203,6 +5231,11 @@ CONFIG_VF610_ADC=m
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5218,6 +5251,7 @@ CONFIG_VF610_ADC=m
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -5512,8 +5546,10 @@ CONFIG_GENERIC_PHY=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -6057,6 +6093,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=m
 CONFIG_CRYPTO_JITTERENTROPY=m
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6066,27 +6103,6 @@ CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 # CONFIG_CRYPTO_STATS is not set
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
 # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
@@ -6132,6 +6148,28 @@ CONFIG_CORDIC=m
 CONFIG_RATIONAL=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
@@ -6279,6 +6317,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -6307,6 +6352,8 @@ CONFIG_HAVE_ARCH_KASAN=y
 CONFIG_CC_HAS_KASAN_GENERIC=y
 CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
 # CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
 # end of Memory Debugging
 
 # CONFIG_DEBUG_SHIRQ is not set
@@ -6391,6 +6438,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
 CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
 CONFIG_TRACE_CLOCK=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
@@ -6458,6 +6506,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_MIN_HEAP is not set
 # CONFIG_TEST_DIV64 is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_REED_SOLOMON_TEST is not set
 # CONFIG_INTERVAL_TREE_TEST is not set
@@ -6475,7 +6524,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_XARRAY is not set
 # CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_IDA is not set
 # CONFIG_TEST_LKM is not set
 # CONFIG_TEST_BITOPS is not set

projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.16.0-rc8 Kernel Configuration
+# Linux/arm64 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621"
 CONFIG_CC_IS_GCC=y
@@ -221,7 +221,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -430,6 +429,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y
 #
 # ARMv8.2 architectural features
 #
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
 # CONFIG_ARM64_PMEM is not set
 # CONFIG_ARM64_RAS_EXTN is not set
 # CONFIG_ARM64_CNP is not set
@@ -652,6 +653,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -866,13 +868,12 @@ CONFIG_MEMORY_FAILURE=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
 # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
 # CONFIG_CMA_SYSFS is not set
 CONFIG_CMA_AREAS=7
+# CONFIG_ZSWAP is not set
 # CONFIG_ZPOOL is not set
 # CONFIG_ZSMALLOC is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y
@@ -887,6 +888,7 @@ CONFIG_ZONE_DMA32=y
 # CONFIG_READ_ONLY_THP_FOR_FS is not set
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1342,6 +1344,7 @@ CONFIG_HAVE_PCI=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1636,7 +1639,6 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_ISCSI_BOOT_SYSFS is not set
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_UFS_HWMON is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_VIRTIO is not set
 # CONFIG_SCSI_DH is not set
@@ -1684,6 +1686,7 @@ CONFIG_ETHERNET=y
 # CONFIG_NET_VENDOR_CAVIUM is not set
 # CONFIG_NET_VENDOR_CORTINA is not set
 # CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 # CONFIG_NET_VENDOR_EZCHIP is not set
 CONFIG_NET_VENDOR_GOOGLE=y
 # CONFIG_NET_VENDOR_HISILICON is not set
@@ -1718,6 +1721,7 @@ CONFIG_DWMAC_GENERIC=y
 CONFIG_DWMAC_ROCKCHIP=y
 # CONFIG_DWMAC_INTEL_PLAT is not set
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_NET_VENDOR_XILINX is not set
@@ -2398,15 +2402,15 @@ CONFIG_PINMUX=y
 CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
+CONFIG_PINCTRL_MAX77620=y
 # CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_RK805=y
 CONFIG_PINCTRL_ROCKCHIP=y
 # CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PINCTRL_SX150X is not set
 # CONFIG_PINCTRL_STMFX is not set
-CONFIG_PINCTRL_MAX77620=y
+# CONFIG_PINCTRL_SX150X is not set
-CONFIG_PINCTRL_RK805=y
-# CONFIG_PINCTRL_OCELOT is not set
-# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
 
 #
 # Renesas pinctrl drivers
@@ -2488,6 +2492,7 @@ CONFIG_GPIO_MAX77620=y
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
 # CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2529,6 +2534,7 @@ CONFIG_POWER_SUPPLY_HWMON=y
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
 # CONFIG_CHARGER_BQ24257 is not set
@@ -2649,6 +2655,7 @@ CONFIG_SENSORS_LM90=m
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -2677,6 +2684,7 @@ CONFIG_SENSORS_PWM_FAN=m
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -2865,7 +2873,6 @@ CONFIG_MFD_WL1273_CORE=m
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -2908,6 +2915,7 @@ CONFIG_REGULATOR_GPIO=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MCP16502 is not set
 # CONFIG_REGULATOR_MP5416 is not set
@@ -3272,6 +3280,7 @@ CONFIG_VIDEO_OV2640=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -3555,7 +3564,8 @@ CONFIG_ROCKCHIP_DW_HDMI=y
 # CONFIG_ROCKCHIP_RK3066_HDMI is not set
 # CONFIG_DRM_UDL is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 # CONFIG_DRM_VIRTIO_GPU is not set
 CONFIG_DRM_PANEL=y
 
@@ -3568,6 +3578,7 @@ CONFIG_DRM_PANEL=y
 # CONFIG_DRM_PANEL_SIMPLE is not set
 CONFIG_DRM_PANEL_EDP=y
 # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
 # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
 # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
 # CONFIG_DRM_PANEL_LG_LB035Q02 is not set
@@ -3643,6 +3654,7 @@ CONFIG_DRM_DW_HDMI_CEC=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -3657,6 +3669,7 @@ CONFIG_DRM_LIMA=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -3782,6 +3795,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -3843,6 +3857,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 CONFIG_SND_SOC_AK4613=m
@@ -3947,6 +3962,7 @@ CONFIG_SND_SOC_SPDIF=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -4068,6 +4084,7 @@ CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LCPOWER=y
 # CONFIG_HID_LED is not set
 CONFIG_HID_LENOVO=y
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 CONFIG_HID_LOGITECH_DJ=y
 CONFIG_HID_LOGITECH_HIDPP=y
@@ -4500,6 +4517,10 @@ CONFIG_LEDS_TRIGGER_PANIC=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_SUPPORT=y
@@ -4762,6 +4783,7 @@ CONFIG_R8188EU=m
 CONFIG_STAGING_MEDIA=y
 CONFIG_VIDEO_HANTRO=m
 CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+# CONFIG_VIDEO_MAX96712 is not set
 CONFIG_VIDEO_ROCKCHIP_VDEC=m
 
 #
@@ -4784,6 +4806,7 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m
 CONFIG_CHROME_PLATFORMS=y
 # CONFIG_CROS_EC is not set
 # CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CLK_PREPARE=y
 CONFIG_COMMON_CLK=y
@@ -4808,6 +4831,7 @@ CONFIG_COMMON_CLK_SCPI=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 CONFIG_COMMON_CLK_CS2000_CP=y
+# CONFIG_COMMON_CLK_LAN966X is not set
 CONFIG_COMMON_CLK_S2MPS11=y
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 CONFIG_COMMON_CLK_XGENE=y
@@ -5095,6 +5119,12 @@ CONFIG_ROCKCHIP_SARADC=y
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5152,6 +5182,7 @@ CONFIG_ROCKCHIP_SARADC=y
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5171,6 +5202,7 @@ CONFIG_ROCKCHIP_SARADC=y
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5194,6 +5226,12 @@ CONFIG_ROCKCHIP_SARADC=y
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5209,6 +5247,7 @@ CONFIG_ROCKCHIP_SARADC=y
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -5499,8 +5538,10 @@ CONFIG_GENERIC_PHY=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -5533,6 +5574,7 @@ CONFIG_PHY_ROCKCHIP_USB=y
 CONFIG_ARM_PMU=y
 # CONFIG_ARM_DSU_PMU is not set
 # CONFIG_ARM_SPE_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
 # end of Performance monitor support
 
 CONFIG_RAS=y
@@ -5937,7 +5979,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
 # end of Kernel hardening options
 # end of Security options
 
-CONFIG_XOR_BLOCKS=m
+CONFIG_XOR_BLOCKS=y
 CONFIG_CRYPTO=y
 
 #
@@ -5970,7 +6012,6 @@ CONFIG_CRYPTO_NULL2=y
 CONFIG_CRYPTO_CRYPTD=y
 CONFIG_CRYPTO_AUTHENC=m
 # CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_SIMD=y
 CONFIG_CRYPTO_ENGINE=m
 
 #
@@ -6084,6 +6125,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6091,26 +6133,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
 # CONFIG_CRYPTO_USER_API_AEAD is not set
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
 # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
@@ -6153,7 +6175,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 CONFIG_CORDIC=m
 # CONFIG_PRIME_NUMBERS is not set
 CONFIG_RATIONAL=y
@@ -6162,6 +6183,27 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
 # CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
@@ -6326,6 +6368,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -6467,7 +6516,6 @@ CONFIG_STRICT_DEVMEM=y
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_ARCH_HAS_KCOV=y
 CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
 CONFIG_ARCH_USE_MEMTEST=y
 CONFIG_MEMTEST=y

projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm64 5.16.0-rc8 Kernel Configuration
+# Linux/arm64 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621"
 CONFIG_CC_IS_GCC=y
@@ -221,7 +221,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -430,6 +429,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y
 #
 # ARMv8.2 architectural features
 #
+CONFIG_AS_HAS_ARMV8_2=y
+CONFIG_AS_HAS_SHA3=y
 # CONFIG_ARM64_PMEM is not set
 # CONFIG_ARM64_RAS_EXTN is not set
 # CONFIG_ARM64_CNP is not set
@@ -652,6 +653,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -867,13 +869,12 @@ CONFIG_MEMORY_FAILURE=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
 # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
 # CONFIG_CMA_SYSFS is not set
 CONFIG_CMA_AREAS=7
+# CONFIG_ZSWAP is not set
 # CONFIG_ZPOOL is not set
 # CONFIG_ZSMALLOC is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y
@@ -888,6 +889,7 @@ CONFIG_ZONE_DMA32=y
 # CONFIG_READ_ONLY_THP_FOR_FS is not set
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 CONFIG_SECRETMEM=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1415,6 +1417,7 @@ CONFIG_PCIE_ROCKCHIP_HOST=m
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1617,7 +1620,6 @@ CONFIG_BLK_DEV_NBD=m
 # CONFIG_ATA_OVER_ETH is not set
 CONFIG_VIRTIO_BLK=y
 # CONFIG_BLK_DEV_RBD is not set
-# CONFIG_BLK_DEV_RSXX is not set
 
 #
 # NVME Support
@@ -1763,7 +1765,6 @@ CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_MPI3MR is not set
 # CONFIG_SCSI_SMARTPQI is not set
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_UFS_HWMON is not set
 # CONFIG_SCSI_HPTIOP is not set
 # CONFIG_SCSI_MYRB is not set
 # CONFIG_SCSI_MYRS is not set
@@ -1965,6 +1966,7 @@ CONFIG_NET_VENDOR_DLINK=y
 # CONFIG_SUNDANCE is not set
 CONFIG_NET_VENDOR_EMULEX=y
 # CONFIG_BE2NET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 # CONFIG_NET_VENDOR_EZCHIP is not set
 CONFIG_NET_VENDOR_GOOGLE=y
 # CONFIG_GVE is not set
@@ -2041,6 +2043,7 @@ CONFIG_NET_VENDOR_TEHUTI=y
 CONFIG_NET_VENDOR_TI=y
 # CONFIG_TI_CPSW_PHY_SEL is not set
 # CONFIG_TLAN is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_NET_VENDOR_XILINX is not set
@@ -2587,6 +2590,7 @@ CONFIG_SERIAL_8250_DWLIB=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_DW=y
 # CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_PERICOM is not set
 CONFIG_SERIAL_OF_PLATFORM=y
 
 #
@@ -2637,6 +2641,7 @@ CONFIG_HW_RANDOM_OPTEE=m
 # CONFIG_HW_RANDOM_CCTRNG is not set
 # CONFIG_HW_RANDOM_XIPHERA is not set
 CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m
+# CONFIG_HW_RANDOM_CN10K is not set
 # CONFIG_APPLICOM is not set
 CONFIG_DEVMEM=y
 CONFIG_DEVPORT=y
@@ -2821,15 +2826,15 @@ CONFIG_PINMUX=y
 CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
+CONFIG_PINCTRL_MAX77620=y
 # CONFIG_PINCTRL_MCP23S08 is not set
+# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+CONFIG_PINCTRL_RK805=y
 CONFIG_PINCTRL_ROCKCHIP=y
 # CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PINCTRL_SX150X is not set
 # CONFIG_PINCTRL_STMFX is not set
-CONFIG_PINCTRL_MAX77620=y
+# CONFIG_PINCTRL_SX150X is not set
-CONFIG_PINCTRL_RK805=y
-# CONFIG_PINCTRL_OCELOT is not set
-# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
 
 #
 # Renesas pinctrl drivers
@@ -2921,6 +2926,7 @@ CONFIG_GPIO_MAX77620=y
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
 # CONFIG_GPIO_VIRTIO is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2962,6 +2968,7 @@ CONFIG_POWER_SUPPLY_HWMON=y
 # CONFIG_CHARGER_LT3651 is not set
 # CONFIG_CHARGER_LTC4162L is not set
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
+# CONFIG_CHARGER_MAX77976 is not set
 # CONFIG_CHARGER_BQ2415X is not set
 # CONFIG_CHARGER_BQ24190 is not set
 # CONFIG_CHARGER_BQ24257 is not set
@@ -3084,6 +3091,7 @@ CONFIG_SENSORS_LM90=m
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -3113,6 +3121,7 @@ CONFIG_SENSORS_PWM_FAN=m
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 CONFIG_SENSORS_INA2XX=m
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -3325,7 +3334,6 @@ CONFIG_MFD_WL1273_CORE=m
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -3368,6 +3376,7 @@ CONFIG_REGULATOR_GPIO=y
 # CONFIG_REGULATOR_MAX8893 is not set
 # CONFIG_REGULATOR_MAX8952 is not set
 # CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_MAX20086 is not set
 # CONFIG_REGULATOR_MAX77826 is not set
 # CONFIG_REGULATOR_MCP16502 is not set
 # CONFIG_REGULATOR_MP5416 is not set
@@ -3795,6 +3804,7 @@ CONFIG_VIDEO_OV2640=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -4103,7 +4113,8 @@ CONFIG_ROCKCHIP_DW_HDMI=y
 # CONFIG_DRM_AST is not set
 # CONFIG_DRM_MGAG200 is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 # CONFIG_DRM_QXL is not set
 # CONFIG_DRM_VIRTIO_GPU is not set
 CONFIG_DRM_PANEL=y
@@ -4117,6 +4128,7 @@ CONFIG_DRM_PANEL=y
 # CONFIG_DRM_PANEL_SIMPLE is not set
 CONFIG_DRM_PANEL_EDP=y
 # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
 # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
 # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
 # CONFIG_DRM_PANEL_LG_LB035Q02 is not set
@@ -4195,6 +4207,7 @@ CONFIG_DRM_DW_HDMI_CEC=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -4209,6 +4222,7 @@ CONFIG_DRM_PANFROST=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -4425,6 +4439,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -4486,6 +4501,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 CONFIG_SND_SOC_AK4613=m
@@ -4590,6 +4606,7 @@ CONFIG_SND_SOC_SPDIF=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -4711,6 +4728,7 @@ CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LCPOWER=y
 # CONFIG_HID_LED is not set
 CONFIG_HID_LENOVO=y
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 CONFIG_HID_LOGITECH_DJ=y
 CONFIG_HID_LOGITECH_HIDPP=y
@@ -5182,6 +5200,10 @@ CONFIG_LEDS_TRIGGER_PANIC=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_SUPPORT=y
@@ -5458,6 +5480,7 @@ CONFIG_R8188EU=m
 CONFIG_STAGING_MEDIA=y
 CONFIG_VIDEO_HANTRO=m
 CONFIG_VIDEO_HANTRO_ROCKCHIP=y
+# CONFIG_VIDEO_MAX96712 is not set
 CONFIG_VIDEO_ROCKCHIP_VDEC=m
 # CONFIG_VIDEO_ZORAN is not set
 CONFIG_DVB_AV7110_IR=y
@@ -5485,6 +5508,7 @@ CONFIG_DVB_SP8870=m
 # CONFIG_GOLDFISH is not set
 # CONFIG_CHROME_PLATFORMS is not set
 # CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CLK_PREPARE=y
 CONFIG_COMMON_CLK=y
@@ -5509,6 +5533,7 @@ CONFIG_COMMON_CLK_SCPI=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 CONFIG_COMMON_CLK_CS2000_CP=y
+# CONFIG_COMMON_CLK_LAN966X is not set
 CONFIG_COMMON_CLK_S2MPS11=y
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 CONFIG_COMMON_CLK_XGENE=y
@@ -5795,6 +5820,12 @@ CONFIG_ROCKCHIP_SARADC=y
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -5852,6 +5883,7 @@ CONFIG_ROCKCHIP_SARADC=y
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -5871,6 +5903,7 @@ CONFIG_ROCKCHIP_SARADC=y
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -5894,6 +5927,12 @@ CONFIG_ROCKCHIP_SARADC=y
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# CONFIG_ADMV8818 is not set
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -5909,6 +5948,7 @@ CONFIG_ROCKCHIP_SARADC=y
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -6205,8 +6245,10 @@ CONFIG_GENERIC_PHY_MIPI_DPHY=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -6239,6 +6281,8 @@ CONFIG_PHY_ROCKCHIP_USB=y
 CONFIG_ARM_PMU=y
 # CONFIG_ARM_DSU_PMU is not set
 # CONFIG_ARM_SPE_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
+# CONFIG_HISI_PCIE_PMU is not set
 # end of Performance monitor support
 
 CONFIG_RAS=y
@@ -6644,7 +6688,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
 # end of Kernel hardening options
 # end of Security options
 
-CONFIG_XOR_BLOCKS=m
+CONFIG_XOR_BLOCKS=y
 CONFIG_CRYPTO=y
 
 #
@@ -6677,7 +6721,6 @@ CONFIG_CRYPTO_NULL2=y
 CONFIG_CRYPTO_CRYPTD=y
 CONFIG_CRYPTO_AUTHENC=m
 # CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_SIMD=y
 CONFIG_CRYPTO_ENGINE=m
 
 #
@@ -6791,6 +6834,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -6798,26 +6842,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y
 # CONFIG_CRYPTO_USER_API_AEAD is not set
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m
-CONFIG_CRYPTO_LIB_BLAKE2S=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA=m
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
-CONFIG_CRYPTO_LIB_CURVE25519=m
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305=m
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
 # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
@@ -6862,7 +6886,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_NET_UTILS=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
 CONFIG_CORDIC=m
 # CONFIG_PRIME_NUMBERS is not set
 CONFIG_RATIONAL=y
@@ -6871,6 +6894,27 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
 # CONFIG_INDIRECT_PIO is not set
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=m
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
+CONFIG_CRYPTO_LIB_CURVE25519=m
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=m
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
@@ -7036,6 +7080,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -7177,7 +7228,6 @@ CONFIG_STRICT_DEVMEM=y
 # CONFIG_FAULT_INJECTION is not set
 CONFIG_ARCH_HAS_KCOV=y
 CONFIG_CC_HAS_SANCOV_TRACE_PC=y
-# CONFIG_KCOV is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
 CONFIG_ARCH_USE_MEMTEST=y
 CONFIG_MEMTEST=y

projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch

@@ -376,133 +376,3 @@ index d0410ae4def2..cc46855aba46 100644
  		status = "disabled";
  	};
  
-
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Alex Bee <knaerzche@gmail.com>
-Date: Wed, 27 Oct 2021 14:43:40 +0200
-Subject: [PATCH] arm64: dts: rockchip: add interrupt and headphone-detection
- for Rock Pi4's audio codec
-
-As Schematics at [1] and [2] show C- and plus-revisions have interrupt and
-headphone detection lines of ES8316 codec connected.
-
-Add them to the respective device trees.
-
-[1] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf
-[2] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4b_plus_v16_sch_20200628.pdf
-
-Signed-off-by: Alex Bee <knaerzche@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi   | 12 +++++++++++-
- .../boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts     | 11 +++++++++++
- .../boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts     | 11 +++++++++++
- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts   | 11 +++++++++++
- 4 files changed, 44 insertions(+), 1 deletion(-)
-
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-index 6a434be62819..92acf6ea299b 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
-@@ -36,7 +36,7 @@ sdio_pwrseq: sdio-pwrseq {
- 		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
- 	};
- 
--	sound {
-+	sound: sound {
- 		compatible = "audio-graph-card";
- 		label = "Analog";
- 		dais = <&i2s0_p0>;
-@@ -543,6 +543,16 @@ bt_wake_l: bt-wake-l {
- 		};
- 	};
- 
-+	es8316 {
-+		hp_detect: hp-detect {
-+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+
-+		hp_int: hp-int {
-+			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+
- 	pcie {
- 		pcie_pwr_en: pcie-pwr-en {
- 			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts
-index 281a04b2f5e9..f5a68d8d072d 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts
-@@ -12,3 +12,14 @@ / {
- 	model = "Radxa ROCK Pi 4A+";
- 	compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399";
- };
-+
-+&es8316 {
-+	pinctrl-0 = <&hp_detect &hp_int>;
-+	pinctrl-names = "default";
-+	interrupt-parent = <&gpio1>;
-+	interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>;
-+};
-+
-+&sound {
-+	hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-+};
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
-index dfad13d2ab24..81bea953c891 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
-@@ -17,6 +17,13 @@ aliases {
- 	};
- };
- 
-+&es8316 {
-+	pinctrl-0 = <&hp_detect &hp_int>;
-+	pinctrl-names = "default";
-+	interrupt-parent = <&gpio1>;
-+	interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>;
-+};
-+
- &sdio0 {
- 	status = "okay";
- 
-@@ -31,6 +38,10 @@ brcmf: wifi@1 {
- 	};
- };
- 
-+&sound {
-+	hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-+};
-+
- &uart0 {
- 	status = "okay";
- 
-diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
-index 99169bcd51c0..0ad7b6e22f70 100644
---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts
-@@ -17,6 +17,13 @@ aliases {
- 	};
- };
- 
-+&es8316 {
-+	pinctrl-0 = <&hp_detect &hp_int>;
-+	pinctrl-names = "default";
-+	interrupt-parent = <&gpio1>;
-+	interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>;
-+};
-+
- &sdio0 {
- 	status = "okay";
- 
-@@ -31,6 +38,10 @@ brcmf: wifi@1 {
- 	};
- };
- 
-+&sound {
-+	hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
-+};
-+
- &uart0 {
- 	status = "okay";
- 

projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch

@@ -362,169 +362,3 @@ index be74c87a8be4..288462fd5d8e 100644
  		DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
  		return ret;
 
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Thomas Zimmermann <tzimmermann@suse.de>
-Date: Thu, 24 Jun 2021 11:55:02 +0200
-Subject: [PATCH] drm/rockchip: Implement mmap as GEM object function
-
-Moving the driver-specific mmap code into a GEM object function allows
-for using DRM helpers for various mmap callbacks.
-
-The respective rockchip functions are being removed. The file_operations
-structure fops is now being created by the helper macro
-DEFINE_DRM_GEM_FOPS().
-
-Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
----
- drivers/gpu/drm/rockchip/rockchip_drm_drv.c   | 13 +-----
- drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c |  3 +-
- drivers/gpu/drm/rockchip/rockchip_drm_gem.c   | 44 +++++--------------
- drivers/gpu/drm/rockchip/rockchip_drm_gem.h   |  7 ---
- 4 files changed, 15 insertions(+), 52 deletions(-)
-
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
-index e4ebe60b3cc1..69c699459dce 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
-@@ -199,16 +199,7 @@ static void rockchip_drm_unbind(struct device *dev)
- 	drm_dev_put(drm_dev);
- }
- 
--static const struct file_operations rockchip_drm_driver_fops = {
--	.owner = THIS_MODULE,
--	.open = drm_open,
--	.mmap = rockchip_gem_mmap,
--	.poll = drm_poll,
--	.read = drm_read,
--	.unlocked_ioctl = drm_ioctl,
--	.compat_ioctl = drm_compat_ioctl,
--	.release = drm_release,
--};
-+DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops);
- 
- static const struct drm_driver rockchip_drm_driver = {
- 	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
-@@ -217,7 +208,7 @@ static const struct drm_driver rockchip_drm_driver = {
- 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
- 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
- 	.gem_prime_import_sg_table	= rockchip_gem_prime_import_sg_table,
--	.gem_prime_mmap		= rockchip_gem_mmap_buf,
-+	.gem_prime_mmap		= drm_gem_prime_mmap,
- 	.fops			= &rockchip_drm_driver_fops,
- 	.name	= DRIVER_NAME,
- 	.desc	= DRIVER_DESC,
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
-index 2fdc455c4ad7..d8418dd39d0e 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
-@@ -7,6 +7,7 @@
- #include <drm/drm.h>
- #include <drm/drm_fb_helper.h>
- #include <drm/drm_fourcc.h>
-+#include <drm/drm_prime.h>
- #include <drm/drm_probe_helper.h>
- 
- #include "rockchip_drm_drv.h"
-@@ -24,7 +25,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info,
- 	struct drm_fb_helper *helper = info->par;
- 	struct rockchip_drm_private *private = to_drm_private(helper);
- 
--	return rockchip_gem_mmap_buf(private->fbdev_bo, vma);
-+	return drm_gem_prime_mmap(private->fbdev_bo, vma);
- }
- 
- static const struct fb_ops rockchip_drm_fbdev_ops = {
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
-index 7971f57436dd..63eb73b624aa 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
-@@ -240,12 +240,22 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj,
- 	int ret;
- 	struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
- 
-+	/*
-+	 * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
-+	 * whole buffer from the start.
-+	 */
-+	vma->vm_pgoff = 0;
-+
- 	/*
- 	 * We allocated a struct page table for rk_obj, so clear
- 	 * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
- 	 */
-+	vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
- 	vma->vm_flags &= ~VM_PFNMAP;
- 
-+	vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
-+	vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
-+
- 	if (rk_obj->pages)
- 		ret = rockchip_drm_gem_object_mmap_iommu(obj, vma);
- 	else
-@@ -257,39 +267,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj,
- 	return ret;
- }
- 
--int rockchip_gem_mmap_buf(struct drm_gem_object *obj,
--			  struct vm_area_struct *vma)
--{
--	int ret;
--
--	ret = drm_gem_mmap_obj(obj, obj->size, vma);
--	if (ret)
--		return ret;
--
--	return rockchip_drm_gem_object_mmap(obj, vma);
--}
--
--/* drm driver mmap file operations */
--int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma)
--{
--	struct drm_gem_object *obj;
--	int ret;
--
--	ret = drm_gem_mmap(filp, vma);
--	if (ret)
--		return ret;
--
--	/*
--	 * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
--	 * whole buffer from the start.
--	 */
--	vma->vm_pgoff = 0;
--
--	obj = vma->vm_private_data;
--
--	return rockchip_drm_gem_object_mmap(obj, vma);
--}
--
- static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj)
- {
- 	drm_gem_object_release(&rk_obj->base);
-@@ -301,6 +278,7 @@ static const struct drm_gem_object_funcs rockchip_gem_object_funcs = {
- 	.get_sg_table = rockchip_gem_prime_get_sg_table,
- 	.vmap = rockchip_gem_prime_vmap,
- 	.vunmap	= rockchip_gem_prime_vunmap,
-+	.mmap = rockchip_drm_gem_object_mmap,
- 	.vm_ops = &drm_gem_cma_vm_ops,
- };
- 
-diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
-index 5a70a56cd406..47c1861eece0 100644
---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
-+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
-@@ -34,13 +34,6 @@ rockchip_gem_prime_import_sg_table(struct drm_device *dev,
- int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
- void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
- 
--/* drm driver mmap file operations */
--int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma);
--
--/* mmap a gem object to userspace. */
--int rockchip_gem_mmap_buf(struct drm_gem_object *obj,
--			  struct vm_area_struct *vma);
--
- struct rockchip_gem_object *
- 	rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
- 				   bool alloc_kmap);

projects/Samsung/linux/linux.arm.conf

@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 5.16.0-rc8 Kernel Configuration
+# Linux/arm 5.17.0-rc3 Kernel Configuration
 #
 CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0"
 CONFIG_CC_IS_GCC=y
@@ -210,7 +210,6 @@ CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_FUTEX_PI=y
-CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
@@ -673,6 +672,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
 CONFIG_HAVE_EXIT_THREAD=y
 CONFIG_ARCH_MMAP_RND_BITS=8
 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -806,13 +806,12 @@ CONFIG_CONTIG_ALLOC=y
 CONFIG_BOUNCE=y
 # CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-# CONFIG_CLEANCACHE is not set
-# CONFIG_FRONTSWAP is not set
 CONFIG_CMA=y
 # CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
 # CONFIG_CMA_SYSFS is not set
 CONFIG_CMA_AREAS=7
+# CONFIG_ZSWAP is not set
 # CONFIG_ZPOOL is not set
 # CONFIG_ZSMALLOC is not set
 CONFIG_GENERIC_EARLY_IOREMAP=y
@@ -821,6 +820,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y
 # CONFIG_GUP_TEST is not set
 CONFIG_KMAP_LOCAL=y
 CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+# CONFIG_ANON_VMA_NAME is not set
 
 #
 # Data Access Monitoring
@@ -1066,6 +1066,7 @@ CONFIG_HAVE_PCI=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEVTMPFS_SAFE is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 
@@ -1260,7 +1261,6 @@ CONFIG_SCSI_LOWLEVEL=y
 CONFIG_ISCSI_TCP=y
 CONFIG_ISCSI_BOOT_SYSFS=y
 # CONFIG_SCSI_UFSHCD is not set
-# CONFIG_SCSI_UFS_HWMON is not set
 # CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_DH is not set
 # end of SCSI device support
@@ -1334,6 +1334,7 @@ CONFIG_ETHERNET=y
 # CONFIG_NET_VENDOR_CORTINA is not set
 # CONFIG_DM9000 is not set
 # CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
 # CONFIG_NET_VENDOR_EZCHIP is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_GOOGLE is not set
@@ -1362,6 +1363,7 @@ CONFIG_ETHERNET=y
 # CONFIG_NET_VENDOR_SOCIONEXT is not set
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_NET_VENDOR_XILINX is not set
@@ -1931,7 +1933,6 @@ CONFIG_I2C_GPIO=y
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_RK3X is not set
-CONFIG_HAVE_S3C2410_I2C=y
 CONFIG_I2C_S3C2410=y
 # CONFIG_I2C_SIMTEC is not set
 # CONFIG_I2C_XILINX is not set
@@ -2021,11 +2022,11 @@ CONFIG_PINMUX=y
 CONFIG_PINCONF=y
 # CONFIG_DEBUG_PINCTRL is not set
 # CONFIG_PINCTRL_MCP23S08 is not set
-# CONFIG_PINCTRL_SINGLE is not set
-# CONFIG_PINCTRL_SX150X is not set
-# CONFIG_PINCTRL_STMFX is not set
-# CONFIG_PINCTRL_OCELOT is not set
 # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
+# CONFIG_PINCTRL_OCELOT is not set
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_STMFX is not set
+# CONFIG_PINCTRL_SX150X is not set
 
 #
 # Renesas pinctrl drivers
@@ -2108,6 +2109,7 @@ CONFIG_GPIO_WM8994=y
 #
 # CONFIG_GPIO_AGGREGATOR is not set
 # CONFIG_GPIO_MOCKUP is not set
+# CONFIG_GPIO_SIM is not set
 # end of Virtual GPIO drivers
 
 # CONFIG_W1 is not set
@@ -2150,6 +2152,7 @@ CONFIG_BATTERY_MAX17042=y
 CONFIG_CHARGER_MAX14577=y
 # CONFIG_CHARGER_DETECTOR_MAX14656 is not set
 CONFIG_CHARGER_MAX77693=y
+# CONFIG_CHARGER_MAX77976 is not set
 CONFIG_CHARGER_MAX8997=y
 CONFIG_CHARGER_MAX8998=y
 # CONFIG_CHARGER_BQ2415X is not set
@@ -2272,6 +2275,7 @@ CONFIG_SENSORS_NTC_THERMISTOR=y
 # CONFIG_SENSORS_NCT7904 is not set
 # CONFIG_SENSORS_NPCM7XX is not set
 # CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_NZXT_SMART2 is not set
 # CONFIG_SENSORS_OCC_P8_I2C is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_PMBUS is not set
@@ -2300,6 +2304,7 @@ CONFIG_SENSORS_PWM_FAN=y
 # CONFIG_SENSORS_AMC6821 is not set
 # CONFIG_SENSORS_INA209 is not set
 CONFIG_SENSORS_INA2XX=y
+# CONFIG_SENSORS_INA238 is not set
 # CONFIG_SENSORS_INA3221 is not set
 # CONFIG_SENSORS_TC74 is not set
 # CONFIG_SENSORS_THMC50 is not set
@@ -2499,7 +2504,6 @@ CONFIG_MFD_TPS65090=y
 # CONFIG_MFD_WM8350_I2C is not set
 CONFIG_MFD_WM8994=y
 # CONFIG_MFD_ROHM_BD718XX is not set
-# CONFIG_MFD_ROHM_BD70528 is not set
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
 # CONFIG_MFD_STPMIC1 is not set
@@ -2542,6 +2546,7 @@ CONFIG_REGULATOR_MAX8952=y
 # CONFIG_REGULATOR_MAX8973 is not set
 CONFIG_REGULATOR_MAX8997=y
 CONFIG_REGULATOR_MAX8998=y
+# CONFIG_REGULATOR_MAX20086 is not set
 CONFIG_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_MAX77693=y
 CONFIG_REGULATOR_MAX77802=y
@@ -2847,6 +2852,7 @@ CONFIG_VIDEOBUF2_VMALLOC=m
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV5670 is not set
 # CONFIG_VIDEO_OV5675 is not set
+# CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV772X is not set
@@ -2980,7 +2986,8 @@ CONFIG_DRM_EXYNOS_HDMI=y
 # CONFIG_DRM_UDL is not set
 # CONFIG_DRM_ARMADA is not set
 # CONFIG_DRM_RCAR_DW_HDMI is not set
-# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RCAR_USE_LVDS is not set
+# CONFIG_DRM_RCAR_MIPI_DSI is not set
 # CONFIG_DRM_OMAP is not set
 # CONFIG_DRM_TILCDC is not set
 # CONFIG_DRM_FSL_DCU is not set
@@ -2993,6 +3000,7 @@ CONFIG_DRM_PANEL=y
 # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
 # CONFIG_DRM_PANEL_ARM_VERSATILE is not set
 # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
+# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
 # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
 # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
 # CONFIG_DRM_PANEL_DSI_CM is not set
@@ -3007,6 +3015,7 @@ CONFIG_DRM_PANEL_EDP=y
 # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
 # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
 # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
+# CONFIG_DRM_PANEL_JDI_R63452 is not set
 # CONFIG_DRM_PANEL_KHADAS_TS050 is not set
 # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
 # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
@@ -3016,6 +3025,7 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y
 # CONFIG_DRM_PANEL_LG_LG4573 is not set
 # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
 # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
 # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
@@ -3047,6 +3057,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y
 # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
 # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
 # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
 # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
 # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
 # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
@@ -3106,6 +3117,7 @@ CONFIG_DRM_ANALOGIX_DP=y
 # CONFIG_DRM_GM12U320 is not set
 # CONFIG_DRM_SIMPLEDRM is not set
 # CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9163 is not set
 # CONFIG_TINYDRM_ILI9225 is not set
 # CONFIG_TINYDRM_ILI9341 is not set
 # CONFIG_TINYDRM_ILI9486 is not set
@@ -3122,6 +3134,7 @@ CONFIG_DRM_ANALOGIX_DP=y
 # CONFIG_DRM_GUD is not set
 # CONFIG_DRM_LEGACY is not set
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_NOMODESET=y
 
 #
 # Frame buffer Devices
@@ -3259,6 +3272,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
 # CONFIG_SND_SOC_ADI is not set
 # CONFIG_SND_SOC_AMD_ACP is not set
+# CONFIG_SND_AMD_ACP_CONFIG is not set
 # CONFIG_SND_ATMEL_SOC is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_DESIGNWARE_I2S is not set
@@ -3324,6 +3338,7 @@ CONFIG_SND_SOC_WM_HUBS=y
 # CONFIG_SND_SOC_ADAU7118_I2C is not set
 # CONFIG_SND_SOC_AK4104 is not set
 # CONFIG_SND_SOC_AK4118 is not set
+# CONFIG_SND_SOC_AK4375 is not set
 # CONFIG_SND_SOC_AK4458 is not set
 # CONFIG_SND_SOC_AK4554 is not set
 # CONFIG_SND_SOC_AK4613 is not set
@@ -3420,6 +3435,7 @@ CONFIG_SND_SOC_RT5631=y
 # CONFIG_SND_SOC_TDA7419 is not set
 # CONFIG_SND_SOC_TFA9879 is not set
 # CONFIG_SND_SOC_TFA989X is not set
+# CONFIG_SND_SOC_TLV320ADC3XXX is not set
 # CONFIG_SND_SOC_TLV320AIC23_I2C is not set
 # CONFIG_SND_SOC_TLV320AIC23_SPI is not set
 # CONFIG_SND_SOC_TLV320AIC31XX is not set
@@ -3538,6 +3554,7 @@ CONFIG_HID_KENSINGTON=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 # CONFIG_HID_LENOVO is not set
+# CONFIG_HID_LETSKETCH is not set
 CONFIG_HID_LOGITECH=y
 # CONFIG_HID_LOGITECH_HIDPP is not set
 # CONFIG_LOGITECH_FF is not set
@@ -3940,6 +3957,10 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_LEDS_TRIGGER_PATTERN is not set
 # CONFIG_LEDS_TRIGGER_AUDIO is not set
 # CONFIG_LEDS_TRIGGER_TTY is not set
+
+#
+# Simple LED drivers
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 CONFIG_EDAC_ATOMIC_SCRUB=y
@@ -4050,7 +4071,6 @@ CONFIG_RTC_I2C_AND_SPI=y
 #
 # on-CPU RTC drivers
 #
-CONFIG_HAVE_S3C_RTC=y
 CONFIG_RTC_DRV_S3C=y
 # CONFIG_RTC_DRV_PL030 is not set
 # CONFIG_RTC_DRV_PL031 is not set
@@ -4227,6 +4247,7 @@ CONFIG_COMMON_CLK_MAX77686=y
 # CONFIG_COMMON_CLK_CDCE706 is not set
 # CONFIG_COMMON_CLK_CDCE925 is not set
 # CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_COMMON_CLK_LAN966X is not set
 CONFIG_COMMON_CLK_S2MPS11=y
 # CONFIG_COMMON_CLK_AXI_CLKGEN is not set
 # CONFIG_COMMON_CLK_PWM is not set
@@ -4327,6 +4348,7 @@ CONFIG_EXYNOS_IOMMU=y
 CONFIG_SOC_SAMSUNG=y
 CONFIG_EXYNOS_ASV_ARM=y
 CONFIG_EXYNOS_CHIPID=y
+# CONFIG_EXYNOS_USI is not set
 CONFIG_EXYNOS_PMU=y
 CONFIG_EXYNOS_PMU_ARM_DRIVERS=y
 CONFIG_EXYNOS_PM_DOMAINS=y
@@ -4500,6 +4522,12 @@ CONFIG_EXYNOS_ADC=y
 # CONFIG_XILINX_XADC is not set
 # end of Analog to digital converters
 
+#
+# Analog to digital and digital to analog converters
+#
+# CONFIG_AD74413R is not set
+# end of Analog to digital and digital to analog converters
+
 #
 # Analog Front Ends
 #
@@ -4555,6 +4583,7 @@ CONFIG_EXYNOS_ADC=y
 #
 # Digital to analog converters
 #
+# CONFIG_AD3552R is not set
 # CONFIG_AD5064 is not set
 # CONFIG_AD5360 is not set
 # CONFIG_AD5380 is not set
@@ -4574,6 +4603,7 @@ CONFIG_EXYNOS_ADC=y
 # CONFIG_AD5766 is not set
 # CONFIG_AD5770R is not set
 # CONFIG_AD5791 is not set
+# CONFIG_AD7293 is not set
 # CONFIG_AD7303 is not set
 # CONFIG_AD8801 is not set
 # CONFIG_DPOT_DAC is not set
@@ -4597,6 +4627,11 @@ CONFIG_EXYNOS_ADC=y
 #
 # end of IIO dummy driver
 
+#
+# Filters
+#
+# end of Filters
+
 #
 # Frequency Synthesizers DDS/PLL
 #
@@ -4612,6 +4647,7 @@ CONFIG_EXYNOS_ADC=y
 #
 # CONFIG_ADF4350 is not set
 # CONFIG_ADF4371 is not set
+# CONFIG_ADMV1013 is not set
 # CONFIG_ADRF6780 is not set
 # end of Phase-Locked Loop (PLL) frequency synthesizers
 # end of Frequency Synthesizers DDS/PLL
@@ -4896,8 +4932,10 @@ CONFIG_GENERIC_PHY=y
 # CONFIG_PHY_CADENCE_SALVO is not set
 # CONFIG_PHY_FSL_IMX8MQ_USB is not set
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_FSL_IMX8M_PCIE is not set
 # CONFIG_PHY_PXA_28NM_HSIC is not set
 # CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_LAN966X_SERDES is not set
 # CONFIG_PHY_CPCAP_USB is not set
 # CONFIG_PHY_MAPPHONE_MDM6600 is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
@@ -5402,6 +5440,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y
 # CONFIG_CRYPTO_DRBG_CTR is not set
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_KDF800108_CTR=y
 CONFIG_CRYPTO_USER_API=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
@@ -5411,25 +5450,6 @@ CONFIG_CRYPTO_USER_API_AEAD=m
 CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
 # CONFIG_CRYPTO_STATS is not set
 CONFIG_CRYPTO_HASH_INFO=y
-
-#
-# Crypto library routines
-#
-CONFIG_CRYPTO_LIB_AES=y
-CONFIG_CRYPTO_LIB_ARC4=m
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_LIB_BLAKE2S=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_LIB_CHACHA=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y
-CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
-CONFIG_CRYPTO_LIB_CURVE25519=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
-CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_POLY1305=y
-CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
-CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_HW=y
 CONFIG_CRYPTO_DEV_EXYNOS_RNG=y
 CONFIG_CRYPTO_DEV_S5P=y
@@ -5475,6 +5495,26 @@ CONFIG_CORDIC=m
 CONFIG_RATIONAL=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=m
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
+CONFIG_CRYPTO_LIB_SHA256=y
+# end of Crypto library routines
+
 CONFIG_CRC_CCITT=y
 CONFIG_CRC16=y
 # CONFIG_CRC_T10DIF is not set
@@ -5640,6 +5680,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MISC=y
 
+#
+# Networking Debugging
+#
+# CONFIG_NET_DEV_REFCNT_TRACKER is not set
+# CONFIG_NET_NS_REFCNT_TRACKER is not set
+# end of Networking Debugging
+
 #
 # Memory Debugging
 #
@@ -5668,6 +5715,8 @@ CONFIG_HAVE_ARCH_KASAN=y
 CONFIG_CC_HAS_KASAN_GENERIC=y
 CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
 # CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
 # end of Memory Debugging
 
 # CONFIG_DEBUG_SHIRQ is not set
@@ -5765,6 +5814,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
 CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y
 CONFIG_TRACE_CLOCK=y
 CONFIG_RING_BUFFER=y
 CONFIG_EVENT_TRACING=y
@@ -5834,6 +5884,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_MIN_HEAP is not set
 # CONFIG_TEST_DIV64 is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_TEST_REF_TRACKER is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_REED_SOLOMON_TEST is not set
 # CONFIG_INTERVAL_TREE_TEST is not set
@@ -5851,7 +5902,7 @@ CONFIG_RUNTIME_TESTING_MENU=y
 # CONFIG_TEST_XARRAY is not set
 # CONFIG_TEST_OVERFLOW is not set
 # CONFIG_TEST_RHASHTABLE is not set
-# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_SIPHASH is not set
 # CONFIG_TEST_IDA is not set
 # CONFIG_TEST_LKM is not set
 # CONFIG_TEST_BITOPS is not set