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Merge pull request #3882 from jernejsk/upstream
Allwinner: Update upstream patches
This commit is contained in:
Jonas Karlman
GitHub
commit
a027672bbc
@ -96,37 +96,3 @@ index a669945eb829a..ace1a6340ca9c 100644
|
|||||||
err_restore_page:
|
err_restore_page:
|
||||||
return phy_restore_page(phydev, oldpage, ret);
|
return phy_restore_page(phydev, oldpage, ret);
|
||||||
}
|
}
|
||||||
From bb0516f4d03ffe9bcc06f840e477ea665af94e9d Mon Sep 17 00:00:00 2001
|
|
||||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
|
||||||
Date: Sun, 25 Aug 2019 14:40:10 +0200
|
|
||||||
Subject: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator
|
|
||||||
delay
|
|
||||||
|
|
||||||
Depending on kernel and bootloader configuration, it's possible that
|
|
||||||
Realtek ethernet PHY isn't powered on properly. It needs some time
|
|
||||||
before it can be used.
|
|
||||||
|
|
||||||
Fix that by adding 100ms ramp delay to regulator responsible for
|
|
||||||
powering PHY.
|
|
||||||
|
|
||||||
Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
|
|
||||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
|
||||||
---
|
|
||||||
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 4 ++++
|
|
||||||
1 file changed, 4 insertions(+)
|
|
||||||
|
|
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
|
||||||
index 24f1aac366d6..9612a34c1762 100644
|
|
||||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
|
||||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
|
||||||
@@ -63,3 +63,7 @@
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
+
|
|
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+®_dc1sw {
|
|
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+ regulator-enable-ramp-delay = <100000>;
|
|
||||||
+};
|
|
||||||
--
|
|
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2.23.0
|
|
||||||
|
|
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@ -1,13 +0,0 @@
|
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
|
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index 8a81f764abd0..46b72f2ed5cd 100644
|
|
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--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
|
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+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
|
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@@ -288,7 +288,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
|
|
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0, 3, /* M */
|
|
||||||
24, 1, /* mux */
|
|
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BIT(31), /* gate */
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|
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- 0);
|
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+ CLK_SET_RATE_PARENT);
|
|
||||||
|
|
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static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
|
|
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0x67c, BIT(0), 0);
|
|
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@ -1,77 +0,0 @@
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From ab099efa81230670679a0aa8ad6aa9cb2ac748b4 Mon Sep 17 00:00:00 2001
|
|
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From: Jernej Skrabec <jernej.skrabec@siol.net>
|
|
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Date: Sat, 14 Sep 2019 15:33:14 +0200
|
|
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Subject: [PATCH] clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
|
|
||||||
|
|
||||||
Audio devices needs exact clock rates in order to correctly reproduce
|
|
||||||
the sound. Until now, only integer factors were used to configure H6
|
|
||||||
audio PLL which resulted in inexact rates. Fix that by adding support
|
|
||||||
for fractional factors using sigma-delta modulation look-up table. It
|
|
||||||
contains values for two most commonly used audio base frequencies.
|
|
||||||
|
|
||||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
|
||||||
---
|
|
||||||
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
|
|
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1 file changed, 15 insertions(+), 6 deletions(-)
|
|
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|
|
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diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
|
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index d89353a3cdec..ed6338d74474 100644
|
|
||||||
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
|
||||||
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
|
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@@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
|
|
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* hardcode it to match with the clock names.
|
|
||||||
*/
|
|
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#define SUN50I_H6_PLL_AUDIO_REG 0x078
|
|
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+
|
|
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+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
|
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+ { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
|
|
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+ { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
|
|
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+};
|
|
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+
|
|
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static struct ccu_nm pll_audio_base_clk = {
|
|
||||||
.enable = BIT(31),
|
|
||||||
.lock = BIT(28),
|
|
||||||
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
|
|
||||||
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
|
|
||||||
+ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
|
|
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+ BIT(24), 0x178, BIT(31)),
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|
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.common = {
|
|
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+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
|
|
||||||
.reg = 0x078,
|
|
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.hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
|
|
||||||
&ccu_nm_ops,
|
|
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@@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
|
|
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};
|
|
||||||
|
|
||||||
/*
|
|
||||||
- * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
|
|
||||||
- * fixed post-divider 2.
|
|
||||||
+ * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
|
|
||||||
+ * rates can be set exactly in conjunction with sigma-delta modulation.
|
|
||||||
*/
|
|
||||||
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
|
|
||||||
clk_parent_pll_audio,
|
|
||||||
- 8, 1, CLK_SET_RATE_PARENT);
|
|
||||||
+ 24, 1, CLK_SET_RATE_PARENT);
|
|
||||||
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
|
|
||||||
clk_parent_pll_audio,
|
|
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4, 1, CLK_SET_RATE_PARENT);
|
|
||||||
@@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
- * Force the post-divider of pll-audio to 8 and the output divider
|
|
||||||
- * of it to 1, to make the clock name represents the real frequency.
|
|
||||||
+ * Force the post-divider of pll-audio to 12 and the output divider
|
|
||||||
+ * of it to 2, so 24576000 and 22579200 rates can be set exactly.
|
|
||||||
*/
|
|
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val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
|
|
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val &= ~(GENMASK(21, 16) | BIT(0));
|
|
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- writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
|
|
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+ writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* First clock parent (osc32K) is unusable for CEC. But since there
|
|
||||||
--
|
|
||||||
2.23.0
|
|
||||||
|
|
||||||
@ -5685,3 +5685,91 @@ index ba2876a64cf6..e877bf1d537c 100644
|
|||||||
--
|
--
|
||||||
2.23.0
|
2.23.0
|
||||||
|
|
||||||
|
From 2511366797fa6ab4a404b4b000ef7cd262aaafe8 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Mon, 9 Sep 2019 20:42:35 +0200
|
||||||
|
Subject: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator
|
||||||
|
delay
|
||||||
|
|
||||||
|
Depending on kernel and bootloader configuration, it's possible that
|
||||||
|
Realtek ethernet PHY isn't powered on properly. According to the
|
||||||
|
datasheet, it needs 30ms to power up and then some more time before it
|
||||||
|
can be used.
|
||||||
|
|
||||||
|
Fix that by adding 100ms ramp delay to regulator responsible for
|
||||||
|
powering PHY.
|
||||||
|
|
||||||
|
Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
|
||||||
|
Suggested-by: Ondrej Jirman <megous@megous.com>
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <mripard@kernel.org>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 9 +++++++++
|
||||||
|
1 file changed, 9 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
||||||
|
index 24f1aac366d6..d5b6e8159a33 100644
|
||||||
|
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
||||||
|
@@ -63,3 +63,12 @@
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+®_dc1sw {
|
||||||
|
+ /*
|
||||||
|
+ * Ethernet PHY needs 30ms to properly power up and some more
|
||||||
|
+ * to initialize. 100ms should be plenty of time to finish
|
||||||
|
+ * whole process.
|
||||||
|
+ */
|
||||||
|
+ regulator-enable-ramp-delay = <100000>;
|
||||||
|
+};
|
||||||
|
--
|
||||||
|
2.23.0
|
||||||
|
|
||||||
|
From ccdf3aaa27ded6db9a93eed3ca7468bb2353b8fe Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Sun, 29 Sep 2019 10:52:59 +0200
|
||||||
|
Subject: [PATCH] arm64: dts: allwinner: a64: sopine-baseboard: Add PHY
|
||||||
|
regulator delay
|
||||||
|
|
||||||
|
It turns out that sopine-baseboard needs same fix as pine64-plus
|
||||||
|
for ethernet PHY. Here too Realtek ethernet PHY chip needs additional
|
||||||
|
power on delay to properly initialize. Datasheet mentions that chip
|
||||||
|
needs 30 ms to be properly powered on and that it needs some more time
|
||||||
|
to be initialized.
|
||||||
|
|
||||||
|
Fix that by adding 100ms ramp delay to regulator responsible for
|
||||||
|
powering PHY.
|
||||||
|
|
||||||
|
Note that issue was found out and fix tested on pine64-lts, but it's
|
||||||
|
basically the same as sopine-baseboard, only layout and connectors
|
||||||
|
differ.
|
||||||
|
|
||||||
|
Fixes: bdfe4cebea11 ("arm64: allwinner: a64: add Ethernet PHY regulator for several boards")
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Signed-off-by: Maxime Ripard <mripard@kernel.org>
|
||||||
|
---
|
||||||
|
.../boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 6 ++++++
|
||||||
|
1 file changed, 6 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
|
||||||
|
index e6fb9683f213..25099202c52c 100644
|
||||||
|
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
|
||||||
|
@@ -159,6 +159,12 @@
|
||||||
|
};
|
||||||
|
|
||||||
|
®_dc1sw {
|
||||||
|
+ /*
|
||||||
|
+ * Ethernet PHY needs 30ms to properly power up and some more
|
||||||
|
+ * to initialize. 100ms should be plenty of time to finish
|
||||||
|
+ * whole process.
|
||||||
|
+ */
|
||||||
|
+ regulator-enable-ramp-delay = <100000>;
|
||||||
|
regulator-name = "vcc-phy";
|
||||||
|
};
|
||||||
|
|
||||||
|
--
|
||||||
|
2.23.0
|
||||||
|
|
||||||
|
|||||||
@ -155,3 +155,114 @@ index cf528c289857..4b3e863c4f8a 100644
|
|||||||
--
|
--
|
||||||
2.23.0
|
2.23.0
|
||||||
|
|
||||||
|
From 3ee5f8ab5e718afdde9984a089137360bdfc66eb Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Sat, 14 Sep 2019 15:51:00 +0200
|
||||||
|
Subject: [PATCH] clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
|
||||||
|
|
||||||
|
Audio devices needs exact clock rates in order to correctly reproduce
|
||||||
|
the sound. Until now, only integer factors were used to configure H6
|
||||||
|
audio PLL which resulted in inexact rates. Fix that by adding support
|
||||||
|
for fractional factors using sigma-delta modulation look-up table. It
|
||||||
|
contains values for two most commonly used audio base frequencies.
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Acked-by: Chen-Yu Tsai <wens@csie.org>
|
||||||
|
Signed-off-by: Maxime Ripard <mripard@kernel.org>
|
||||||
|
---
|
||||||
|
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------
|
||||||
|
1 file changed, 15 insertions(+), 6 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
||||||
|
index d89353a3cdec..ed6338d74474 100644
|
||||||
|
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
||||||
|
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
||||||
|
@@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = {
|
||||||
|
* hardcode it to match with the clock names.
|
||||||
|
*/
|
||||||
|
#define SUN50I_H6_PLL_AUDIO_REG 0x078
|
||||||
|
+
|
||||||
|
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
|
||||||
|
+ { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
|
||||||
|
+ { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static struct ccu_nm pll_audio_base_clk = {
|
||||||
|
.enable = BIT(31),
|
||||||
|
.lock = BIT(28),
|
||||||
|
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
|
||||||
|
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
|
||||||
|
+ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
|
||||||
|
+ BIT(24), 0x178, BIT(31)),
|
||||||
|
.common = {
|
||||||
|
+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
|
||||||
|
.reg = 0x078,
|
||||||
|
.hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
|
||||||
|
&ccu_nm_ops,
|
||||||
|
@@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
- * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
|
||||||
|
- * fixed post-divider 2.
|
||||||
|
+ * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
|
||||||
|
+ * rates can be set exactly in conjunction with sigma-delta modulation.
|
||||||
|
*/
|
||||||
|
static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
|
||||||
|
clk_parent_pll_audio,
|
||||||
|
- 8, 1, CLK_SET_RATE_PARENT);
|
||||||
|
+ 24, 1, CLK_SET_RATE_PARENT);
|
||||||
|
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
|
||||||
|
clk_parent_pll_audio,
|
||||||
|
4, 1, CLK_SET_RATE_PARENT);
|
||||||
|
@@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
- * Force the post-divider of pll-audio to 8 and the output divider
|
||||||
|
- * of it to 1, to make the clock name represents the real frequency.
|
||||||
|
+ * Force the post-divider of pll-audio to 12 and the output divider
|
||||||
|
+ * of it to 2, so 24576000 and 22579200 rates can be set exactly.
|
||||||
|
*/
|
||||||
|
val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
|
||||||
|
val &= ~(GENMASK(21, 16) | BIT(0));
|
||||||
|
- writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
|
||||||
|
+ writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* First clock parent (osc32K) is unusable for CEC. But since there
|
||||||
|
--
|
||||||
|
2.23.0
|
||||||
|
|
||||||
|
From 4947913491aa83d760e5710c3290f150eb56847a Mon Sep 17 00:00:00 2001
|
||||||
|
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
Date: Tue, 1 Oct 2019 21:59:25 +0200
|
||||||
|
Subject: [PATCH] clk: sunxi-ng: h6: Allow GPU to change parent rate
|
||||||
|
|
||||||
|
GPU PLL was designed with dynamic frequency switching in mind so driver
|
||||||
|
can adjust rate based on the GPU load.
|
||||||
|
|
||||||
|
Allow GPU clock to change parent rate (GPU PLL is the only possible
|
||||||
|
parent of GPU clock).
|
||||||
|
|
||||||
|
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||||
|
---
|
||||||
|
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
|
||||||
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
||||||
|
index d89353a3cdec..e254c06c8621 100644
|
||||||
|
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
||||||
|
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
|
||||||
|
@@ -290,7 +290,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
|
||||||
|
0, 3, /* M */
|
||||||
|
24, 1, /* mux */
|
||||||
|
BIT(31), /* gate */
|
||||||
|
- 0);
|
||||||
|
+ CLK_SET_RATE_PARENT);
|
||||||
|
|
||||||
|
static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
|
||||||
|
0x67c, BIT(0), 0);
|
||||||
|
--
|
||||||
|
2.23.0
|
||||||
|
|
||||||
|
|||||||
Loading…
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Reference in New Issue
Block a user