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linux (default): drop obsolete patches, fix incompatible patches
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MilhouseVH
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commit
c035a54849
@ -1,60 +0,0 @@
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From 428ce1a022a0bc30cf2d09cde4c1352a88d70d0a Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Fri, 26 Aug 2016 19:26:01 +0100
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Subject: [PATCH] drm/i915: Limit the depth of the display pipeline to the
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framebuffer
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There is little point in using higher bitdepth inside the pipeline if
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the endpoints are of lower accuracy. Using the higher bitdepth requires
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extra bandwidth, often to the point of failure - such as signal loss and
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blank displays.
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Since commit 7a0baa623446 ("Revert "drm/i915: Disable 12bpc hdmi for
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now"") we have had users reporting blank screens and rightfully
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complaining about the regressions. Whilst these are using due to some
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other underlying bug, they have lingered and still remain unresolved. So
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let's try a different tact and avoid using higher bitdepths than
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required.
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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---
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drivers/gpu/drm/i915/intel_display.c | 11 ++++++++---
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1 file changed, 8 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index af551a2c89ba..05ad77dae2e8 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -12695,9 +12695,11 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_device *dev = crtc->base.dev;
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- struct drm_atomic_state *state;
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+ struct drm_atomic_state *state = pipe_config->base.state;
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+
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struct drm_connector *connector;
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struct drm_connector_state *connector_state;
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+ struct drm_plane_state *plane_state;
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int bpp, i;
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if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
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@@ -12707,11 +12709,14 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
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else
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bpp = 8*3;
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+ plane_state = drm_atomic_get_plane_state(state, crtc->base.primary);
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+ if (plane_state->fb->depth < bpp)
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+ bpp = 8*3;
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+ DRM_DEBUG_KMS("initial pipeline bpp = %d (fb depth %d)\n",
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+ bpp, plane_state->fb->depth);
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pipe_config->pipe_bpp = bpp;
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- state = pipe_config->base.state;
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-
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/* Clamp display bpp to EDID value */
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for_each_connector_in_state(state, connector, connector_state, i) {
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if (connector_state->crtc != &crtc->base)
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--
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2.9.3
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@ -1,89 +1,3 @@
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From 0db9810b18ffc46709ad00831c426712d5489aea Mon Sep 17 00:00:00 2001
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Sat, 13 Aug 2016 21:32:17 +0100
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Subject: [PATCH 1/2] drm/i915: Show RPS autotuning thresholds along waitboost
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---
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drivers/gpu/drm/i915/i915_debugfs.c | 62 +++++++++++++++++++++++++++++++++++++
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1 file changed, 62 insertions(+)
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diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
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index 1035468..2cff44a 100644
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--- a/drivers/gpu/drm/i915/i915_debugfs.c
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+++ b/drivers/gpu/drm/i915/i915_debugfs.c
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@@ -2434,6 +2434,68 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
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spin_unlock(&dev_priv->rps.client_lock);
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mutex_unlock(&dev->filelist_mutex);
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+ if (INTEL_INFO(dev)->gen >= 6) {
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+ u32 rpmodectl, rpinclimit, rpdeclimit;
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+ u32 rpstat, cagf;
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+ u32 rpupei, rpcurup, rpprevup;
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+ u32 rpdownei, rpcurdown, rpprevdown;
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+
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+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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+
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+ rpmodectl = I915_READ(GEN6_RP_CONTROL);
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+ rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
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+ rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
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+
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+ rpstat = I915_READ(GEN6_RPSTAT1);
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+ rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
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+ rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
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+ rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
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+ rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
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+ rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
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+ rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
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+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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+
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+ if (IS_GEN9(dev))
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+ cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
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+ else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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+ cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
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+ else
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+ cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
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+ cagf = intel_gpu_freq(dev_priv, cagf);
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+
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+
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+ seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
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+ rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
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+ seq_printf(m, "RP CUR UP: %d (%dus)\n",
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+ rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
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+ seq_printf(m, "RP PREV UP: %d (%dus)\n",
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+ rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
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+ seq_printf(m, "Up threshold: %d%%\n",
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+ dev_priv->rps.up_threshold);
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+
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+ seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
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+ rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
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+ seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
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+ rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
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+ seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
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+ rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
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+ seq_printf(m, "Down threshold: %d%%\n",
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+ dev_priv->rps.down_threshold);
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+
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+ seq_printf(m, "Current freq: %d MHz\n",
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+ intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
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+ seq_printf(m, "Actual freq: %d MHz\n", cagf);
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+ seq_printf(m, "Idle freq: %d MHz\n",
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+ intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
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+ seq_printf(m, "Min freq: %d MHz\n",
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+ intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
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+ seq_printf(m, "Max freq: %d MHz\n",
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+ intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
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+ seq_printf(m,
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+ "efficient (RPe) frequency: %d MHz\n",
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+ intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
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+ }
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+
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return 0;
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}
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--
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2.7.4
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From d77c081cd5ea0d278b314ee2043556d2bd9aacaf Mon Sep 17 00:00:00 2001
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From: fritsch <peter.fruehberger@gmail.com>
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Date: Sat, 13 Aug 2016 22:56:37 +0200
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