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u-boot (Rockchip): drop upstreamed patches in 2023.04
This commit is contained in:
Jonas Karlman
Rudi Heitbaum
parent
a34e611e7e
commit
d16106b387
@ -1,115 +0,0 @@
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From 2cb23b80e4169e121c520ff33cb6a60e0a0ded21 Mon Sep 17 00:00:00 2001
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From: Xavier Drudis Ferran <xdrudis@tinet.cat>
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Date: Sat, 16 Jul 2022 12:31:45 +0200
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Subject: [PATCH] arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in
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documented range
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The original code set up the DDR clock to 48 MHz, not 50MHz as
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requested, and did it in a way that didn't satisfy the Application
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Notes in RK3399 TRM [1]. 2.9.2.B says:
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PLL frequency range requirement
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[...]
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FOUTVCO: 800MHz to 3.2GHz
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2.9.2.A :
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PLL output frequency configuration
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[...]
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FOUTVCO = FREF / REFDIV * FBDIV
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FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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FREF = 24 MHz
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The original code gives FOUTVCO: 24MHz/1 * 12 = 288MHz < 800MHz
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And the resulting FOUTPOSTDIV is 288MHz / 3 / 2 = 48MHz
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but the requested frequency was 50MHz
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Note:
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2.7.2 Detail Register Description
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PMUCRU_PPLL_CON0 says
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fbdiv
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Feedback Divide Value
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Valid divider settings are:
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[16, 3200] in integer mode
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So .fbdiv = 12 wouldn't be right. But 2.9.2.C says:
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PLL setting consideration
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[...]
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The following settings are valid for FBDIV:
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DSMPD=1 (Integer Mode):
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12,13,14,16-4095 (practical value is limited to 3200, 2400, or 1600
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(FVCOMAX / FREFMIN))
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[...]
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So .fbdiv = 12 would be right.
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In any case FOUTVCO is still wrong. I thank YouMin Chen for
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confirmation and explanation.
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Despite documentation, I don't seem to be able to reproduce a
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practical problem with the wrong FOUTVCO. When I initially found it I
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thought some problems with detecting the RAM capacity in my Rock Pi 4B
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could be related to it and my patch seemed to help. But since I'm no
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longer able to reproduce the issue, it works with or without this
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patch. And meanwhile a patch[2] by Lee Jones and YouMin Chen addresses
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this issue. Btw, shouldn't that be commited?
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So this patches solves no visible problem. Yet, to prevent future
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problems, I think it'd be best to stick to spec.
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An alternative to this patch could be
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{.refdiv = 1, .fbdiv = 75, .postdiv1 = 6, .postdiv2 = 6};
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This would theoretically consume more power and yield less jitter,
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according to 2.9.2.C :
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PLL setting consideration
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[...]
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For lowest power operation, the minimum VCO and FREF frequencies
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should be used. For minimum jitter operation, the highest VCO and
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FREF frequencies should be used.
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[...]
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But I haven't tried it because I don't think it matters much. 50MHz
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for DDR is only shortly used by TPL at RAM init. Normal operation is
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at 800MHz. Maybe it's better to use less power until later when more
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complex software can control batteries or charging or whatever ?
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Cc: Simon Glass <sjg@chromium.org>
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Cc: Philipp Tomsich <philipp.tomsich@vrull.eu>
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Cc: Kever Yang <kever.yang@rock-chips.com>
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Cc: Lukasz Majewski <lukma@denx.de>
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Cc: Sean Anderson <seanga2@gmail.com>
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Link: [1] https://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf
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Link: [2] https://patchwork.ozlabs.org/project/uboot/list/?series=305766
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Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat>
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Tested-by: Michal Suchánek <msuchanek@suse.de>
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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---
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drivers/clk/rockchip/clk_rk3399.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
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index 97bf1c6e15..eaeac451df 100644
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--- a/drivers/clk/rockchip/clk_rk3399.c
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+++ b/drivers/clk/rockchip/clk_rk3399.c
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@@ -856,7 +856,7 @@ static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
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switch (set_rate) {
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case 50 * MHz:
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dpll_cfg = (struct pll_div)
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- {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
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+ {.refdiv = 2, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 6};
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break;
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case 200 * MHz:
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dpll_cfg = (struct pll_div)
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--
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2.39.0
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@ -1,150 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Francis Fan <francis.fan@rock-chips.com>
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Date: Tue, 7 Nov 2017 17:50:11 +0800
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Subject: [PATCH 1/6] rockchip: efuse: add support for RK322x non-secure efuse
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block
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Signed-off-by: Francis Fan <francis.fan@rock-chips.com>
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Signed-off-by: Cody Xie <cody.xie@rock-chips.com>
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---
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drivers/misc/rockchip-efuse.c | 96 +++++++++++++++++++++++++++++++++--
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1 file changed, 92 insertions(+), 4 deletions(-)
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diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
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index 083ee65e0a..4c9239f7ba 100644
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--- a/drivers/misc/rockchip-efuse.c
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+++ b/drivers/misc/rockchip-efuse.c
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@@ -27,6 +27,17 @@
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#define RK3399_STROBE BIT(1)
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#define RK3399_CSB BIT(0)
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+#define RK3288_A_SHIFT 6
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+#define RK3288_A_MASK 0x3ff
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+#define RK3288_NFUSES 32
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+#define RK3288_BYTES_PER_FUSE 1
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+#define RK3288_PGENB BIT(3)
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+#define RK3288_LOAD BIT(2)
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+#define RK3288_STROBE BIT(1)
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+#define RK3288_CSB BIT(0)
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+
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+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
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+
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struct rockchip_efuse_regs {
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u32 ctrl; /* 0x00 efuse control register */
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u32 dout; /* 0x04 efuse data out register */
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@@ -53,7 +64,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
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*/
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struct udevice *dev;
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- u8 fuses[128];
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+ u8 fuses[128] = {0};
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int ret;
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/* retrieve the device */
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@@ -77,7 +88,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
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}
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U_BOOT_CMD(
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- rk3399_dump_efuses, 1, 1, dump_efuses,
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+ rockchip_dump_efuses, 1, 1, dump_efuses,
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"Dump the content of the efuses",
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""
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);
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@@ -127,10 +138,59 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
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return 0;
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}
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+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
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+ void *buf, int size)
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+{
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+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
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+ struct rockchip_efuse_regs *efuse =
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+ (struct rockchip_efuse_regs *)plat->base;
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+ u8 *buffer = buf;
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+ int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE;
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+
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+ if (size > (max_size - offset))
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+ size = max_size - offset;
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+
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+ /* Switch to read mode */
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+ writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl);
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+ udelay(1);
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+
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+ while (size--) {
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+ writel(readl(&efuse->ctrl) &
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+ (~(RK3288_A_MASK << RK3288_A_SHIFT)),
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+ &efuse->ctrl);
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+ /* set addr */
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+ writel(readl(&efuse->ctrl) |
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+ ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
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+ &efuse->ctrl);
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+ udelay(1);
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+ /* strobe low to high */
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+ writel(readl(&efuse->ctrl) |
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+ RK3288_STROBE, &efuse->ctrl);
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+ ndelay(60);
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+ /* read data */
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+ *buffer++ = readl(&efuse->dout);
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+ /* reset strobe to low */
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+ writel(readl(&efuse->ctrl) &
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+ (~RK3288_STROBE), &efuse->ctrl);
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+ udelay(1);
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+ }
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+
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+ /* Switch to standby mode */
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+ writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl);
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+
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+ return 0;
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+}
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+
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static int rockchip_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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- return rockchip_rk3399_efuse_read(dev, offset, buf, size);
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+ EFUSE_READ efuse_read = NULL;
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+
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+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
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+ if (!efuse_read)
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+ return -ENOSYS;
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+
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+ return (*efuse_read)(dev, offset, buf, size);
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}
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static const struct misc_ops rockchip_efuse_ops = {
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@@ -146,7 +206,35 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev)
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}
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static const struct udevice_id rockchip_efuse_ids[] = {
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- { .compatible = "rockchip,rk3399-efuse" },
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+ /* deprecated but kept around for dts binding compatibility */
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+ {
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+ .compatible = "rockchip,rockchip-efuse",
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+ .data = (ulong)&rockchip_rk3288_efuse_read,
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+ },
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+ {
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+ .compatible = "rockchip,rk3066a-efuse",
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+ .data = (ulong)&rockchip_rk3288_efuse_read,
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+ },
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+ {
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+ .compatible = "rockchip,rk3188-efuse",
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+ .data = (ulong)&rockchip_rk3288_efuse_read,
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+ },
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+ {
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+ .compatible = "rockchip,rk3228-efuse",
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+ .data = (ulong)&rockchip_rk3288_efuse_read,
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+ },
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+ {
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+ .compatible = "rockchip,rk3288-efuse",
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+ .data = (ulong)&rockchip_rk3288_efuse_read,
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+ },
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+ {
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+ .compatible = "rockchip,rk3368-efuse",
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+ .data = (ulong)&rockchip_rk3288_efuse_read,
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+ },
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+ {
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+ .compatible = "rockchip,rk3399-efuse",
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+ .data = (ulong)&rockchip_rk3399_efuse_read,
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+ },
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{}
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};
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@ -1,117 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Joseph Chen <chenjh@rock-chips.com>
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Date: Thu, 2 Aug 2018 20:33:16 +0800
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Subject: [PATCH 2/6] rockchip: efuse: add support for RK3328 non-secure efuse
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block
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Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
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---
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drivers/misc/rockchip-efuse.c | 67 +++++++++++++++++++++++++++++++++++
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1 file changed, 67 insertions(+)
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diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
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index 4c9239f7ba..c75405bfcf 100644
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--- a/drivers/misc/rockchip-efuse.c
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+++ b/drivers/misc/rockchip-efuse.c
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@@ -13,6 +13,7 @@
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#include <dm.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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+#include <malloc.h>
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#include <misc.h>
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#define RK3399_A_SHIFT 16
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@@ -36,6 +37,13 @@
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#define RK3288_STROBE BIT(1)
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#define RK3288_CSB BIT(0)
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+#define RK3328_INT_STATUS 0x0018
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+#define RK3328_DOUT 0x0020
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+#define RK3328_AUTO_CTRL 0x0024
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+#define RK3328_INT_FINISH BIT(0)
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+#define RK3328_AUTO_ENB BIT(0)
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+#define RK3328_AUTO_RD BIT(1)
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+
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typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
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struct rockchip_efuse_regs {
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@@ -46,6 +54,10 @@ struct rockchip_efuse_regs {
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u32 jtag_pass; /* 0x10 JTAG password */
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u32 strobe_finish_ctrl;
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/* 0x14 efuse strobe finish control register */
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+ u32 int_status;/* 0x18 */
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+ u32 reserved; /* 0x1c */
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+ u32 dout2; /* 0x20 */
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+ u32 auto_ctrl; /* 0x24 */
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};
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struct rockchip_efuse_plat {
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@@ -181,6 +193,57 @@ static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
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return 0;
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}
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+static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
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+ void *buf, int size)
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+{
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+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
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+ struct rockchip_efuse_regs *efuse =
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+ (struct rockchip_efuse_regs *)plat->base;
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+ unsigned int addr_start, addr_end, addr_offset, addr_len;
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+ u32 out_value, status;
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+ u8 *buffer;
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+ int ret = 0, i = 0, j = 0;
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+
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+ /* Max non-secure Byte */
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+ if (size > 32)
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+ size = 32;
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+
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+ /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
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+ offset += 96;
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+ addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) /
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+ RK3399_BYTES_PER_FUSE;
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+ addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) /
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+ RK3399_BYTES_PER_FUSE;
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+ addr_offset = offset % RK3399_BYTES_PER_FUSE;
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+ addr_len = addr_end - addr_start;
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+
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+ buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE);
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+ if (!buffer)
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+ return -ENOMEM;
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+
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+ for (j = 0; j < addr_len; j++) {
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+ writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
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+ ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
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+ &efuse->auto_ctrl);
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+ udelay(5);
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+ status = readl(&efuse->int_status);
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+ if (!(status & RK3328_INT_FINISH)) {
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+ ret = -EIO;
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+ goto err;
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+ }
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+ out_value = readl(&efuse->dout2);
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+ writel(RK3328_INT_FINISH, &efuse->int_status);
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+
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+ memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE);
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+ i += RK3399_BYTES_PER_FUSE;
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+ }
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+ memcpy(buf, buffer + addr_offset, size);
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+err:
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+ free(buffer);
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+
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+ return ret;
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+}
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+
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static int rockchip_efuse_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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@@ -231,6 +294,10 @@ static const struct udevice_id rockchip_efuse_ids[] = {
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.compatible = "rockchip,rk3368-efuse",
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.data = (ulong)&rockchip_rk3288_efuse_read,
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},
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+ {
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+ .compatible = "rockchip,rk3328-efuse",
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+ .data = (ulong)&rockchip_rk3328_efuse_read,
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+ },
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{
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.compatible = "rockchip,rk3399-efuse",
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.data = (ulong)&rockchip_rk3399_efuse_read,
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@ -1,22 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Sun, 11 Sep 2022 10:56:43 +0200
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Subject: [PATCH 3/6] arm: dts: update efuse for RK3288 for 0x20
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---
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arch/arm/dts/rk3288.dtsi | 3 +-
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1 file changed, 1 insertion(+), 1 deletions(-)
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diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
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index 53ee760b98..f923630f63 100644
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--- a/arch/arm/dts/rk3288.dtsi
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+++ b/arch/arm/dts/rk3288.dtsi
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@@ -1214,7 +1214,7 @@
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efuse: efuse@ffb40000 {
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compatible = "rockchip,rk3288-efuse";
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- reg = <0xffb40000 0x10000>;
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+ reg = <0xffb40000 0x20>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&cru PCLK_EFUSE256>;
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