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Fix boot from 128GB Micron eMMC on ODROID-N2(+) (#1064)
This commit is contained in:
Stefan Agner
GitHub
parent
c2098e1cf4
commit
162084082e
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From f9877c2895d6c05710a828d0cd46d9f25626b070 Mon Sep 17 00:00:00 2001
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From 526ccae8321b9b48925c44999611c3c5a374328e Mon Sep 17 00:00:00 2001
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Message-Id: <f9877c2895d6c05710a828d0cd46d9f25626b070.1606490648.git.stefan@agner.ch>
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Message-Id: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Mon, 31 Aug 2020 13:40:18 +0200
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Date: Mon, 31 Aug 2020 13:40:18 +0200
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Subject: [PATCH 1/2] ARM: meson: isolate loading of socinfo
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Subject: [PATCH 1/4] ARM: meson: isolate loading of socinfo
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Move loading of socinfo into a separate function so the value can be
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Move loading of socinfo into a separate function so the value can be
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reused later.
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reused later.
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@ -1,10 +1,10 @@
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From 31e32295dc261032d7f5540a0b7f79a4f5a5b807 Mon Sep 17 00:00:00 2001
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From 2b2ad8c105cbb5fb48c3c5f0512c031f6533d522 Mon Sep 17 00:00:00 2001
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Message-Id: <31e32295dc261032d7f5540a0b7f79a4f5a5b807.1606490648.git.stefan@agner.ch>
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Message-Id: <2b2ad8c105cbb5fb48c3c5f0512c031f6533d522.1607361661.git.stefan@agner.ch>
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In-Reply-To: <f9877c2895d6c05710a828d0cd46d9f25626b070.1606490648.git.stefan@agner.ch>
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In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
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References: <f9877c2895d6c05710a828d0cd46d9f25626b070.1606490648.git.stefan@agner.ch>
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References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
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From: Pascal Vizeli <pvizeli@syshack.ch>
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From: Pascal Vizeli <pvizeli@syshack.ch>
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Date: Tue, 4 Aug 2020 13:50:57 +0000
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Date: Tue, 4 Aug 2020 13:50:57 +0000
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Subject: [PATCH 2/2] meson: Add board_rev to env
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Subject: [PATCH 2/4] meson: Add board_rev to env
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Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
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Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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@ -0,0 +1,103 @@
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From 77241850a471015eb18e1b3cb124fce71c7b59c8 Mon Sep 17 00:00:00 2001
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Message-Id: <77241850a471015eb18e1b3cb124fce71c7b59c8.1607361661.git.stefan@agner.ch>
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In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
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References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
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From: Neil Armstrong <narmstrong@baylibre.com>
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Date: Wed, 11 Nov 2020 08:22:10 +0900
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Subject: [PATCH 3/4] mmc: meson-gx: change clock phase value on SM1 SoCs
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Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's
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working fine over 50MHz on Amlogic SM1 SoCs.
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Since Other Amlogic SoCs doens't report an issue, phase value is using
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to 180' by default.
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To distinguish which value is used adds an u-boot only sm1 compatible.
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In future, it needs to find what value is a proper about each SoCs.
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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
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Tested-by: Anand Moon <linux.amoon@gmail.com>
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---
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arch/arm/include/asm/arch-meson/sd_emmc.h | 5 +++++
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drivers/mmc/meson_gx_mmc.c | 27 +++++++++++++++++++----
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2 files changed, 28 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
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index 1e9f8cf498..cb16f75fc6 100644
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--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
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+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
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@@ -12,6 +12,11 @@
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#endif
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+enum meson_gx_mmc_compatible {
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+ MMC_COMPATIBLE_GX,
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+ MMC_COMPATIBLE_SM1,
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+};
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+
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#define SDIO_PORT_A 0
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#define SDIO_PORT_B 1
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#define SDIO_PORT_C 2
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diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
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index 719dd1e5e5..5facbfdd9a 100644
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--- a/drivers/mmc/meson_gx_mmc.c
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+++ b/drivers/mmc/meson_gx_mmc.c
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@@ -17,6 +17,14 @@
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#include <linux/delay.h>
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#include <linux/log2.h>
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+bool meson_gx_mmc_is_compatible(struct udevice *dev,
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+ enum meson_gx_mmc_compatible family)
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+{
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+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
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+
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+ return compat == family;
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+}
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+
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static inline void *get_regbase(const struct mmc *mmc)
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{
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struct meson_mmc_platdata *pdata = mmc->priv;
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@@ -42,6 +50,8 @@ static void meson_mmc_config_clock(struct mmc *mmc)
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if (!mmc->clock)
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return;
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+ /* TOFIX This should use the proper clock taken from DT */
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+
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/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
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if (mmc->clock > 16000000) {
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clk = SD_EMMC_CLKSRC_DIV2;
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@@ -52,8 +62,16 @@ static void meson_mmc_config_clock(struct mmc *mmc)
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}
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clk_div = DIV_ROUND_UP(clk, mmc->clock);
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- /* 180 phase core clock */
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- meson_mmc_clk |= CLK_CO_PHASE_180;
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+ /*
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+ * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
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+ * If CLK_CO_PHASE_270 is used, it's more stable than other.
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+ * Other SoCs use CLK_CO_PHASE_180 by default.
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+ * It needs to find what is a proper value about each SoCs.
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+ */
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+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
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+ meson_mmc_clk |= CLK_CO_PHASE_270;
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+ else
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+ meson_mmc_clk |= CLK_CO_PHASE_180;
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/* 180 phase tx clock */
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meson_mmc_clk |= CLK_TX_PHASE_000;
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@@ -308,8 +326,9 @@ int meson_mmc_bind(struct udevice *dev)
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}
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static const struct udevice_id meson_mmc_match[] = {
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- { .compatible = "amlogic,meson-gx-mmc" },
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- { .compatible = "amlogic,meson-axg-mmc" },
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+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
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+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
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+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
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{ /* sentinel */ }
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};
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--
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2.29.2
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@ -0,0 +1,73 @@
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From 179546705437886904fd8215bf2e6fbe7d731fb9 Mon Sep 17 00:00:00 2001
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Message-Id: <179546705437886904fd8215bf2e6fbe7d731fb9.1607361661.git.stefan@agner.ch>
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In-Reply-To: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
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References: <526ccae8321b9b48925c44999611c3c5a374328e.1607361661.git.stefan@agner.ch>
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From: Stefan Agner <stefan@agner.ch>
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Date: Mon, 7 Dec 2020 17:55:28 +0100
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Subject: [PATCH 4/4] mmc: meson-gx: change clock phase value on AGX SoCs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Amlogic AGX SoCs seem to have issue communicating with some eMMC
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devices (in particular with a Micron 128GB eMMC 5.1). The device
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is detected with 1-bit bus width, and at higher temperature loading
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pretty much anything from the storage fails: (e.g. fs_devread read error
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- block).
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When phase is set to 270° it is detected with 8-bit bus width and is
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working fine accross all temperatures.
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Signed-off-by: Stefan Agner <stefan@agner.ch>
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---
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arch/arm/include/asm/arch-meson/sd_emmc.h | 1 +
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drivers/mmc/meson_gx_mmc.c | 9 +++++----
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2 files changed, 6 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
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index cb16f75fc6..db5e058098 100644
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--- a/arch/arm/include/asm/arch-meson/sd_emmc.h
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+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
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@@ -14,6 +14,7 @@
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enum meson_gx_mmc_compatible {
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MMC_COMPATIBLE_GX,
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+ MMC_COMPATIBLE_AGX,
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MMC_COMPATIBLE_SM1,
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};
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diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
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index 5facbfdd9a..2c27113c10 100644
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--- a/drivers/mmc/meson_gx_mmc.c
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+++ b/drivers/mmc/meson_gx_mmc.c
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@@ -64,14 +64,15 @@ static void meson_mmc_config_clock(struct mmc *mmc)
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/*
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* SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
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+ * AGX SoCs don't work reliable with some eMMCs with CLK_CO_PHASE_180
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* If CLK_CO_PHASE_270 is used, it's more stable than other.
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* Other SoCs use CLK_CO_PHASE_180 by default.
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* It needs to find what is a proper value about each SoCs.
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*/
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- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
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- meson_mmc_clk |= CLK_CO_PHASE_270;
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- else
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+ if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_GX))
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meson_mmc_clk |= CLK_CO_PHASE_180;
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+ else
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+ meson_mmc_clk |= CLK_CO_PHASE_270;
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/* 180 phase tx clock */
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meson_mmc_clk |= CLK_TX_PHASE_000;
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@@ -327,7 +328,7 @@ int meson_mmc_bind(struct udevice *dev)
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static const struct udevice_id meson_mmc_match[] = {
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{ .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
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- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
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+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_AGX },
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{ .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
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{ /* sentinel */ }
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};
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--
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2.29.2
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