Merge pull request #10241 from heitbaum/uplift-kernel-projects-to-master

[le12.2] Uplift kernel projects to master
This commit is contained in:
Matthias Reichl 2025-07-22 19:53:58 +02:00 committed by GitHub
commit ba3527f093
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
182 changed files with 16751 additions and 22622 deletions

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@ -16,6 +16,7 @@ CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_NF_REJECT_IPV6=m
CONFIG_IP6_NF_IPTABLES=m
@ -23,6 +24,7 @@ CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_NAT=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_TARGET_LOG=m
@ -173,3 +175,7 @@ CONFIG_MD=y
CONFIG_BLK_DEV_DM=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_OVERLAY_FS=m
# new options since 28.0.0
CONFIG_IP_SET=m
CONFIG_IP_SET_HASH_NET=m
CONFIG_NETFILTER_XT_SET=m

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@ -16,8 +16,8 @@ PKG_PATCH_DIRS="${LINUX}"
case "${LINUX}" in
amlogic)
PKG_VERSION="e8f897f4afef0031fe618a8e94127a0934896aba" # 6.8.0
PKG_SHA256="52608771cc42196f0a7a71a93270a27ca5f7ba1d9280fb398e521b0620a7a3ac"
PKG_VERSION="86731a2a651e58953fc949573895f2fa6d456841" # 6.16-rc3
PKG_SHA256="008b00968a8bfc0627580b82a2d30c7304336a4f92a58e80cdbc2d4723e01840"
PKG_URL="https://github.com/torvalds/linux/archive/${PKG_VERSION}.tar.gz"
PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
PKG_PATCH_DIRS="default"
@ -30,8 +30,8 @@ case "${LINUX}" in
PKG_PATCH_DIRS="raspberrypi rtlwifi/6.13 rtlwifi/6.14 rtlwifi/6.15"
;;
*)
PKG_VERSION="6.6.71"
PKG_SHA256="219715ba2dcfa6539fba09ad3f9212772f3507189eb60d77f8e89b06c32e724e"
PKG_VERSION="6.15.6"
PKG_SHA256="2bb586c954277d070c8fdf6d7275faa93b4807d9bf3353b491d8149cca02b4fc"
PKG_URL="https://www.kernel.org/pub/linux/kernel/v${PKG_VERSION/.*/}.x/${PKG_NAME}-${PKG_VERSION}.tar.xz"
PKG_PATCH_DIRS="default"
;;

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@ -1,13 +0,0 @@
diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index 0294bfb6c5f8..153036bbed7e 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -35,7 +35,7 @@ ifeq ($(SRCARCH),x86)
ifeq (${IS_64_BIT}, 1)
CFLAGS += -DHAVE_ARCH_X86_64_SUPPORT -DHAVE_SYSCALL_TABLE -I$(OUTPUT)arch/x86/include/generated
ARCH_INCLUDE = ../../arch/x86/lib/memcpy_64.S ../../arch/x86/lib/memset_64.S
- LIBUNWIND_LIBS = -lunwind-x86_64 -lunwind -llzma
+ LIBUNWIND_LIBS = -lunwind-x86_64 -lunwind
$(call detected,CONFIG_X86_64)
else
LIBUNWIND_LIBS = -lunwind-x86 -llzma -lunwind

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@ -1,49 +0,0 @@
From 826beca0ce76876507372349da860a986078eacd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Istv=C3=A1n=20V=C3=A1radi?= <ivaradi@varadiistvan.hu>
Date: Tue, 13 Feb 2024 21:20:32 +0100
Subject: [PATCH] media: anysee: accept read buffers of length 1 in
anysee_master_xfer
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
anysee_master_xfer currently accepts read messages of length 2 only.
However, several frontends, e.g. tda10023 send buffers of length 1,
containing an 8-bit register number (see tda10023_readreg).
These buffers are rejected currently, making many Anysee variants
to not work. In these cases the "Unsupported Anysee version"
message is logged.
This patch alters the function to accept buffers of a length of 1 too.
Signed-off-by: István Váradi <ivaradi@varadiistvan.hu>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
[hverkuil: add spaces around '<', fix typo in 'sevaral']
---
drivers/media/usb/dvb-usb-v2/anysee.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/usb/dvb-usb-v2/anysee.c b/drivers/media/usb/dvb-usb-v2/anysee.c
index a1235d0cce92..8699846eb416 100644
--- a/drivers/media/usb/dvb-usb-v2/anysee.c
+++ b/drivers/media/usb/dvb-usb-v2/anysee.c
@@ -202,14 +202,14 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
while (i < num) {
if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) {
- if (msg[i].len != 2 || msg[i + 1].len > 60) {
+ if (msg[i].len < 1 || msg[i].len > 2 || msg[i + 1].len > 60) {
ret = -EOPNOTSUPP;
break;
}
buf[0] = CMD_I2C_READ;
buf[1] = (msg[i].addr << 1) | 0x01;
buf[2] = msg[i].buf[0];
- buf[3] = msg[i].buf[1];
+ buf[3] = (msg[i].len < 2) ? 0 : msg[i].buf[1];
buf[4] = msg[i].len-1;
buf[5] = msg[i+1].len;
ret = anysee_ctrl_msg(d, buf, 6, msg[i+1].buf,
--
2.34.1

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,5 @@
# ath9k.conf: setup modload options for module ath9k.
#
# enable "Channel Context support" to avoid buffering in live TV
options ath9k use_chanctx=1

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@ -62,14 +62,14 @@ again for each clock, which is part of why I didn't do it that way.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/clk-conf.c | 54 ++++++++++++++++++++++++++++++++++++++++++
drivers/clk/clk-conf.c | 56 ++++++++++++++++++++++++++++++++++++++++++
drivers/clk/clk.c | 31 ++++++++++++++++++++++++
drivers/clk/clk.h | 2 ++
3 files changed, 87 insertions(+)
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -11,6 +11,54 @@
@@ -11,6 +11,56 @@
#include <linux/of.h>
#include <linux/printk.h>
@ -93,7 +93,9 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
+ clkspec.np = node;
+ clkspec.args_count = nr_cells;
+
+ of_property_for_each_u32(node, "protected-clocks", prop, cur, clkspec.args[0]) {
+ prop = of_find_property(node, "protected-clocks", NULL);
+ for (cur = of_prop_next_u32(prop, NULL, &clkspec.args[0]); cur;
+ cur = of_prop_next_u32(prop, cur, &clkspec.args[0])) {
+ /* read the remainder of the clock specifier */
+ for (i = 1; i < nr_cells; ++i) {
+ cur = of_prop_next_u32(prop, cur, &clkspec.args[i]);

View File

@ -15,7 +15,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -194,22 +194,6 @@ int qcom_cc_register_sleep_clk(struct de
@@ -223,20 +223,6 @@ int qcom_cc_register_sleep_clk(struct de
}
EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
@ -23,11 +23,9 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
-static void qcom_cc_drop_protected(struct device *dev, struct qcom_cc *cc)
-{
- struct device_node *np = dev->of_node;
- struct property *prop;
- const __be32 *p;
- u32 i;
-
- of_property_for_each_u32(np, "protected-clocks", prop, p, i) {
- of_property_for_each_u32(np, "protected-clocks", i) {
- if (i >= cc->num_rclks)
- continue;
-
@ -38,7 +36,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -272,8 +256,6 @@ int qcom_cc_really_probe(struct platform
@@ -330,8 +314,6 @@ int qcom_cc_really_probe(struct platform
cc->rclks = rclks;
cc->num_rclks = num_clks;

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@ -1,61 +0,0 @@
Subject: [PATCH] drm: Call drm_atomic_helper_shutdown() at shutdown time for misc drivers
From: Douglas Anderson <dianders@chromium.org>
Date: Fri, 01 Sep 2023 16:39:53 -0700
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Based on grepping through the source code these drivers appear to be
missing a call to drm_atomic_helper_shutdown() at system shutdown
time. Among other things, this means that if a panel is in use that it
won't be cleanly powered off at system shutdown time.
The fact that we should call drm_atomic_helper_shutdown() in the case
of OS shutdown/restart comes straight out of the kernel doc "driver
instance overview" in drm_drv.c.
All of the drivers in this patch were fairly straightforward to fix
since they already had a call to drm_atomic_helper_shutdown() at
remove/unbind time but were just lacking one at system shutdown. The
only hitch is that some of these drivers use the component model to
register/unregister their DRM devices. The shutdown callback is part
of the original device. The typical solution here, based on how other
DRM drivers do this, is to keep track of whether the device is bound
based on drvdata. In most cases the drvdata is the drm_device, so we
can just make sure it is NULL when the device is not bound. In some
drivers, this required minor code changes. To make things simpler,
drm_atomic_helper_shutdown() has been modified to consider a NULL
drm_device as a noop in the patch ("drm/atomic-helper:
drm_atomic_helper_shutdown(NULL) should be a noop").
Suggested-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20230901163944.RFT.2.I9115e5d094a43e687978b0699cc1fe9f2a3452ea@changeid
---
<snip>
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 6a8dfc022d3c..35d7a7ffd208 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -413,6 +413,11 @@ static void sun4i_drv_remove(struct platform_device *pdev)
component_master_del(&pdev->dev, &sun4i_drv_master_ops);
}
+static void sun4i_drv_shutdown(struct platform_device *pdev)
+{
+ drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
+}
+
static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun4i-a10-display-engine" },
{ .compatible = "allwinner,sun5i-a10s-display-engine" },
@@ -437,6 +442,7 @@ MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
static struct platform_driver sun4i_drv_platform_driver = {
.probe = sun4i_drv_probe,
.remove_new = sun4i_drv_remove,
+ .shutdown = sun4i_drv_shutdown,
.driver = {
.name = "sun4i-drm",
.of_match_table = sun4i_drv_of_table,
<snip>

View File

@ -39,7 +39,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
aquantia-objs += aquantia_main.o
--- /dev/null
+++ b/drivers/net/phy/ac200.c
@@ -0,0 +1,234 @@
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Driver for AC200 Ethernet PHY
@ -242,7 +242,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+ return 0;
+}
+
+static int ac200_ephy_remove(struct platform_device *pdev)
+static void ac200_ephy_remove(struct platform_device *pdev)
+{
+ struct ac200_ephy_dev *priv = platform_get_drvdata(pdev);
+
@ -251,8 +251,6 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+ regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
+ regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
+ regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
+
+ return 0;
+}
+
+static const struct of_device_id ac200_ephy_match[] = {

View File

@ -47,7 +47,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+obj-$(CONFIG_VIDEO_SUN50I_DEINTERLACE) += sun50i-di.o
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun50i-di/sun50i-di.c
@@ -0,0 +1,1137 @@
@@ -0,0 +1,1135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner sun50i deinterlacer driver
@ -848,7 +848,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+ src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ src_vq->drv_priv = ctx;
+ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ src_vq->min_buffers_needed = 1;
+ src_vq->min_queued_buffers = 1;
+ src_vq->ops = &deinterlace_qops;
+ src_vq->mem_ops = &vb2_dma_contig_memops;
+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
@ -863,7 +863,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ dst_vq->drv_priv = ctx;
+ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ dst_vq->min_buffers_needed = 2;
+ dst_vq->min_queued_buffers = 2;
+ dst_vq->ops = &deinterlace_qops;
+ dst_vq->mem_ops = &vb2_dma_contig_memops;
+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
@ -1087,7 +1087,7 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+ return ret;
+}
+
+static int deinterlace_remove(struct platform_device *pdev)
+static void deinterlace_remove(struct platform_device *pdev)
+{
+ struct deinterlace_dev *dev = platform_get_drvdata(pdev);
+
@ -1096,8 +1096,6 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+ v4l2_device_unregister(&dev->v4l2_dev);
+
+ pm_runtime_force_suspend(&pdev->dev);
+
+ return 0;
+}
+
+static int deinterlace_runtime_resume(struct device *device)

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@ -1,165 +0,0 @@
From 25b44143ea8162209beb02759ca3ea3bd3be7a74 Mon Sep 17 00:00:00 2001
From: Corentin Labbe <clabbe.montjoie@gmail.com>
Date: Fri, 14 Oct 2022 12:54:21 +0200
Subject: [PATCH] phy: handle optional regulator for PHY
Add handling of optional regulators for PHY.
Regulators need to be enabled before PHY scanning, so MDIO bus
initiate this task.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
drivers/net/mdio/fwnode_mdio.c | 53 ++++++++++++++++++++++++++++++++--
drivers/net/phy/phy_device.c | 6 ++++
include/linux/phy.h | 3 ++
3 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mdio/fwnode_mdio.c b/drivers/net/mdio/fwnode_mdio.c
index fd02f5cbc853..bd5a27eaf40c 100644
--- a/drivers/net/mdio/fwnode_mdio.c
+++ b/drivers/net/mdio/fwnode_mdio.c
@@ -11,6 +11,7 @@
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/pse-pd/pse.h>
+#include <linux/regulator/consumer.h>
MODULE_AUTHOR("Calvin Johnson <calvin.johnson@oss.nxp.com>");
MODULE_LICENSE("GPL");
@@ -58,6 +59,40 @@ fwnode_find_mii_timestamper(struct fwnode_handle *fwnode)
return register_mii_timestamper(arg.np, arg.args[0]);
}
+static int
+fwnode_regulator_get_bulk_enabled(struct device *dev,
+ struct fwnode_handle *fwnode,
+ struct regulator_bulk_data **consumers)
+{
+ struct device_node *np;
+ int ret, reg_cnt;
+
+ np = to_of_node(fwnode);
+ if (!np)
+ return 0;
+
+ reg_cnt = of_regulator_bulk_get_all(dev, np, consumers);
+ if (reg_cnt < 0) {
+ ret = reg_cnt;
+ goto clean_consumers;
+ }
+
+ if (reg_cnt == 0)
+ return 0;
+
+ ret = regulator_bulk_enable(reg_cnt, *consumers);
+ if (ret)
+ goto clean_consumers;
+
+ return reg_cnt;
+
+clean_consumers:
+ kfree(*consumers);
+ *consumers = NULL;
+
+ return ret;
+}
+
int fwnode_mdiobus_phy_device_register(struct mii_bus *mdio,
struct phy_device *phy,
struct fwnode_handle *child, u32 addr)
@@ -113,12 +148,13 @@ EXPORT_SYMBOL(fwnode_mdiobus_phy_device_register);
int fwnode_mdiobus_register_phy(struct mii_bus *bus,
struct fwnode_handle *child, u32 addr)
{
+ struct regulator_bulk_data *consumers = NULL;
struct mii_timestamper *mii_ts = NULL;
struct pse_control *psec = NULL;
struct phy_device *phy;
+ int rc, reg_cnt;
bool is_c45;
u32 phy_id;
- int rc;
psec = fwnode_find_pse_control(child);
if (IS_ERR(psec))
@@ -130,6 +166,12 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus,
goto clean_pse;
}
+ reg_cnt = fwnode_regulator_get_bulk_enabled(&bus->dev, child, &consumers);
+ if (reg_cnt < 0) {
+ rc = reg_cnt;
+ goto clean_mii_ts;
+ }
+
is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
if (is_c45 || fwnode_get_phy_id(child, &phy_id))
phy = get_phy_device(bus, addr, is_c45);
@@ -137,9 +179,12 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus,
phy = phy_device_create(bus, addr, phy_id, 0, NULL);
if (IS_ERR(phy)) {
rc = PTR_ERR(phy);
- goto clean_mii_ts;
+ goto clean_regulators;
}
+ phy->regulator_cnt = reg_cnt;
+ phy->consumers = consumers;
+
if (is_acpi_node(child)) {
phy->irq = bus->irq[addr];
@@ -174,6 +219,10 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus,
clean_phy:
phy_device_free(phy);
+clean_regulators:
+ if (reg_cnt > 0)
+ regulator_bulk_disable(reg_cnt, consumers);
+ kfree(consumers);
clean_mii_ts:
unregister_mii_timestamper(mii_ts);
clean_pse:
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 2ce74593d6e4..31b6913ceed1 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -31,6 +31,7 @@
#include <linux/phy_led_triggers.h>
#include <linux/pse-pd/pse.h>
#include <linux/property.h>
+#include <linux/regulator/consumer.h>
#include <linux/rtnetlink.h>
#include <linux/sfp.h>
#include <linux/skbuff.h>
@@ -3400,6 +3401,11 @@ static int phy_remove(struct device *dev)
phydev->drv = NULL;
+ if (phydev->regulator_cnt > 0)
+ regulator_bulk_disable(phydev->regulator_cnt, phydev->consumers);
+
+ kfree(phydev->consumers);
+
return 0;
}
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 3cc52826f18e..832cb2d4f76a 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -757,6 +757,9 @@ struct phy_device {
void (*phy_link_change)(struct phy_device *phydev, bool up);
void (*adjust_link)(struct net_device *dev);
+ int regulator_cnt;
+ struct regulator_bulk_data *consumers;
+
#if IS_ENABLED(CONFIG_MACSEC)
/* MACsec management functions */
const struct macsec_ops *macsec_ops;
--
2.43.0

View File

@ -24,7 +24,7 @@ Signed-off-by: Sebastian Meyer <git-commit@mailhell.seb7.de>
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
wifi_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
@@ -20,6 +30,10 @@

View File

@ -1,4 +1,4 @@
From 59cc76036f42c7f7baa17cb46e6e19cf3a6a62bb Mon Sep 17 00:00:00 2001
From 8f163618d4021cb84334109796c60f083fabda8d Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Sun, 26 Sep 2021 09:31:45 +0200
Subject: [PATCH] WIP: OPi3 DT fixes
@ -8,7 +8,7 @@ Subject: [PATCH] WIP: OPi3 DT fixes
1 file changed, 35 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index c45d7b7fb39a..af92d92d85a3 100644
index f005072c68a1..d01a318653a3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -63,27 +63,7 @@ reg_vcc5v: vcc5v {
@ -39,8 +39,8 @@ index c45d7b7fb39a..af92d92d85a3 100644
+
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
@@ -136,8 +116,8 @@ &mmc0 {
clocks = <&rtc CLK_OSC32K_FANOUT>;
@@ -137,8 +117,8 @@ &mmc0 {
};
&mmc1 {
@ -51,7 +51,7 @@ index c45d7b7fb39a..af92d92d85a3 100644
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
@@ -172,13 +152,17 @@ &ohci3 {
@@ -173,7 +153,7 @@ &ohci3 {
&pio {
vcc-pc-supply = <&reg_bldo2>;
vcc-pd-supply = <&reg_cldo1>;
@ -59,18 +59,8 @@ index c45d7b7fb39a..af92d92d85a3 100644
+ vcc-pg-supply = <&reg_bldo3>;
};
&r_ir {
status = "okay";
};
+&r_pio {
+ vcc-pm-supply = <&reg_bldo3>;
+};
+
&r_rsb {
status = "okay";
@@ -234,13 +218,12 @@ reg_bldo2: bldo2 {
&r_i2c {
@@ -231,13 +211,12 @@ reg_bldo2: bldo2 {
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-efuse-pcie-hdmi-pc";
};
@ -90,7 +80,7 @@ index c45d7b7fb39a..af92d92d85a3 100644
};
reg_cldo1: cldo1 {
@@ -250,19 +233,34 @@ reg_cldo1: cldo1 {
@@ -247,19 +226,34 @@ reg_cldo1: cldo1 {
regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
};
@ -131,6 +121,17 @@ index c45d7b7fb39a..af92d92d85a3 100644
regulator-name = "vdd-cpu";
};
@@ -296,6 +290,10 @@ &r_ir {
status = "okay";
};
+&r_pio {
+ vcc-pm-supply = <&reg_bldo3>;
+};
+
&rtc {
clocks = <&ext_osc32k>;
};
--
2.33.0
2.48.1

View File

@ -18,7 +18,7 @@ diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index d7c5e9b1a087..9944266c4f58 100644
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -593,10 +593,12 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
@@ -598,10 +598,12 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
{
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
struct sun50i_iommu *iommu = sun50i_domain->iommu;
@ -29,9 +29,9 @@ index d7c5e9b1a087..9944266c4f58 100644
+ pages = size / SPAGE_SIZE;
+
page_table = sun50i_dte_get_page_table(sun50i_domain, iova, gfp);
if (IS_ERR(page_table)) {
ret = PTR_ERR(page_table);
/* the IOMMU can only handle 32-bit addresses, both input and output */
if ((uint64_t)paddr >> 32) {
ret = -EINVAL;
@@ -604,18 +606,21 @@ static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iova,
}
@ -61,9 +61,9 @@ index d7c5e9b1a087..9944266c4f58 100644
- *pte_addr = sun50i_mk_pte(paddr, prot);
- sun50i_table_flush(sun50i_domain, pte_addr, 1);
+ sun50i_table_flush(sun50i_domain, &page_table[pte_index], pages);
*mapped = size;
out:
return ret;
@@ -626,8 +631,10 @@ static size_t sun50i_iommu_unmap(struct iommu_domain *domain, unsigned long iova
{
struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain);
@ -97,11 +97,11 @@ index d7c5e9b1a087..9944266c4f58 100644
static phys_addr_t sun50i_iommu_iova_to_phys(struct iommu_domain *domain,
@@ -828,7 +836,7 @@ static int sun50i_iommu_of_xlate(struct device *dev,
}
static const struct iommu_ops sun50i_iommu_ops = {
.identity_domain = &sun50i_iommu_identity_domain,
- .pgsize_bitmap = SZ_4K,
+ .pgsize_bitmap = 0x1ff000,
.device_group = sun50i_iommu_device_group,
.domain_alloc = sun50i_iommu_domain_alloc,
.device_group = generic_single_device_group,
.domain_alloc_paging = sun50i_iommu_domain_alloc_paging,
.of_xlate = sun50i_iommu_of_xlate,

View File

@ -1,29 +0,0 @@
From 667a93ec571a2a8f2487c258c928936d73b7fa14 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@gmail.com>
Date: Sun, 19 Feb 2023 13:02:31 +0100
Subject: [PATCH] ARM: dts: sun8i-r40: Add interconnect to video-codec
Video codec needs interconnect, so driver knows that it needs to adjust
DMA addresses.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
index 4ef26d8f5340..a5b1f1e3900d 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
@@ -338,6 +338,8 @@ video-codec@1c0e000 {
resets = <&ccu RST_BUS_VE>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
allwinner,sram = <&ve_sram 1>;
+ interconnects = <&mbus 4>;
+ interconnect-names = "dma-mem";
};
mmc0: mmc@1c0f000 {
--
2.39.2

View File

@ -17,16 +17,28 @@ Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 5 ++
2 files changed, 117 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -3,6 +3,7 @@
tristate "DRM Support for Allwinner A10 Display Engine"
depends on DRM && COMMON_CLK
depends on ARCH_SUNXI || COMPILE_TEST
+ select DRM_BRIDGE_CONNECTOR
select DRM_CLIENT_SELECTION
select DRM_GEM_DMA_HELPER
select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index 8f8d3bdba5ce..93831cdf1917 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -8,14 +8,82 @@
@@ -8,14 +8,90 @@
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge_connector.h>
+#include <drm/drm_edid.h>
#include <drm/drm_managed.h>
#include <drm/drm_modeset_helper_vtables.h>
#include <drm/drm_of.h>
@ -61,16 +73,23 @@ index 8f8d3bdba5ce..93831cdf1917 100644
+ enum drm_connector_status status)
+{
+ struct sun8i_dw_hdmi *hdmi = bridge_to_sun8i_dw_hdmi(bridge);
+ struct edid *edid;
+
+ if (!hdmi->cec_notifier)
+ return;
+
+ if (status == connector_status_connected) {
+ edid = drm_bridge_get_edid(hdmi->hdmi_bridge, hdmi->connector);
+ if (edid)
+ cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier,
+ edid);
+ const struct drm_edid *drm_edid;
+ const struct edid *edid;
+
+ drm_edid = drm_bridge_edid_read(hdmi->hdmi_bridge,
+ hdmi->connector);
+ if (drm_edid)
+ return;
+
+ edid = drm_edid_raw(drm_edid);
+ cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier,
+ edid);
+ drm_edid_free(drm_edid);
+ } else {
+ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
+ }

View File

@ -538,7 +538,7 @@ diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i
index 22e084989ee6..0837e2576556 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -7,18 +7,25 @@
@@ -7,19 +7,26 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@ -546,6 +546,7 @@ index 22e084989ee6..0837e2576556 100644
#include <drm/drm_atomic_state_helper.h>
#include <drm/drm_bridge_connector.h>
#include <drm/drm_edid.h>
#include <drm/drm_managed.h>
#include <drm/drm_modeset_helper_vtables.h>
#include <drm/drm_of.h>

View File

@ -16,10 +16,10 @@ diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2
index f4d9d6279094..1e07066fa129 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1510,6 +1510,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_PIX_FMT_AV1_FRAME: descr = "AV1 Frame"; break;
case V4L2_PIX_FMT_MT2110T: descr = "Mediatek 10bit Tile Mode"; break;
case V4L2_PIX_FMT_MT2110R: descr = "Mediatek 10bit Raster Mode"; break;
@@ -1542,6 +1542,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_PIX_FMT_PISP_COMP2_GBRG: descr = "PiSP 8b GBGB/RGRG mode2 compr"; break;
case V4L2_PIX_FMT_PISP_COMP2_BGGR: descr = "PiSP 8b BGBG/GRGR mode2 compr"; break;
case V4L2_PIX_FMT_PISP_COMP2_MONO: descr = "PiSP 8b monochrome mode2 compr"; break;
+ case V4L2_PIX_FMT_YUV420_8_AFBC_16X16_SPLIT: descr = "YUV 4:2:0 (AFBC 16x16)"; break;
+ case V4L2_PIX_FMT_YUV420_10_AFBC_16X16_SPLIT: descr = "10-bit YUV 4:2:0 (AFBC 16x16)"; break;
default:

View File

@ -17,22 +17,24 @@ diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8
index 884abe3cf773..91781b5bbbbc 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
@@ -365,6 +365,10 @@ struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
@@ -295,6 +295,11 @@ struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
if (!layer)
return ERR_PTR(-ENOMEM);
+ layer->mixer = mixer;
+ layer->type = SUN8I_LAYER_TYPE_UI;
+ layer->channel = channel;
+ layer->overlay = 0;
+
if (index == 0)
type = DRM_PLANE_TYPE_PRIMARY;
@@ -395,9 +399,6 @@ struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
@@ -325,10 +330,6 @@ struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
}
drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
- layer->mixer = mixer;
- layer->type = SUN8I_LAYER_TYPE_UI;
- layer->channel = channel;
- layer->overlay = 0;
@ -42,22 +44,24 @@ diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8
index 6ee3790a2a81..329e8bf8cd20 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -549,6 +549,10 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
@@ -478,6 +478,11 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
if (!layer)
return ERR_PTR(-ENOMEM);
+ layer->mixer = mixer;
+ layer->type = SUN8I_LAYER_TYPE_VI;
+ layer->channel = index;
+ layer->overlay = 0;
+
if (mixer->cfg->is_de3) {
formats = sun8i_vi_layer_de3_formats;
format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
@@ -607,9 +611,6 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
@@ -543,10 +549,6 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
}
drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
- layer->mixer = mixer;
- layer->type = SUN8I_LAYER_TYPE_VI;
- layer->channel = index;
- layer->overlay = 0;

View File

@ -372,6 +372,26 @@ index 000000000000..cea685c86855
+void sun50i_afbc_disable(struct sun8i_mixer *mixer, unsigned int channel);
+
+#endif
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -26,6 +26,7 @@
#include <uapi/linux/media-bus-format.h>
#include "sun4i_drv.h"
+#include "sun50i_afbc.h"
#include "sun50i_fmt.h"
#include "sun8i_mixer.h"
#include "sun8i_ui_layer.h"
@@ -272,6 +273,8 @@
val = enable ? SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN : 0;
mask = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
reg = SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay);
+ if (!enable && layer->mixer->cfg->is_de3)
+ sun50i_afbc_disable(layer->mixer, layer->channel);
}
regmap_update_bits(layer->mixer->engine.regs, reg, mask, val);
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 329e8bf8cd20..bda91c3e2bb7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@ -414,7 +434,7 @@ index 329e8bf8cd20..bda91c3e2bb7 100644
DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");
hm = src_w;
hn = scanline;
@@ -356,6 +358,15 @@ static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
@@ -307,6 +309,15 @@ static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
return 0;
}
@ -430,34 +450,20 @@ index 329e8bf8cd20..bda91c3e2bb7 100644
static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
@@ -399,6 +410,8 @@ static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
old_zpos);
+ if (mixer->cfg->is_de3)
+ sun50i_afbc_disable(mixer, layer->channel);
}
static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
@@ -411,26 +424,53 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
@@ -346,19 +357,44 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
plane);
struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
unsigned int zpos = new_state->normalized_zpos;
unsigned int old_zpos = old_state->normalized_zpos;
+ struct drm_framebuffer *fb = plane->state->fb;
struct sun8i_mixer *mixer = layer->mixer;
+ bool afbc = drm_is_afbc(fb->modifier);
if (!new_state->visible) {
sun8i_vi_layer_enable(mixer, layer->channel,
layer->overlay, false, 0, old_zpos);
+ if (mixer->cfg->is_de3)
+ sun50i_afbc_disable(mixer, layer->channel);
if (!new_state->crtc || !new_state->visible)
return;
}
+
+ if (afbc) {
+ u32 fmt_type;
+
+ sun8i_vi_layer_prepare_non_linear(mixer, layer->channel,
+ layer->overlay);
+ sun50i_afbc_atomic_update(mixer, layer->channel, plane);
@ -485,21 +491,17 @@ index 329e8bf8cd20..bda91c3e2bb7 100644
- sun8i_vi_layer_update_buffer(mixer, layer->channel,
- layer->overlay, plane);
+ layer->overlay, plane, zpos, afbc);
sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
true, zpos, old_zpos);
}
+}
+
+static bool sun8i_vi_layer_format_mod_supported(struct drm_plane *plane,
+ u32 format, u64 modifier)
+{
+ struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
+ struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+
+ return sun50i_afbc_format_mod_supported(layer->mixer, format, modifier);
+}
+
}
static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
.atomic_check = sun8i_vi_layer_atomic_check,
.atomic_disable = sun8i_vi_layer_atomic_disable,
@@ -444,6 +484,7 @@ static const struct drm_plane_funcs sun8i_vi_layer_funcs = {
.disable_plane = drm_atomic_helper_disable_plane,
.reset = drm_atomic_helper_plane_reset,
@ -536,13 +538,13 @@ index 329e8bf8cd20..bda91c3e2bb7 100644
+ DRM_FORMAT_MOD_INVALID
+};
+
struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
struct sun8i_mixer *mixer,
int index)
struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
struct sun8i_mixer *mixer,
int index)
@@ -542,6 +600,7 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
u32 supported_encodings, supported_ranges;
unsigned int plane_cnt, format_count;
struct sun8i_vi_layer *layer;
struct sun8i_layer *layer;
+ const uint64_t *modifiers;
const u32 *formats;
int ret;

View File

@ -201,7 +201,7 @@ index 581233d6eaf2..a5771b5d9b67 100644
static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -681,6 +756,14 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
@@ -681,6 +756,15 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
phy->variant = of_device_get_match_data(dev);
phy->dev = dev;
@ -209,6 +209,7 @@ index 581233d6eaf2..a5771b5d9b67 100644
+ of_machine_is_compatible("friendlyarm,nanopi-m1") ||
+ of_machine_is_compatible("xunlong,orangepi-lite") ||
+ of_machine_is_compatible("xunlong,orangepi-one") ||
+ of_machine_is_compatible("xunlong,orangepi-pc") ||
+ of_machine_is_compatible("xunlong,orangepi-pc-plus") ||
+ of_machine_is_compatible("xunlong,orangepi-plus2e");
+ phy->bit_bang_cec = phy->disable_cec &&
@ -216,18 +217,16 @@ index 581233d6eaf2..a5771b5d9b67 100644
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
@@ -727,8 +810,19 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
@@ -727,8 +810,17 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
return 0;
}
+static int sun8i_hdmi_phy_remove(struct platform_device *pdev)
+static void sun8i_hdmi_phy_remove(struct platform_device *pdev)
+{
+ struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev);
+
+ cec_notifier_cec_adap_unregister(phy->cec_notifier, phy->cec_adapter);
+ cec_unregister_adapter(phy->cec_adapter);
+
+ return 0;
+}
+
struct platform_driver sun8i_hdmi_phy_driver = {

View File

@ -0,0 +1,75 @@
From 1877122b4d0fef204f7076f4c28761cae9fcd807 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 15 Mar 2025 17:38:35 +0100
Subject: [PATCH 1/3] net: stmmac: sun8i: Use devm_regulator_get for PHY
regulator
Use devm_regulator_get instead of devm_regulator_get_optional and rely
on dummy supply. This avoids NULL checks before regulator_enable/disable
calls.
This path also improves error reporting, because we now report both
use of dummy supply and error during registration with more detail,
instead of generic info level message "No regulator found" that
was reported previously on errors and lack of regulator property in DT.
Finally, we'll be adding further optional regulators, and the overall
code will be simpler.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 23 ++++++++-----------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 4b7b2582a120..94a4898260b0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -588,12 +588,10 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
struct sunxi_priv_data *gmac = priv;
int ret;
- if (gmac->regulator) {
- ret = regulator_enable(gmac->regulator);
- if (ret) {
- dev_err(&pdev->dev, "Fail to enable regulator\n");
- return ret;
- }
+ ret = regulator_enable(gmac->regulator);
+ if (ret) {
+ dev_err(&pdev->dev, "Fail to enable regulator\n");
+ return ret;
}
if (gmac->use_internal_phy) {
@@ -1051,8 +1049,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
if (gmac->variant->soc_has_internal_phy)
sun8i_dwmac_unpower_internal_phy(gmac);
- if (gmac->regulator)
- regulator_disable(gmac->regulator);
+ regulator_disable(gmac->regulator);
}
static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
@@ -1176,12 +1173,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
/* Optional regulator for PHY */
- gmac->regulator = devm_regulator_get_optional(dev, "phy");
+ gmac->regulator = devm_regulator_get(dev, "phy");
if (IS_ERR(gmac->regulator)) {
- if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
- dev_info(dev, "No regulator found\n");
- gmac->regulator = NULL;
+ ret = PTR_ERR(gmac->regulator);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get PHY regulator (%d)\n", ret);
+ return ret;
}
/* The "GMAC clock control" register might be located in the
--
2.48.1

View File

@ -0,0 +1,92 @@
From a46ed6e8213c96d0905de691620cd473b0a2e45e Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 15 Mar 2025 17:49:23 +0100
Subject: [PATCH 2/3] net: stmmac: sun8i: Add support for enabling a regulator
for PHY I/O pins
Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
to the phy datasheet, both regulators need to be enabled at the same time.
Add support for the second optional regulator, "phy-io", to the glue
driver.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 23 ++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 94a4898260b0..da77e82f06d2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -61,6 +61,8 @@ struct emac_variant {
/* struct sunxi_priv_data - hold all sunxi private data
* @ephy_clk: reference to the optional EPHY clock for the internal PHY
* @regulator: reference to the optional regulator
+ * @regulator_phy_io: reference to the optional regulator for
+ * PHY I/O pins
* @rst_ephy: reference to the optional EPHY reset for the internal PHY
* @variant: reference to the current board variant
* @regmap: regmap for using the syscon
@@ -71,6 +73,7 @@ struct emac_variant {
struct sunxi_priv_data {
struct clk *ephy_clk;
struct regulator *regulator;
+ struct regulator *regulator_phy_io;
struct reset_control *rst_ephy;
const struct emac_variant *variant;
struct regmap_field *regmap_field;
@@ -588,10 +591,16 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
struct sunxi_priv_data *gmac = priv;
int ret;
+ ret = regulator_enable(gmac->regulator_phy_io);
+ if (ret) {
+ dev_err(&pdev->dev, "Fail to enable PHY I/O regulator\n");
+ return ret;
+ }
+
ret = regulator_enable(gmac->regulator);
if (ret) {
dev_err(&pdev->dev, "Fail to enable regulator\n");
- return ret;
+ goto err_disable_regulator_phy_io;
}
if (gmac->use_internal_phy) {
@@ -605,6 +614,8 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
err_disable_regulator:
if (gmac->regulator)
regulator_disable(gmac->regulator);
+err_disable_regulator_phy_io:
+ regulator_disable(gmac->regulator_phy_io);
return ret;
}
@@ -1050,6 +1061,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
sun8i_dwmac_unpower_internal_phy(gmac);
regulator_disable(gmac->regulator);
+ regulator_disable(gmac->regulator_phy_io);
}
static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
@@ -1181,6 +1193,15 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
return ret;
}
+ /* Optional regulator for PHY I/O pins */
+ gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io");
+ if (IS_ERR(gmac->regulator_phy_io)) {
+ ret = PTR_ERR(gmac->regulator_phy_io);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get PHY I/O regulator (%d)\n", ret);
+ return ret;
+ }
+
/* The "GMAC clock control" register might be located in the
* CCU address range (on the R40), or the system control address
* range (on most other sun8i and later SoCs).
--
2.48.1

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@ -1,12 +1,12 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
Date: Tue, 20 Aug 2019 14:54:48 +0200
Subject: [PATCH] arm64: dts: allwinner: orange-pi-3: Enable ethernet
From 2409d598b229dee9036f9ea2f14dde2647e8c114 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Sat, 15 Mar 2025 18:00:20 +0100
Subject: [PATCH 3/3] arm64: dts: allwinner: orange-pi-3: Enable ethernet
Orange Pi 3 has two regulators that power the Realtek RTL8211E
PHY. According to the datasheet, both regulators need to be enabled
at the same time, or that "phy-io" should be enabled slightly earlier
than "ephy" regulator.
than "phy" regulator.
RTL8211E/RTL8211EG datasheet says:
@ -14,26 +14,33 @@ RTL8211E/RTL8211EG datasheet says:
or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power
later than 3.3V power may lead to errors.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
The driver ensures the regulator enable ordering. The timing is set
in DT via startup-delay-us.
We also need to wait at least 30ms after power-up/reset, before
accessing the PHY registers.
All values of RX/TX delay were tested exhaustively and a middle one
of the range of working values was chosen.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 6fc65e8db220..df8b6de2b4d2 100644
index d01a318653a3..89049a7c0473 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -13,6 +13,7 @@ / {
compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
@@ -15,6 +15,7 @@ / {
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
+ ethernet0 = &emac;
};
@@ -55,6 +56,16 @@ led-1 {
chosen {
@@ -55,6 +56,15 @@ led-1 {
};
};
@ -44,21 +51,30 @@ index 6fc65e8db220..df8b6de2b4d2 100644
+ regulator-max-microvolt = <2500000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ off-on-delay-us = <100000>;
+ };
+
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the DC jack */
compatible = "regulator-fixed";
@@ -113,6 +124,33 @@ &ehci3 {
status = "okay";
@@ -108,6 +118,35 @@ hdmi_out_con: endpoint {
};
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&ext_rgmii_phy>;
+ /*
+ * The board uses 2.5V RGMII signalling. Power sequence to enable
+ * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
+ * at the same time and to wait 100ms. The driver enables phy-io
+ * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
+ */
+ phy-supply = <&reg_aldo2>;
+ phy-io-supply = <&reg_gmac_2v5>;
+ allwinner,rx-delay-ps = <1500>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
@ -66,14 +82,6 @@ index 6fc65e8db220..df8b6de2b4d2 100644
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ /*
+ * The board uses 2.5V RGMII signalling. Power sequence to enable
+ * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
+ * at the same time and to wait 100ms. The driver enables phy-io
+ * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
+ */
+ phy-io-supply = <&reg_gmac_2v5>;
+ ephy-supply = <&reg_aldo2>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
@ -81,10 +89,10 @@ index 6fc65e8db220..df8b6de2b4d2 100644
+ };
+};
+
&gpu {
mali-supply = <&reg_dcdcc>;
status = "okay";
@@ -211,6 +249,7 @@ reg_aldo2: aldo2 {
&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -188,6 +227,7 @@ reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc33-audio-tv-ephy-mac";
@ -92,3 +100,6 @@ index 6fc65e8db220..df8b6de2b4d2 100644
};
/* ALDO3 is shorted to CLDO1 */
--
2.48.1

View File

@ -1,7 +1,7 @@
From fa91cacc8756959b9b04b2cd3d369888b9a19e82 Mon Sep 17 00:00:00 2001
From 9a711d3aca9f7bd053caefec4f1bef07ba1a4817 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sat, 13 Apr 2019 05:41:51 +0000
Subject: [PATCH 01/53] LOCAL: set meson-gx cma pool to 896MB
Subject: [PATCH 01/37] LOCAL: set meson-gx cma pool to 896MB
This change sets the CMA pool to a larger 896MB! value for vdec use
@ -11,7 +11,7 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 2673f0dbafe7..5f9b0854c201 100644
index 7d99ca44e660..eebd4a4d388c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -58,7 +58,7 @@ secmon_reserved_bl32: secmon@5300000 {

View File

@ -1,7 +1,7 @@
From db61fd1f5ac1a4b39f7699ef5583db1464f2a419 Mon Sep 17 00:00:00 2001
From 5979e28bfa5986d47ba62f147feb5d9b83f16e6d Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 14 Aug 2019 19:58:14 +0000
Subject: [PATCH 02/53] LOCAL: set meson-g12 cma pool to 896MB
Subject: [PATCH 02/37] LOCAL: set meson-g12 cma pool to 896MB
This change sets the CMA pool to a larger 896MB! value for vdec use
@ -11,7 +11,7 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index ff68b911b729..f7f8df88d464 100644
index dcc927a9da80..0b6f13f8911b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -117,7 +117,7 @@ secmon_reserved_bl32: secmon@5300000 {

View File

@ -1,7 +1,7 @@
From ee6ecf00c056184730623b0a09f8e1ce0adb3d24 Mon Sep 17 00:00:00 2001
From 3df5b83cf844e053806a57afd5a4af8d11617c5d Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sat, 13 Apr 2019 05:45:18 +0000
Subject: [PATCH 03/53] LOCAL: arm64: fix Kodi sysinfo CPU information
Subject: [PATCH 03/37] LOCAL: arm64: fix Kodi sysinfo CPU information
This allows the CPU information to show in the Kodi sysinfo screen, e.g.
@ -9,23 +9,25 @@ This allows the CPU information to show in the Kodi sysinfo screen, e.g.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/kernel/cpuinfo.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
arch/arm64/kernel/cpuinfo.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 47043c0d95ec..03410a9fac77 100644
index c1f2b6b04b41..8bbdb64ec3ec 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -190,8 +190,7 @@ static int c_show(struct seq_file *m, void *v)
* "processor". Give glibc what it expects.
*/
seq_printf(m, "processor\t: %d\n", i);
- if (compat)
- seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
+ seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
@@ -221,9 +221,8 @@ static int c_show(struct seq_file *m, void *v)
* "processor". Give glibc what it expects.
*/
seq_printf(m, "processor\t: %d\n", cpu);
- if (compat)
- seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
- MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
+ seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
+ MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
loops_per_jiffy / (500000UL/HZ),
--
2.34.1

View File

@ -1,7 +1,7 @@
From 18375f3ce86dcec9a07f711b696aefb6fcb79829 Mon Sep 17 00:00:00 2001
From cacea1a7dcf9e69c3d1cfc1026a05a9332bf9837 Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Thu, 3 Nov 2016 15:29:23 +0100
Subject: [PATCH 04/53] LOCAL: arm64: meson: add Amlogic Meson GX PM Suspend
Subject: [PATCH 04/37] LOCAL: arm64: meson: add Amlogic Meson GX PM Suspend
The Amlogic Meson GX SoCs uses a non-standard argument to the
PSCI CPU_SUSPEND call to enter system suspend.

View File

@ -1,7 +1,7 @@
From 346f8f56697d21901ca2c5d48c7beecc654131c0 Mon Sep 17 00:00:00 2001
From ac95c04240bf6d1f12158f819bb9c0a0d06d6653 Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Thu, 3 Nov 2016 15:29:25 +0100
Subject: [PATCH 05/53] LOCAL: arm64: dts: meson: add support for GX PM and
Subject: [PATCH 05/37] LOCAL: arm64: dts: meson: add support for GX PM and
Virtual RTC
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
@ -10,7 +10,7 @@ Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 5f9b0854c201..b702a7f7bcf5 100644
index eebd4a4d388c..260628cf218e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -223,6 +223,10 @@ sm: secure-monitor {

View File

@ -1,7 +1,7 @@
From e288d4c79fb45f1af148b279bcfd091f770e9070 Mon Sep 17 00:00:00 2001
From 3198831b6d71337b85e5011fc820ea13057ab3a6 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Thu, 21 Jan 2021 01:35:36 +0000
Subject: [PATCH 06/53] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to
Subject: [PATCH 06/37] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to
Khadas VIM
Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1
@ -13,7 +13,7 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index fea65f20523a..dacbca73279c 100644
index 4e89d6f6bb57..e137ebd48c5e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -29,6 +29,8 @@ button-function {

View File

@ -1,7 +1,7 @@
From 1ebc6f1a726d896fb8c72ed5e86423ad2485eea1 Mon Sep 17 00:00:00 2001
From 596472232f2a08c7dd62597c9c041be4333e22b0 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sat, 6 Nov 2021 13:01:08 +0000
Subject: [PATCH 07/53] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to
Subject: [PATCH 07/37] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to
Khadas VIM2
Add aliases to ensure the vrtc time (which normally proves first) is /dev/rtc1
@ -13,7 +13,7 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index 860f307494c5..cee27e7222c8 100644
index 2a09b3d550e2..8a89940869b0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -18,6 +18,8 @@ / {

View File

@ -1,7 +1,7 @@
From 83e3e72c22bd9261d248c2dda723d5fb3abd4ab9 Mon Sep 17 00:00:00 2001
From a8f90df94245a52d5a0aff58a640b5c86e0ed83c Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 1 Feb 2021 19:27:40 +0000
Subject: [PATCH 08/53] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to Minix
Subject: [PATCH 08/37] LOCAL: arm64: dts: meson: add rtc/vrtc aliases to Minix
NEO U9-H
Add node aliases to prevent meson-vrtc from claiming /dev/rtc0

View File

@ -1,7 +1,7 @@
From b419174ce9cd28aa55673140319aa4317922d0d7 Mon Sep 17 00:00:00 2001
From e751b7cfeaca07cef1b14cebbd4dc567ed50ed37 Mon Sep 17 00:00:00 2001
From: Anssi Hannula <anssi.hannula@iki.fi>
Date: Sun, 17 Apr 2022 04:37:48 +0000
Subject: [PATCH 09/53] LOCAL: ASoC: meson: assign internal PCM
Subject: [PATCH 09/37] LOCAL: ASoC: meson: assign internal PCM
chmap/ELD/IEC958 kctls to device 0
On SoC sound devices utilizing codec2codec DAI links with an HDMI codec the kctls
@ -24,26 +24,26 @@ Tested-by: Christian Hewitt <christianshewitt@gmail.com>
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index 41103e5c43ce..0db7fe63911e 100644
index 6eaa950504cf..f2f05f1c4f98 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -2581,7 +2581,10 @@ int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream,
@@ -2612,7 +2612,10 @@ int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream,
knew.name = "Playback Channel Map";
else
knew.name = "Capture Channel Map";
- knew.device = pcm->device;
+ if (pcm->internal && pcm->device)
+ dev_info(pcm->card->dev, "workaround active: internal PCM chmap controls mapped to device 0\n");
+ dev_info(pcm->card->dev, "workaround: internal PCM chmap controls mapped to device 0\n");
+ else
+ knew.device = pcm->device;
knew.count = pcm->streams[stream].substream_count;
knew.private_value = private_value;
info->kctl = snd_ctl_new1(&knew, info);
diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
index d3abb7ce2153..e06b28c7e5ba 100644
index 31121f9c18c9..606abb3889c1 100644
--- a/sound/soc/codecs/hdmi-codec.c
+++ b/sound/soc/codecs/hdmi-codec.c
@@ -802,7 +802,8 @@ static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd,
@@ -821,7 +821,8 @@ static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd,
if (!kctl)
return -ENOMEM;

View File

@ -1,7 +1,7 @@
From 9787871fe1e00af9f915237be4474a3b1f1e0887 Mon Sep 17 00:00:00 2001
From 3de630c16f0ddbaa6442ebc3b6938bc1c4526b34 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Thu, 5 Jan 2023 15:16:46 +0000
Subject: [PATCH 10/53] LOCAL: media: meson: vdec: disable MPEG1/MPEG2 hardware
Subject: [PATCH 10/37] LOCAL: media: meson: vdec: disable MPEG1/MPEG2 hardware
decoding
The MPEG1/2 decoder is broken and nobody has volunteered to poke
@ -11,11 +11,11 @@ hardware decoding for now.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../staging/media/meson/vdec/vdec_platform.c | 110 ------------------
1 file changed, 110 deletions(-)
.../staging/media/meson/vdec/vdec_platform.c | 132 ------------------
1 file changed, 132 deletions(-)
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
index 70c9fd7c8bc5..f1df637681e5 100644
index 66bb307db85a..8a7e5b3f5d00 100644
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
@@ -26,28 +26,6 @@ static const struct amvdec_format vdec_formats_gxbb[] = {
@ -76,7 +76,7 @@ index 70c9fd7c8bc5..f1df637681e5 100644
},
};
@@ -126,28 +82,6 @@ static const struct amvdec_format vdec_formats_gxm[] = {
@@ -114,28 +70,6 @@ static const struct amvdec_format vdec_formats_gxlx[] = {
.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
.flags = V4L2_FMT_FLAG_COMPRESSED |
V4L2_FMT_FLAG_DYN_RESOLUTION,
@ -105,7 +105,7 @@ index 70c9fd7c8bc5..f1df637681e5 100644
},
};
@@ -176,28 +110,6 @@ static const struct amvdec_format vdec_formats_g12a[] = {
@@ -164,28 +98,6 @@ static const struct amvdec_format vdec_formats_gxm[] = {
.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
.flags = V4L2_FMT_FLAG_COMPRESSED |
V4L2_FMT_FLAG_DYN_RESOLUTION,
@ -134,7 +134,36 @@ index 70c9fd7c8bc5..f1df637681e5 100644
},
};
@@ -226,28 +138,6 @@ static const struct amvdec_format vdec_formats_sm1[] = {
@@ -214,28 +126,6 @@ static const struct amvdec_format vdec_formats_g12a[] = {
.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
.flags = V4L2_FMT_FLAG_COMPRESSED |
V4L2_FMT_FLAG_DYN_RESOLUTION,
- }, {
- .pixfmt = V4L2_PIX_FMT_MPEG1,
- .min_buffers = 8,
- .max_buffers = 8,
- .max_width = 1920,
- .max_height = 1080,
- .vdec_ops = &vdec_1_ops,
- .codec_ops = &codec_mpeg12_ops,
- .firmware_path = "meson/vdec/gxl_mpeg12.bin",
- .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
- .flags = V4L2_FMT_FLAG_COMPRESSED,
- }, {
- .pixfmt = V4L2_PIX_FMT_MPEG2,
- .min_buffers = 8,
- .max_buffers = 8,
- .max_width = 1920,
- .max_height = 1080,
- .vdec_ops = &vdec_1_ops,
- .codec_ops = &codec_mpeg12_ops,
- .firmware_path = "meson/vdec/gxl_mpeg12.bin",
- .pixfmts_cap = { V4L2_PIX_FMT_NV12M, V4L2_PIX_FMT_YUV420M, 0 },
- .flags = V4L2_FMT_FLAG_COMPRESSED,
},
};
@@ -264,28 +154,6 @@ static const struct amvdec_format vdec_formats_sm1[] = {
.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
.flags = V4L2_FMT_FLAG_COMPRESSED |
V4L2_FMT_FLAG_DYN_RESOLUTION,

View File

@ -1,31 +0,0 @@
From f376bb7ba1afbca87fba7b98f31697cba6776b1b Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Mon, 16 Oct 2023 10:02:03 +0200
Subject: [PATCH 11/53] FROMGIT(6.9): arm64: dts: meson-g12-common: Set the
rates of the clocks for the NPU
Otherwise they are left at 24MHz and the NPU runs very slowly.
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Suggested-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index f7f8df88d464..a960d07f9af3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -2502,6 +2502,9 @@ npu: npu@ff100000 {
clocks = <&clkc CLKID_NNA_CORE_CLK>,
<&clkc CLKID_NNA_AXI_CLK>;
clock-names = "core", "bus";
+ assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>,
+ <&clkc CLKID_NNA_AXI_CLK>;
+ assigned-clock-rates = <800000000>, <800000000>;
resets = <&reset RESET_NNA>;
status = "disabled";
};
--
2.34.1

View File

@ -0,0 +1,138 @@
From 4c895bf75fbf67654d02032cfbdfa57fa4777b20 Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Wed, 9 Apr 2025 23:44:22 +0200
Subject: [PATCH 11/37] FROMLIST(v1): drm/meson: fix resource cleanup in
meson_drv_bind_master() on error
meson_drv_bind_master() does not free resources in the order they are
allocated. This can lead to crashes such as:
Unable to handle kernel NULL pointer dereference at virtual address 00000000000000c8
[...]
Hardware name: Beelink GT-King Pro (DT)
pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : meson_dw_hdmi_unbind+0x10/0x24 [meson_dw_hdmi]
lr : component_unbind+0x38/0x60
[...]
Call trace:
meson_dw_hdmi_unbind+0x10/0x24 [meson_dw_hdmi]
component_unbind+0x38/0x60
component_unbind_all+0xb8/0xc4
meson_drv_bind_master+0x1ec/0x514 [meson_drm]
meson_drv_bind+0x14/0x20 [meson_drm]
try_to_bring_up_aggregate_device+0xa8/0x160
__component_add+0xb8/0x1a8
component_add+0x14/0x20
meson_dw_hdmi_probe+0x1c/0x28 [meson_dw_hdmi]
platform_probe+0x68/0xdc
really_probe+0xc0/0x39c
__driver_probe_device+0x7c/0x14c
driver_probe_device+0x3c/0x120
__driver_attach+0xc4/0x200
bus_for_each_dev+0x78/0xd8
driver_attach+0x24/0x30
bus_add_driver+0x110/0x240
driver_register+0x68/0x124
__platform_driver_register+0x24/0x30
meson_dw_hdmi_platform_driver_init+0x20/0x1000 [meson_dw_hdmi]
do_one_initcall+0x50/0x1bc
do_init_module+0x54/0x1fc
load_module+0x788/0x884
init_module_from_file+0x88/0xd4
__arm64_sys_finit_module+0x248/0x340
invoke_syscall+0x48/0x104
el0_svc_common.constprop.0+0x40/0xe0
do_el0_svc+0x1c/0x28
el0_svc+0x30/0xcc
el0t_64_sync_handler+0x120/0x12c
el0t_64_sync+0x190/0x194
Clean up resources in the error path in the same order and under the
same conditions as they were allocated to fix this.
Reported-by: Furkan Kardame <f.kardame@manjaro.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/gpu/drm/meson/meson_drv.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
index 49ff9f1f16d3..ea5bda297a74 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -314,35 +314,35 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
dev_err(drm->dev, "Couldn't bind all components\n");
/* Do not try to unbind */
has_components = false;
- goto exit_afbcd;
+ goto cvbs_encoder_remove;
}
}
ret = meson_encoder_hdmi_probe(priv);
if (ret)
- goto exit_afbcd;
+ goto unbind_components;
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
ret = meson_encoder_dsi_probe(priv);
if (ret)
- goto exit_afbcd;
+ goto hdmi_encoder_remove;
}
ret = meson_plane_create(priv);
if (ret)
- goto exit_afbcd;
+ goto dsi_encoder_remove;
ret = meson_overlay_create(priv);
if (ret)
- goto exit_afbcd;
+ goto dsi_encoder_remove;
ret = meson_crtc_create(priv);
if (ret)
- goto exit_afbcd;
+ goto dsi_encoder_remove;
ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
if (ret)
- goto exit_afbcd;
+ goto dsi_encoder_remove;
drm_mode_config_reset(drm);
@@ -360,6 +360,16 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
uninstall_irq:
free_irq(priv->vsync_irq, drm);
+dsi_encoder_remove:
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
+ meson_encoder_dsi_remove(priv);
+hdmi_encoder_remove:
+ meson_encoder_hdmi_remove(priv);
+unbind_components:
+ if (has_components)
+ component_unbind_all(dev, drm);
+cvbs_encoder_remove:
+ meson_encoder_cvbs_remove(priv);
exit_afbcd:
if (priv->afbcd.ops)
priv->afbcd.ops->exit(priv);
@@ -374,13 +384,6 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
free_drm:
drm_dev_put(drm);
- meson_encoder_dsi_remove(priv);
- meson_encoder_hdmi_remove(priv);
- meson_encoder_cvbs_remove(priv);
-
- if (has_components)
- component_unbind_all(dev, drm);
-
return ret;
}
--
2.34.1

View File

@ -0,0 +1,60 @@
From 6745bff6c6c1ee1746c955504a3ea32d12ec8d79 Mon Sep 17 00:00:00 2001
From: Zhang Kunbo <zhangkunbo@huawei.com>
Date: Wed, 6 Nov 2024 02:45:48 +0000
Subject: [PATCH 12/37] FROMLIST(v1): drm/meson: Avoid use-after-free issues
with crtc
It's dangerous to call drm_crtc_init_with_planes() whose second
argument is allocated with devm_kzalloc() [1][2].
Use drmm_kzalloc instead to avoid UAF.
[1] https://lore.kernel.org/all/a830685d8b10a00cfe0a86db1ee9fb13@ispras.ru
[2] https://lore.kernel.org/all/2111196.TG1k3f53YQ@avalon
Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller")
Signed-off-by: Zhang Kunbo <zhangkunbo@huawei.com>
---
drivers/gpu/drm/meson/meson_crtc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
index d70616da8ce2..603022554a48 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -17,6 +17,7 @@
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
+#include <drm/drm_managed.h>
#include "meson_crtc.h"
#include "meson_plane.h"
@@ -72,7 +73,6 @@ static void meson_crtc_disable_vblank(struct drm_crtc *crtc)
static const struct drm_crtc_funcs meson_crtc_funcs = {
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
- .destroy = drm_crtc_cleanup,
.page_flip = drm_atomic_helper_page_flip,
.reset = drm_atomic_helper_crtc_reset,
.set_config = drm_atomic_helper_set_config,
@@ -677,14 +677,14 @@ int meson_crtc_create(struct meson_drm *priv)
struct drm_crtc *crtc;
int ret;
- meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
+ meson_crtc = drmm_kzalloc(priv->drm, sizeof(*meson_crtc),
GFP_KERNEL);
if (!meson_crtc)
return -ENOMEM;
meson_crtc->priv = priv;
crtc = &meson_crtc->base;
- ret = drm_crtc_init_with_planes(priv->drm, crtc,
+ ret = drmm_crtc_init_with_planes(priv->drm, crtc,
priv->primary_plane, NULL,
&meson_crtc_funcs, "meson_crtc");
if (ret) {
--
2.34.1

View File

@ -0,0 +1,69 @@
From 4babe8c6a677ed0f21cf518c8ce78caecc8963b8 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Fri, 7 Feb 2025 04:29:08 +0000
Subject: [PATCH 13/37] FROMLIST(v2): media: si2168: increase cmd execution
timeout value
Testing with a MyGica T230C v2 USB device (0572:c68a) shows occasional
cmd timeouts that cause Tvheadend services to fail:
Jan 28 12:23:46.788180 LibreELEC kernel: si2168 1-0060: cmd execution took 0 ms
Jan 28 12:23:46.790799 LibreELEC kernel: si2168 1-0060: cmd execution took 0 ms
Jan 28 12:23:46.878158 LibreELEC kernel: si2168 1-0060: cmd execution took 80 ms
Jan 28 12:23:46.879158 LibreELEC kernel: si2168 1-0060: failed=-110
Jan 28 12:23:46.879908 LibreELEC kernel: si2168 1-0060: failed=-110
Jan 28 12:23:46.948234 LibreELEC kernel: si2168 1-0060: cmd execution took 60 ms
Jan 28 12:23:46.949121 LibreELEC kernel: si2168 1-0060: cmd execution took 0 ms
Jan 28 12:23:46.949940 LibreELEC kernel: si2168 1-0060: cmd execution took 10 ms
..
Jan 28 12:23:57.457216 LibreELEC tvheadend[3126]: subscription: 009B: service instance is bad, reason: No input detected
Jan 28 12:23:57.457392 LibreELEC tvheadend[3126]: linuxdvb: Silicon Labs Si2168 #0 : DVB-T #0 - stopping 778MHz in DVB-T Network
..
Jan 28 12:23:57.457584 LibreELEC tvheadend[3126]: subscription: 009B: No input source available for subscription "127.0.0.1 [ | Kodi Media Center ]" to channel "XXXXXXX"
The original timeout of 50ms was extended to 70ms in commit 551c33e729f6
("[media] Si2168: increase timeout to fix firmware loading") but testing
shows there are other demux commands that take longer. The largest value
observed from user reports/logs is 150ms so increase timeout to 200ms.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/media/dvb-frontends/si2168.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/media/dvb-frontends/si2168.c b/drivers/media/dvb-frontends/si2168.c
index d6b6b8bc7d4e..843f1e01318e 100644
--- a/drivers/media/dvb-frontends/si2168.c
+++ b/drivers/media/dvb-frontends/si2168.c
@@ -9,6 +9,8 @@
#include "si2168_priv.h"
+#define CMD_TIMEOUT 200
+
static const struct dvb_frontend_ops si2168_ops;
static void cmd_init(struct si2168_cmd *cmd, const u8 *buf, int wlen, int rlen)
@@ -40,8 +42,7 @@ static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd)
if (cmd->rlen) {
/* wait cmd execution terminate */
- #define TIMEOUT 70
- timeout = jiffies + msecs_to_jiffies(TIMEOUT);
+ timeout = jiffies + msecs_to_jiffies(CMD_TIMEOUT);
while (!time_after(jiffies, timeout)) {
ret = i2c_master_recv(client, cmd->args, cmd->rlen);
if (ret < 0) {
@@ -58,7 +59,7 @@ static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd)
dev_dbg(&client->dev, "cmd execution took %d ms\n",
jiffies_to_msecs(jiffies) -
- (jiffies_to_msecs(timeout) - TIMEOUT));
+ (jiffies_to_msecs(timeout) - CMD_TIMEOUT));
/* error bit set? */
if ((cmd->args[0] >> 6) & 0x01) {
--
2.34.1

View File

@ -1,7 +1,7 @@
From b4b3656688319a77827ce533f8797f317dfaa01c Mon Sep 17 00:00:00 2001
From 3eb58e53708f534a47f4cccbd44efa36d5584a5c Mon Sep 17 00:00:00 2001
From: Neil Armstrong <narmstrong@baylibre.com>
Date: Mon, 22 Nov 2021 09:15:21 +0000
Subject: [PATCH 20/53] FROMLIST(v1): media: meson: vdec: esparser: check
Subject: [PATCH 14/37] FROMLIST(v1): media: meson: vdec: esparser: check
parsing state with hardware write pointer
Also check the hardware write pointer to check if ES Parser has stalled.

View File

@ -1,114 +0,0 @@
From 24712c83de1ef21e7263f7c3bbe4423068070089 Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Sun, 20 Feb 2022 08:24:47 +0000
Subject: [PATCH 14/53] FROMLIST(v5): dt-bindings: auxdisplay: Add Titan Micro
Electronics TM1628
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add a YAML schema binding for TM1628 auxdisplay
(7/11-segment LED) controller.
This patch is partially based on previous RFC work from
Andreas Färber <afaerber@suse.de>.
Co-developed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
.../bindings/auxdisplay/titanmec,tm1628.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml
diff --git a/Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml b/Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml
new file mode 100644
index 000000000000..d9cbbc950aab
--- /dev/null
+++ b/Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/titanmec,tm1628.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Titan Micro Electronics TM1628 LED controller
+
+properties:
+ compatible:
+ enum:
+ - titanmec,tm1628
+
+ reg:
+ maxItems: 1
+
+ grid:
+ description:
+ Mapping of display digit position to grid number.
+ This implicitly defines the display size.
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ minItems: 1
+ maxItems: 7
+
+ segment-mapping:
+ description:
+ Mapping of 7 segment display segments A-G to bit numbers 1-12.
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ minItems: 7
+ maxItems: 7
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+patternProperties:
+ "^.*@[1-7],([1-9]|1[0-6])$":
+ type: object
+ description: |
+ Properties for a single LED.
+
+ properties:
+ reg:
+ description: |
+ 1-based grid number, followed by 1-based segment bit number.
+ maxItems: 1
+
+ required:
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@0 {
+ compatible = "titanmec,tm1628";
+ reg = <0>;
+ spi-3-wire;
+ spi-lsb-first;
+ spi-max-frequency = <500000>;
+ grid = /bits/ 8 <4 3 2 1>;
+ segment-mapping = /bits/ 8 <4 5 6 1 2 3 7>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ alarmn@5,4 {
+ reg = <5 4>;
+ function = LED_FUNCTION_ALARM;
+ };
+ };
+ };
+...
--
2.34.1

View File

@ -1,7 +1,7 @@
From 73aa203801527e081409ead1c5708552ecc5f82b Mon Sep 17 00:00:00 2001
From 61874bc3835b2326bb40bae200888657e7d38fa3 Mon Sep 17 00:00:00 2001
From: Benjamin Roszak <benjamin545@gmail.com>
Date: Mon, 23 Jan 2023 10:56:46 +0000
Subject: [PATCH 21/53] FROMLIST(v2): media: meson: vdec: implement 10bit
Subject: [PATCH 15/37] FROMLIST(v2): media: meson: vdec: implement 10bit
bitstream handling
In order to support 10bit bitstream decoding, buffers and MMU
@ -453,10 +453,10 @@ index baf0dba3c418..ef6dd05d89c8 100644
return -EAGAIN;
}
diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
index 0906b8fb5cc6..a48170fe4cff 100644
index 258685177700..e1e731b7d431 100644
--- a/drivers/staging/media/meson/vdec/vdec.h
+++ b/drivers/staging/media/meson/vdec/vdec.h
@@ -244,6 +244,7 @@ struct amvdec_session {
@@ -243,6 +243,7 @@ struct amvdec_session {
u32 width;
u32 height;
u32 colorspace;

View File

@ -1,31 +0,0 @@
From 35a48968c689d245bbe3dd2ff5cd9192d3a16e62 Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Sun, 20 Feb 2022 08:26:27 +0000
Subject: [PATCH 15/53] FROMLIST(v5): docs: ABI: document tm1628 attribute
display-text
Document the attribute for reading / writing the text to be displayed on
the 7 segment display.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628 | 7 +++++++
1 file changed, 7 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628
diff --git a/Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628 b/Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628
new file mode 100644
index 000000000000..382757e721af
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628
@@ -0,0 +1,7 @@
+What: /sys/devices/.../display-text
+Date: February 2022
+Contact: Heiner Kallweit <hkallweit1@gmail.com>
+Description:
+ The text to be displayed on the 7 segment display.
+ Any printable character is allowed as input, but some
+ can not be displayed in a readable way with 7 segments.
--
2.34.1

View File

@ -1,7 +1,7 @@
From 00829e834a4cd6594b076550fd18be30ddba5b0e Mon Sep 17 00:00:00 2001
From befb64847f9d38e20a38ed9ca3e351a4d80e9d05 Mon Sep 17 00:00:00 2001
From: Maxime Jourdan <mjourdan@baylibre.com>
Date: Mon, 23 Jan 2023 11:07:04 +0000
Subject: [PATCH 22/53] FROMLIST(v2): media: meson: vdec: add HEVC decode codec
Subject: [PATCH 16/37] FROMLIST(v2): media: meson: vdec: add HEVC decode codec
Add initial HEVC codec for the Amlogic GXBB/GXL/GXM SoCs using
the common "HEVC" decoder driver.
@ -15,8 +15,8 @@ Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
drivers/staging/media/meson/vdec/codec_hevc.h | 13 +
drivers/staging/media/meson/vdec/esparser.c | 3 +-
drivers/staging/media/meson/vdec/hevc_regs.h | 1 +
.../staging/media/meson/vdec/vdec_platform.c | 37 +
6 files changed, 1516 insertions(+), 2 deletions(-)
.../staging/media/meson/vdec/vdec_platform.c | 49 +
6 files changed, 1528 insertions(+), 2 deletions(-)
create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c
create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h
@ -1546,7 +1546,7 @@ index 0392f41a1eed..e7eabdd2b119 100644
#define HEVC_SAO_MMU_VH1_ADDR 0xd8ec
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
index f1df637681e5..083adf0d07d9 100644
index 8a7e5b3f5d00..870e61dedd81 100644
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
@@ -11,10 +11,23 @@
@ -1592,7 +1592,26 @@ index f1df637681e5..083adf0d07d9 100644
}, {
.pixfmt = V4L2_PIX_FMT_H264,
.min_buffers = 2,
@@ -70,6 +95,18 @@ static const struct amvdec_format vdec_formats_gxm[] = {
@@ -59,6 +84,18 @@ static const struct amvdec_format vdec_formats_gxl[] = {
static const struct amvdec_format vdec_formats_gxlx[] = {
{
+ .pixfmt = V4L2_PIX_FMT_HEVC,
+ .min_buffers = 4,
+ .max_buffers = 24,
+ .max_width = 3840,
+ .max_height = 2160,
+ .vdec_ops = &vdec_hevc_ops,
+ .codec_ops = &codec_hevc_ops,
+ .firmware_path = "meson/vdec/gxl_hevc.bin",
+ .pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+ .flags = V4L2_FMT_FLAG_COMPRESSED |
+ V4L2_FMT_FLAG_DYN_RESOLUTION,
+ }, {
.pixfmt = V4L2_PIX_FMT_H264,
.min_buffers = 2,
.max_buffers = 24,
@@ -86,6 +123,18 @@ static const struct amvdec_format vdec_formats_gxm[] = {
.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
.flags = V4L2_FMT_FLAG_COMPRESSED |
V4L2_FMT_FLAG_DYN_RESOLUTION,

View File

@ -1,461 +0,0 @@
From e7c3f45587cda5b5b445df7434f38a0d751bb197 Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Mon, 4 Apr 2022 18:51:20 +0000
Subject: [PATCH 16/53] FROMLIST(v5): auxdisplay: add support for Titanmec
TM1628 7 segment display controller
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This patch adds support for the Titanmec TM1628 7 segment display
controller. It's based on previous RFC work from Andreas Färber.
The RFC version placed the driver in the LED subsystem, but this was
NAK'ed by the LED maintainer. Therefore I moved the driver to
/drivers/auxdisplay what seems most reasonable to me.
Further changes to the RFC version:
- Driver can be built also w/o LED class support, for displays that
don't have any symbols to be exposed as LED's.
- Simplified the code and rewrote a lot of it.
- Driver is now kind of a MVP, but functionality should be sufficient
for most use cases.
- Use the existing 7 segment support in uapi/linux/map_to_7segment.h
as suggested by Geert Uytterhoeven.
Note: There's a number of chips from other manufacturers that are
almost identical, e.g. FD628, SM1628. Only difference I saw so
far is that they partially support other display modes.
TM1628: 6x12, 7x11
SM1628C: 4x13, 5x12, 6x11, 7x10
For typical displays on devices using these chips this
difference shouldn't matter.
Successfully tested on a TX3 Mini TV box that has an SM1628C and a
display with 4 digits and 7 symbols.
Co-developed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
drivers/auxdisplay/Kconfig | 11 ++
drivers/auxdisplay/Makefile | 1 +
drivers/auxdisplay/tm1628.c | 376 ++++++++++++++++++++++++++++++++++++
3 files changed, 388 insertions(+)
create mode 100644 drivers/auxdisplay/tm1628.c
diff --git a/drivers/auxdisplay/Kconfig b/drivers/auxdisplay/Kconfig
index d944d5298eca..f3d513139e5c 100644
--- a/drivers/auxdisplay/Kconfig
+++ b/drivers/auxdisplay/Kconfig
@@ -197,6 +197,17 @@ config ARM_CHARLCD
line and the Linux version on the second line, but that's
still useful.
+config TM1628
+ tristate "TM1628 driver for LED 7/11 segment displays"
+ depends on SPI
+ depends on OF || COMPILE_TEST
+ help
+ Say Y to enable support for Titan Micro Electronics TM1628
+ LED controller.
+
+ It's a 3-wire SPI device controlling a two-dimensional grid of
+ LEDs. Dimming is applied to all outputs through an internal PWM.
+
menuconfig PARPORT_PANEL
tristate "Parallel port LCD/Keypad Panel support"
depends on PARPORT
diff --git a/drivers/auxdisplay/Makefile b/drivers/auxdisplay/Makefile
index 6968ed4d3f0a..7728e17e1c5a 100644
--- a/drivers/auxdisplay/Makefile
+++ b/drivers/auxdisplay/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_HT16K33) += ht16k33.o
obj-$(CONFIG_PARPORT_PANEL) += panel.o
obj-$(CONFIG_LCD2S) += lcd2s.o
obj-$(CONFIG_LINEDISP) += line-display.o
+obj-$(CONFIG_TM1628) += tm1628.o
diff --git a/drivers/auxdisplay/tm1628.c b/drivers/auxdisplay/tm1628.c
new file mode 100644
index 000000000000..4d99a7aa077b
--- /dev/null
+++ b/drivers/auxdisplay/tm1628.c
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Titan Micro Electronics TM1628 LED controller
+ *
+ * Copyright (c) 2019 Andreas Färber
+ * Copyright (c) 2022 Heiner Kallweit
+ */
+
+#include <linux/ctype.h>
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/spi/spi.h>
+#include <uapi/linux/map_to_7segment.h>
+
+#define TM1628_CMD_DISPLAY_MODE (0 << 6)
+#define TM1628_DISPLAY_MODE_6_12 0x02
+#define TM1628_DISPLAY_MODE_7_11 0x03
+
+#define TM1628_CMD_DATA (1 << 6)
+#define TM1628_DATA_TEST_MODE BIT(3)
+#define TM1628_DATA_FIXED_ADDR BIT(2)
+#define TM1628_DATA_WRITE_DATA 0x00
+#define TM1628_DATA_READ_DATA 0x02
+
+#define TM1628_CMD_DISPLAY_CTRL (2 << 6)
+#define TM1628_DISPLAY_CTRL_DISPLAY_ON BIT(3)
+
+#define TM1628_CMD_SET_ADDRESS (3 << 6)
+
+#define TM1628_BRIGHTNESS_MAX 7
+#define NUM_LED_SEGS 7
+
+/* Physical limits, depending on the mode the chip may support less */
+#define MAX_GRID_SIZE 7
+#define MAX_SEGMENT_NUM 16
+
+struct tm1628_led {
+ struct led_classdev leddev;
+ struct tm1628 *ctrl;
+ u32 grid;
+ u32 seg;
+};
+
+struct tm1628 {
+ struct spi_device *spi;
+ __le16 data[MAX_GRID_SIZE];
+ struct mutex disp_lock;
+ char text[MAX_GRID_SIZE + 1];
+ u8 segment_mapping[NUM_LED_SEGS];
+ u8 grid[MAX_GRID_SIZE];
+ int grid_size;
+ struct tm1628_led leds[];
+};
+
+/* Command 1: Display Mode Setting */
+static int tm1628_set_display_mode(struct spi_device *spi, u8 grid_mode)
+{
+ const u8 cmd = TM1628_CMD_DISPLAY_MODE | grid_mode;
+
+ return spi_write(spi, &cmd, 1);
+}
+
+/* Command 3: Address Setting */
+static int tm1628_set_address(struct spi_device *spi, u8 offset)
+{
+ const u8 cmd = TM1628_CMD_SET_ADDRESS | (offset * sizeof(__le16));
+
+ return spi_write(spi, &cmd, 1);
+}
+
+/* Command 2: Data Setting */
+static int tm1628_write_data(struct spi_device *spi, unsigned int offset,
+ unsigned int len)
+{
+ struct tm1628 *s = spi_get_drvdata(spi);
+ const u8 cmd = TM1628_CMD_DATA | TM1628_DATA_WRITE_DATA;
+ struct spi_transfer xfers[] = {
+ {
+ .tx_buf = &cmd,
+ .len = 1,
+ },
+ {
+ .tx_buf = (__force void *)(s->data + offset),
+ .len = len * sizeof(__le16),
+ },
+ };
+
+ if (offset + len > MAX_GRID_SIZE) {
+ dev_err(&spi->dev, "Invalid data address offset %u len %u\n",
+ offset, len);
+ return -EINVAL;
+ }
+
+ tm1628_set_address(spi, offset);
+
+ return spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers));
+}
+
+/* Command 4: Display Control */
+static int tm1628_set_display_ctrl(struct spi_device *spi, bool on)
+{
+ u8 cmd = TM1628_CMD_DISPLAY_CTRL | TM1628_BRIGHTNESS_MAX;
+
+ if (on)
+ cmd |= TM1628_DISPLAY_CTRL_DISPLAY_ON;
+
+ return spi_write(spi, &cmd, 1);
+}
+
+static int tm1628_show_text(struct tm1628 *s)
+{
+ static SEG7_CONVERSION_MAP(map_seg7, MAP_ASCII7SEG_ALPHANUM);
+ int msg_len, i, ret;
+
+ msg_len = strlen(s->text);
+
+ mutex_lock(&s->disp_lock);
+
+ for (i = 0; i < s->grid_size; i++) {
+ int pos = s->grid[i] - 1;
+ int j, char7_raw, char7;
+
+ if (i >= msg_len) {
+ s->data[pos] = 0;
+ continue;
+ }
+
+ char7_raw = map_to_seg7(&map_seg7, s->text[i]);
+
+ for (j = 0, char7 = 0; j < NUM_LED_SEGS; j++) {
+ if (char7_raw & BIT(j))
+ char7 |= BIT(s->segment_mapping[j] - 1);
+ }
+
+ s->data[pos] = cpu_to_le16(char7);
+ }
+
+ ret = tm1628_write_data(s->spi, 0, s->grid_size);
+
+ mutex_unlock(&s->disp_lock);
+
+ return ret;
+}
+
+static int tm1628_led_set_brightness(struct led_classdev *led_cdev,
+ enum led_brightness brightness)
+{
+ struct tm1628_led *led = container_of(led_cdev, struct tm1628_led, leddev);
+ struct tm1628 *s = led->ctrl;
+ int ret, offset = led->grid - 1;
+ __le16 bit = cpu_to_le16(BIT(led->seg - 1));
+
+ mutex_lock(&s->disp_lock);
+
+ if (brightness == LED_OFF)
+ s->data[offset] &= ~bit;
+ else
+ s->data[offset] |= bit;
+
+ ret = tm1628_write_data(s->spi, offset, 1);
+
+ mutex_unlock(&s->disp_lock);
+
+ return ret;
+}
+
+static enum led_brightness tm1628_led_get_brightness(struct led_classdev *led_cdev)
+{
+ struct tm1628_led *led = container_of(led_cdev, struct tm1628_led, leddev);
+ struct tm1628 *s = led->ctrl;
+ int offset = led->grid - 1;
+ __le16 bit = cpu_to_le16(BIT(led->seg - 1));
+ bool on;
+
+ mutex_lock(&s->disp_lock);
+ on = s->data[offset] & bit;
+ mutex_unlock(&s->disp_lock);
+
+ return on ? LED_ON : LED_OFF;
+}
+
+static int tm1628_register_led(struct tm1628 *s, struct fwnode_handle *node,
+ u32 grid, u32 seg, struct tm1628_led *led)
+{
+ struct device *dev = &s->spi->dev;
+ struct led_init_data init_data = { .fwnode = node };
+
+ led->ctrl = s;
+ led->grid = grid;
+ led->seg = seg;
+ led->leddev.max_brightness = LED_ON;
+ led->leddev.brightness_set_blocking = tm1628_led_set_brightness;
+ led->leddev.brightness_get = tm1628_led_get_brightness;
+
+ return devm_led_classdev_register_ext(dev, &led->leddev, &init_data);
+}
+
+static ssize_t display_text_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct tm1628 *s = dev_get_drvdata(dev);
+
+ return sysfs_emit(buf, "%s\n", s->text);
+}
+
+static ssize_t display_text_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct tm1628 *s = dev_get_drvdata(dev);
+ int ret, i;
+
+ for (i = 0; i < count && i < s->grid_size && isprint(buf[i]); i++)
+ s->text[i] = buf[i];
+
+ s->text[i] = '\0';
+
+ ret = tm1628_show_text(s);
+ if (ret < 0)
+ return ret;
+
+ return count;
+}
+
+static const DEVICE_ATTR_RW(display_text);
+
+static int tm1628_spi_probe(struct spi_device *spi)
+{
+ struct fwnode_handle *child;
+ unsigned int num_leds;
+ struct tm1628 *s;
+ int ret, i;
+
+ num_leds = device_get_child_node_count(&spi->dev);
+
+ s = devm_kzalloc(&spi->dev, struct_size(s, leds, num_leds), GFP_KERNEL);
+ if (!s)
+ return -ENOMEM;
+
+ s->spi = spi;
+ spi_set_drvdata(spi, s);
+
+ mutex_init(&s->disp_lock);
+
+ /* According to TM1628 datasheet */
+ msleep(200);
+
+ /* Clear screen */
+ ret = tm1628_write_data(spi, 0, MAX_GRID_SIZE);
+ if (ret)
+ return ret;
+
+ /* For now we support 6x12 mode only. This should be sufficient for most use cases */
+ ret = tm1628_set_display_mode(spi, TM1628_DISPLAY_MODE_6_12);
+ if (ret)
+ return ret;
+
+ ret = tm1628_set_display_ctrl(spi, true);
+ if (ret)
+ return ret;
+
+ num_leds = 0;
+
+ if (!IS_REACHABLE(CONFIG_LEDS_CLASS))
+ goto no_leds;
+
+ device_for_each_child_node(&spi->dev, child) {
+ u32 reg[2];
+
+ ret = fwnode_property_read_u32_array(child, "reg", reg, 2);
+ if (ret) {
+ dev_err(&spi->dev, "Reading %s reg property failed (%d)\n",
+ fwnode_get_name(child), ret);
+ continue;
+ }
+
+ if (reg[0] == 0 || reg[0] > MAX_GRID_SIZE) {
+ dev_err(&spi->dev, "Invalid grid %u at %s\n",
+ reg[0], fwnode_get_name(child));
+ continue;
+ }
+
+ if (reg[1] == 0 || reg[1] > MAX_SEGMENT_NUM) {
+ dev_err(&spi->dev, "Invalid segment %u at %s\n",
+ reg[1], fwnode_get_name(child));
+ continue;
+ }
+
+ ret = tm1628_register_led(s, child, reg[0], reg[1], s->leds + num_leds);
+ if (ret) {
+ dev_err(&spi->dev, "Failed to register LED %s (%d)\n",
+ fwnode_get_name(child), ret);
+ continue;
+ }
+ num_leds++;
+ }
+
+no_leds:
+ ret = device_property_count_u8(&spi->dev, "titanmec,grid");
+ if (ret < 1 || ret > MAX_GRID_SIZE) {
+ dev_err(&spi->dev, "Invalid display length (%d)\n", ret);
+ return -EINVAL;
+ }
+
+ s->grid_size = ret;
+
+ ret = device_property_read_u8_array(&spi->dev, "titanmec,grid", s->grid, s->grid_size);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < s->grid_size; i++) {
+ if (s->grid[i] < 1 || s->grid[i] > s->grid_size)
+ return -EINVAL;
+ }
+
+ ret = device_property_read_u8_array(&spi->dev, "titanmec,segment-mapping",
+ s->segment_mapping, NUM_LED_SEGS);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < NUM_LED_SEGS; i++) {
+ if (s->segment_mapping[i] < 1 || s->segment_mapping[i] > MAX_SEGMENT_NUM)
+ return -EINVAL;
+ }
+
+ ret = device_create_file(&spi->dev, &dev_attr_display_text);
+ if (ret)
+ return ret;
+
+ dev_info(&spi->dev, "Configured display with %u digits and %u symbols\n",
+ s->grid_size, num_leds);
+
+ return 0;
+}
+
+static void tm1628_spi_remove(struct spi_device *spi)
+{
+ device_remove_file(&spi->dev, &dev_attr_display_text);
+ tm1628_set_display_ctrl(spi, false);
+}
+
+static void tm1628_spi_shutdown(struct spi_device *spi)
+{
+ tm1628_set_display_ctrl(spi, false);
+}
+
+static const struct of_device_id tm1628_spi_of_matches[] = {
+ { .compatible = "titanmec,tm1628" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, tm1628_spi_of_matches);
+
+static const struct spi_device_id tm1628_spi_id_table[] = {
+ { "tm1628" },
+ {},
+};
+MODULE_DEVICE_TABLE(spi, tm1628_spi_id_table);
+
+static struct spi_driver tm1628_spi_driver = {
+ .probe = tm1628_spi_probe,
+ .remove = tm1628_spi_remove,
+ .shutdown = tm1628_spi_shutdown,
+ .id_table = tm1628_spi_id_table,
+
+ .driver = {
+ .name = "tm1628",
+ .of_match_table = tm1628_spi_of_matches,
+ },
+};
+module_spi_driver(tm1628_spi_driver);
+
+MODULE_DESCRIPTION("TM1628 LED controller driver");
+MODULE_AUTHOR("Andreas Färber <afaerber@suse.de>");
+MODULE_AUTHOR("Heiner Kallweit <hkallweit1@gmail.com>");
+MODULE_LICENSE("GPL");
--
2.34.1

View File

@ -0,0 +1,41 @@
From 2411a183fc6f2806727cf9dcfe62dcd5e1199ce9 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sat, 3 May 2025 15:18:07 +0000
Subject: [PATCH 17/37] FROMLIST(v1): arm64: dts: amlogic: sm1-bananapi: lower
SD card speed for stability
Users report being able to boot (u-boot) from SD card but kernel
init then fails to mount partitions on the card containing boot
media resulting in first-boot failure. System logs show only the
probe of the mmc devices: the SD card is seen, but no partitions
are found so init fails to mount them and boot stalls.
Reducing the speed of the SD card from 50MHz to 35MHz results in
complete probing of the card and successful boot.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
index 538b35036954..5e07f0f9538e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
@@ -380,11 +380,10 @@ &sd_emmc_b {
bus-width = <4>;
cap-sd-highspeed;
- max-frequency = <50000000>;
+ /* Boot failures are observed at 50MHz */
+ max-frequency = <35000000>;
disable-wp;
- /* TOFIX: SD card is barely usable in SDR modes */
-
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&vddio_c>;
--
2.34.1

View File

@ -1,93 +0,0 @@
From 8dd34cfc3fdb2ae31c34492b8b25bdf7d8c3352b Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Mon, 4 Apr 2022 18:52:34 +0000
Subject: [PATCH 17/53] FROMLIST(v5): arm64: dts: meson-gxl-s905w-tx3-mini: add
support for the 7 segment display
This patch adds support for the 7 segment display of the device.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
.../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
index 6705c2082a78..ae0d8d7b1e19 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
@@ -10,6 +10,7 @@
#include "meson-gxl-s905x.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/leds/common.h>
/ {
compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl";
@@ -19,6 +20,64 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */
};
+
+ spi {
+ compatible = "spi-gpio";
+ sck-gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tm1628: led-controller@0 {
+ compatible = "titanmec,tm1628";
+ reg = <0>;
+ spi-3wire;
+ spi-lsb-first;
+ spi-rx-delay-us = <1>;
+ spi-max-frequency = <500000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ titanmec,segment-mapping = /bits/ 8 <4 5 6 1 2 3 7>;
+ titanmec,grid = /bits/ 8 <4 3 2 1>;
+
+ alarm@5,1 {
+ reg = <5 1>;
+ function = LED_FUNCTION_ALARM;
+ };
+
+ usb@5,2 {
+ reg = <5 2>;
+ function = LED_FUNCTION_USB;
+ };
+ play@5,3 {
+ reg = <5 3>;
+ function = "play";
+ };
+
+ pause@5,4 {
+ reg = <5 4>;
+ function = "pause";
+ };
+
+ colon@5,5 {
+ reg = <5 5>;
+ function = "colon";
+ };
+
+ lan@5,6 {
+ reg = <5 6>;
+ function = LED_FUNCTION_LAN;
+ };
+
+ wlan@5,7 {
+ reg = <5 7>;
+ function = LED_FUNCTION_WLAN;
+ };
+ };
+ };
};
&ir {
--
2.34.1

View File

@ -1,32 +0,0 @@
From 3a59c995a56b3802ceb6db413c81e2170fa767cb Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Mon, 4 Apr 2022 18:53:32 +0000
Subject: [PATCH 18/53] FROMLIST(v5): MAINTAINERS: Add entry for tm1628
auxdisplay driver
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1aabf1c15bb3..ea6d2ff2eb20 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22155,6 +22155,13 @@ W: http://sourceforge.net/projects/tlan/
F: Documentation/networking/device_drivers/ethernet/ti/tlan.rst
F: drivers/net/ethernet/ti/tlan.*
+TM1628 LED CONTROLLER DRIVER
+M: Heiner Kallweit <hkallweit1@gmail.com>
+S: Maintained
+F: Documentation/devicetree/bindings/auxdisplay/titanmec,tm1628.yaml
+F: Documentation/ABI/testing/sysfs-devices-auxdisplay-tm1628
+F: drivers/auxdisplay/tm1628.c
+
TMIO/SDHI MMC DRIVER
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
L: linux-mmc@vger.kernel.org
--
2.34.1

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@ -0,0 +1,50 @@
From a1f197da3061f0ccf210e7b69c478e31377196c4 Mon Sep 17 00:00:00 2001
From: Andreas Baierl <ichgeh@imkreisrum.de>
Date: Tue, 2 Apr 2024 14:22:52 +0000
Subject: [PATCH 18/37] WIP: media: meson: vdec: reintroduce wiggle room
Without the wiggle room, it happens that matching offsets can't be found.
This results in non-matches and afterwards in frame drops in userspace apps.
Reintroduce this wiggle room again.
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
---
drivers/staging/media/meson/vdec/vdec_helpers.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
index fef76142f0c5..fbfdbf3ec19d 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.c
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
@@ -378,7 +378,16 @@ void amvdec_dst_buf_done_offset(struct amvdec_session *sess,
/* Look for our vififo offset to get the corresponding timestamp. */
list_for_each_entry_safe(tmp, n, &sess->timestamps, list) {
- if (tmp->offset > offset) {
+ s64 delta = (s64)offset - tmp->offset;
+
+ /* Offsets reported by codecs usually differ slightly,
+ * so we need some wiggle room.
+ * 4KiB being the minimum packet size, there is no risk here.
+ */
+ if (delta > (-1 * (s32)SZ_4K) && delta < SZ_4K) {
+ match = tmp;
+ break;
+ } else {
/*
* Delete any record that remained unused for 32 match
* checks
@@ -387,10 +396,7 @@ void amvdec_dst_buf_done_offset(struct amvdec_session *sess,
list_del(&tmp->list);
kfree(tmp);
}
- break;
}
-
- match = tmp;
}
if (!match) {
--
2.34.1

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@ -1,203 +0,0 @@
From 665584f98081e481e77286b49b6a0e1ce9fe5655 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 23 Dec 2018 02:24:38 +0100
Subject: [PATCH 19/53] FROMLIST(v1): ASoC: hdmi-codec: reorder channel
allocation list
Wrong channel allocation is selected by hdmi_codec_get_ch_alloc_table_idx().
E.g when ELD reports FL|FR|LFE|FC|RL|RR or FL|FR|LFE|FC|RL|RR|RC|RLC|RRC
ca_id 0x01 with speaker mask FL|FR|LFE gets selected instead of
ca_id 0x03 with speaker mask FL|FR|LFE|FC for 4 channels
and
ca_id 0x04 with speaker mask FL|FR|RC gets selected instead of
ca_id 0x0b with speaker mask FL|FR|LFE|FC|RL|RR for 6 channels
Fix this by reorder the channel allocation list with
most specific speaker mask at the top.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
sound/soc/codecs/hdmi-codec.c | 140 +++++++++++++++++++---------------
1 file changed, 77 insertions(+), 63 deletions(-)
diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
index e06b28c7e5ba..6ebbd4bfa47e 100644
--- a/sound/soc/codecs/hdmi-codec.c
+++ b/sound/soc/codecs/hdmi-codec.c
@@ -185,84 +185,97 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
/*
* hdmi_codec_channel_alloc: speaker configuration available for CEA
*
- * This is an ordered list that must match with hdmi_codec_8ch_chmaps struct
+ * This is an ordered list where ca_id must exist in hdmi_codec_8ch_chmaps
* The preceding ones have better chances to be selected by
* hdmi_codec_get_ch_alloc_table_idx().
*/
static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
{ .ca_id = 0x00, .n_ch = 2,
- .mask = FL | FR},
- /* 2.1 */
- { .ca_id = 0x01, .n_ch = 4,
- .mask = FL | FR | LFE},
- /* Dolby Surround */
+ .mask = FL | FR },
+ { .ca_id = 0x03, .n_ch = 4,
+ .mask = FL | FR | LFE | FC },
{ .ca_id = 0x02, .n_ch = 4,
.mask = FL | FR | FC },
- /* surround51 */
+ { .ca_id = 0x01, .n_ch = 4,
+ .mask = FL | FR | LFE },
{ .ca_id = 0x0b, .n_ch = 6,
- .mask = FL | FR | LFE | FC | RL | RR},
- /* surround40 */
- { .ca_id = 0x08, .n_ch = 6,
- .mask = FL | FR | RL | RR },
- /* surround41 */
- { .ca_id = 0x09, .n_ch = 6,
- .mask = FL | FR | LFE | RL | RR },
- /* surround50 */
+ .mask = FL | FR | LFE | FC | RL | RR },
{ .ca_id = 0x0a, .n_ch = 6,
.mask = FL | FR | FC | RL | RR },
- /* 6.1 */
- { .ca_id = 0x0f, .n_ch = 8,
- .mask = FL | FR | LFE | FC | RL | RR | RC },
- /* surround71 */
+ { .ca_id = 0x09, .n_ch = 6,
+ .mask = FL | FR | LFE | RL | RR },
+ { .ca_id = 0x08, .n_ch = 6,
+ .mask = FL | FR | RL | RR },
+ { .ca_id = 0x07, .n_ch = 6,
+ .mask = FL | FR | LFE | FC | RC },
+ { .ca_id = 0x06, .n_ch = 6,
+ .mask = FL | FR | FC | RC },
+ { .ca_id = 0x05, .n_ch = 6,
+ .mask = FL | FR | LFE | RC },
+ { .ca_id = 0x04, .n_ch = 6,
+ .mask = FL | FR | RC },
{ .ca_id = 0x13, .n_ch = 8,
.mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
- /* others */
- { .ca_id = 0x03, .n_ch = 8,
- .mask = FL | FR | LFE | FC },
- { .ca_id = 0x04, .n_ch = 8,
- .mask = FL | FR | RC},
- { .ca_id = 0x05, .n_ch = 8,
- .mask = FL | FR | LFE | RC },
- { .ca_id = 0x06, .n_ch = 8,
- .mask = FL | FR | FC | RC },
- { .ca_id = 0x07, .n_ch = 8,
- .mask = FL | FR | LFE | FC | RC },
- { .ca_id = 0x0c, .n_ch = 8,
- .mask = FL | FR | RC | RL | RR },
- { .ca_id = 0x0d, .n_ch = 8,
- .mask = FL | FR | LFE | RL | RR | RC },
- { .ca_id = 0x0e, .n_ch = 8,
- .mask = FL | FR | FC | RL | RR | RC },
- { .ca_id = 0x10, .n_ch = 8,
- .mask = FL | FR | RL | RR | RLC | RRC },
- { .ca_id = 0x11, .n_ch = 8,
- .mask = FL | FR | LFE | RL | RR | RLC | RRC },
+ { .ca_id = 0x1f, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
{ .ca_id = 0x12, .n_ch = 8,
.mask = FL | FR | FC | RL | RR | RLC | RRC },
- { .ca_id = 0x14, .n_ch = 8,
- .mask = FL | FR | FLC | FRC },
- { .ca_id = 0x15, .n_ch = 8,
- .mask = FL | FR | LFE | FLC | FRC },
- { .ca_id = 0x16, .n_ch = 8,
- .mask = FL | FR | FC | FLC | FRC },
- { .ca_id = 0x17, .n_ch = 8,
- .mask = FL | FR | LFE | FC | FLC | FRC },
- { .ca_id = 0x18, .n_ch = 8,
- .mask = FL | FR | RC | FLC | FRC },
- { .ca_id = 0x19, .n_ch = 8,
- .mask = FL | FR | LFE | RC | FLC | FRC },
- { .ca_id = 0x1a, .n_ch = 8,
- .mask = FL | FR | RC | FC | FLC | FRC },
- { .ca_id = 0x1b, .n_ch = 8,
- .mask = FL | FR | LFE | RC | FC | FLC | FRC },
- { .ca_id = 0x1c, .n_ch = 8,
- .mask = FL | FR | RL | RR | FLC | FRC },
- { .ca_id = 0x1d, .n_ch = 8,
- .mask = FL | FR | LFE | RL | RR | FLC | FRC },
{ .ca_id = 0x1e, .n_ch = 8,
.mask = FL | FR | FC | RL | RR | FLC | FRC },
- { .ca_id = 0x1f, .n_ch = 8,
- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
+ { .ca_id = 0x11, .n_ch = 8,
+ .mask = FL | FR | LFE | RL | RR | RLC | RRC },
+ { .ca_id = 0x1d, .n_ch = 8,
+ .mask = FL | FR | LFE | RL | RR | FLC | FRC },
+ { .ca_id = 0x10, .n_ch = 8,
+ .mask = FL | FR | RL | RR | RLC | RRC },
+ { .ca_id = 0x1c, .n_ch = 8,
+ .mask = FL | FR | RL | RR | FLC | FRC },
+ { .ca_id = 0x0f, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | RL | RR | RC },
+ { .ca_id = 0x1b, .n_ch = 8,
+ .mask = FL | FR | LFE | RC | FC | FLC | FRC },
+ { .ca_id = 0x0e, .n_ch = 8,
+ .mask = FL | FR | FC | RL | RR | RC },
+ { .ca_id = 0x1a, .n_ch = 8,
+ .mask = FL | FR | RC | FC | FLC | FRC },
+ { .ca_id = 0x0d, .n_ch = 8,
+ .mask = FL | FR | LFE | RL | RR | RC },
+ { .ca_id = 0x19, .n_ch = 8,
+ .mask = FL | FR | LFE | RC | FLC | FRC },
+ { .ca_id = 0x0c, .n_ch = 8,
+ .mask = FL | FR | RC | RL | RR },
+ { .ca_id = 0x18, .n_ch = 8,
+ .mask = FL | FR | RC | FLC | FRC },
+ { .ca_id = 0x17, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | FLC | FRC },
+ { .ca_id = 0x16, .n_ch = 8,
+ .mask = FL | FR | FC | FLC | FRC },
+ { .ca_id = 0x15, .n_ch = 8,
+ .mask = FL | FR | LFE | FLC | FRC },
+ { .ca_id = 0x14, .n_ch = 8,
+ .mask = FL | FR | FLC | FRC },
+ { .ca_id = 0x0b, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | RL | RR },
+ { .ca_id = 0x0a, .n_ch = 8,
+ .mask = FL | FR | FC | RL | RR },
+ { .ca_id = 0x09, .n_ch = 8,
+ .mask = FL | FR | LFE | RL | RR },
+ { .ca_id = 0x08, .n_ch = 8,
+ .mask = FL | FR | RL | RR },
+ { .ca_id = 0x07, .n_ch = 8,
+ .mask = FL | FR | LFE | FC | RC },
+ { .ca_id = 0x06, .n_ch = 8,
+ .mask = FL | FR | FC | RC },
+ { .ca_id = 0x05, .n_ch = 8,
+ .mask = FL | FR | LFE | RC },
+ { .ca_id = 0x04, .n_ch = 8,
+ .mask = FL | FR | RC },
+ { .ca_id = 0x03, .n_ch = 8,
+ .mask = FL | FR | LFE | FC },
+ { .ca_id = 0x02, .n_ch = 8,
+ .mask = FL | FR | FC },
+ { .ca_id = 0x01, .n_ch = 8,
+ .mask = FL | FR | LFE },
};
struct hdmi_codec_priv {
@@ -371,7 +384,8 @@ static int hdmi_codec_chmap_ctl_get(struct snd_kcontrol *kcontrol,
struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
struct hdmi_codec_priv *hcp = info->private_data;
- map = info->chmap[hcp->chmap_idx].map;
+ if (hcp->chmap_idx != HDMI_CODEC_CHMAP_IDX_UNKNOWN)
+ map = info->chmap[hcp->chmap_idx].map;
for (i = 0; i < info->max_channels; i++) {
if (hcp->chmap_idx == HDMI_CODEC_CHMAP_IDX_UNKNOWN)
--
2.34.1

View File

@ -0,0 +1,28 @@
From e0ebd51471f1153d3d1dc53b9a645fde537b1411 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Tue, 14 Mar 2023 01:13:15 +0000
Subject: [PATCH 19/37] WIP: media: meson: vdec: fix memory leak of 'new_frame'
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Link: https://lore.kernel.org/r/202303120441.YFGHDOya-lkp@intel.com/
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
drivers/staging/media/meson/vdec/codec_hevc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
index fcaaa1ad50b8..b0d8623c3c7d 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc.c
+++ b/drivers/staging/media/meson/vdec/codec_hevc.c
@@ -731,6 +731,7 @@ codec_hevc_prepare_new_frame(struct amvdec_session *sess)
vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
if (!vbuf) {
dev_err(sess->core->dev, "No dst buffer available\n");
+ kfree(new_frame);
return NULL;
}
--
2.34.1

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@ -0,0 +1,235 @@
From 32d8e8ef41de29cfede75a4eed0f33fa4d326057 Mon Sep 17 00:00:00 2001
From: Andreas Baierl <ichgeh@imkreisrum.de>
Date: Thu, 20 Feb 2025 23:59:14 +0000
Subject: [PATCH 20/37] WIP: media: meson: vdec: fix
V4L2_BUF_FLAG_{KEY|P|B}FRAME
ffmpeg needs the keyframe flag to be set correctly, else
AV_FRAME_FLAG_* can not be set. Fix that (only h264 atm).
Register values and bits were obtained from the vendor
4.9 kernel source [0].
[0] https://github.com/hardkernel/linux/tree/odroidg12-4.9.y/drivers/amlogic/media_modules/frame_provider/decoder/h264
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
---
drivers/staging/media/meson/vdec/codec_h264.c | 19 +++++++++++++-
drivers/staging/media/meson/vdec/codec_hevc.c | 4 +--
.../staging/media/meson/vdec/codec_mpeg12.c | 2 +-
drivers/staging/media/meson/vdec/codec_vp9.c | 4 +--
.../staging/media/meson/vdec/vdec_helpers.c | 25 +++++++++++++------
.../staging/media/meson/vdec/vdec_helpers.h | 6 ++---
6 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
index d53c9a464bde..4edb4021c244 100644
--- a/drivers/staging/media/meson/vdec/codec_h264.c
+++ b/drivers/staging/media/meson/vdec/codec_h264.c
@@ -35,6 +35,11 @@
#define PIC_TOP_BOT 5
#define PIC_BOT_TOP 6
+/* Slice type */
+#define SLICE_TYPE_I 2
+#define SLICE_TYPE_P 5
+#define SLICE_TYPE_B 6
+
/* Size of Motion Vector per macroblock */
#define MB_MV_SIZE 96
@@ -393,8 +398,11 @@ static void codec_h264_frames_ready(struct amvdec_session *sess, u32 status)
u32 buffer_index = frame_status & BUF_IDX_MASK;
u32 pic_struct = (frame_status >> PIC_STRUCT_BIT) &
PIC_STRUCT_MASK;
+ u32 idr_flag = (frame_status & 0x400);
u32 offset = (frame_status >> OFFSET_BIT) & OFFSET_MASK;
u32 field = V4L2_FIELD_NONE;
+ u32 slice_type = (amvdec_read_dos(core, AV_SCRATCH_H) >> (i * 4)) & 0xf;
+ u32 type = 0;
/*
* A buffer decode error means it was decoded,
@@ -410,8 +418,17 @@ static void codec_h264_frames_ready(struct amvdec_session *sess, u32 status)
else if (pic_struct == PIC_BOT_TOP)
field = V4L2_FIELD_INTERLACED_BT;
+ if (idr_flag)
+ type = 4;
+ else if (slice_type == SLICE_TYPE_I)
+ type = 1;
+ else if (slice_type == SLICE_TYPE_P)
+ type = 2;
+ else if (slice_type == SLICE_TYPE_B || slice_type == 8)
+ type = 3;
+
offset |= get_offset_msb(core, i);
- amvdec_dst_buf_done_idx(sess, buffer_index, offset, field);
+ amvdec_dst_buf_done_idx(sess, buffer_index, offset, field, type);
}
}
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
index b0d8623c3c7d..fe439770637c 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc.c
+++ b/drivers/staging/media/meson/vdec/codec_hevc.c
@@ -499,7 +499,7 @@ static void codec_hevc_show_frames(struct amvdec_session *sess)
dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n",
tmp->poc, tmp->vbuf->vb2_buf.index);
amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset,
- V4L2_FIELD_NONE, false);
+ V4L2_FIELD_NONE, 0, false);
tmp->show = 0;
hevc->frames_num--;
@@ -667,7 +667,7 @@ static void codec_hevc_flush_output(struct amvdec_session *sess)
struct hevc_frame *tmp, *n;
while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
- amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE);
+ amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE, 0);
tmp->show = 0;
hevc->frames_num--;
}
diff --git a/drivers/staging/media/meson/vdec/codec_mpeg12.c b/drivers/staging/media/meson/vdec/codec_mpeg12.c
index 48869cc3d973..05c52766fe52 100644
--- a/drivers/staging/media/meson/vdec/codec_mpeg12.c
+++ b/drivers/staging/media/meson/vdec/codec_mpeg12.c
@@ -187,7 +187,7 @@ static irqreturn_t codec_mpeg12_threaded_isr(struct amvdec_session *sess)
codec_mpeg12_update_dar(sess);
buffer_index = ((reg & 0xf) - 1) & 7;
offset = amvdec_read_dos(core, MREG_FRAME_OFFSET);
- amvdec_dst_buf_done_idx(sess, buffer_index, offset, field);
+ amvdec_dst_buf_done_idx(sess, buffer_index, offset, field, 0);
end:
amvdec_write_dos(core, MREG_BUFFEROUT, 0);
diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
index 8e3bbf0db4b3..1b1f1797110a 100644
--- a/drivers/staging/media/meson/vdec/codec_vp9.c
+++ b/drivers/staging/media/meson/vdec/codec_vp9.c
@@ -665,7 +665,7 @@ static void codec_vp9_flush_output(struct amvdec_session *sess)
if (!tmp->done) {
if (tmp->show)
amvdec_dst_buf_done(sess, tmp->vbuf,
- V4L2_FIELD_NONE);
+ V4L2_FIELD_NONE, 0);
else
v4l2_m2m_buf_queue(sess->m2m_ctx, tmp->vbuf);
@@ -1427,7 +1427,7 @@ static void codec_vp9_show_frame(struct amvdec_session *sess)
if (!tmp->done) {
pr_debug("Doning %u\n", tmp->index);
- amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE);
+ amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE, 0);
tmp->done = 1;
vp9->frames_num--;
}
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
index fbfdbf3ec19d..9a61dabd8ce9 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.c
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
@@ -280,7 +280,7 @@ EXPORT_SYMBOL_GPL(amvdec_remove_ts);
static void dst_buf_done(struct amvdec_session *sess,
struct vb2_v4l2_buffer *vbuf,
- u32 field, u64 timestamp,
+ u32 field, u32 type, u64 timestamp,
struct v4l2_timecode timecode, u32 flags)
{
struct device *dev = sess->core->dev_dec;
@@ -303,6 +303,15 @@ static void dst_buf_done(struct amvdec_session *sess,
vbuf->flags = flags;
vbuf->timecode = timecode;
+ if (type == 1)
+ vbuf->flags |= V4L2_BUF_FLAG_KEYFRAME;
+ else if (type == 2)
+ vbuf->flags |= V4L2_BUF_FLAG_PFRAME;
+ else if (type == 3)
+ vbuf->flags |= V4L2_BUF_FLAG_BFRAME;
+ else if (type == 4)
+ vbuf->flags |= V4L2_BUF_FLAG_KEYFRAME;
+
if (sess->should_stop &&
atomic_read(&sess->esparser_queued_bufs) <= 1) {
const struct v4l2_event ev = { .type = V4L2_EVENT_EOS };
@@ -329,7 +338,7 @@ static void dst_buf_done(struct amvdec_session *sess,
}
void amvdec_dst_buf_done(struct amvdec_session *sess,
- struct vb2_v4l2_buffer *vbuf, u32 field)
+ struct vb2_v4l2_buffer *vbuf, u32 field, u32 type)
{
struct device *dev = sess->core->dev_dec;
struct amvdec_timestamp *tmp;
@@ -357,14 +366,14 @@ void amvdec_dst_buf_done(struct amvdec_session *sess,
kfree(tmp);
spin_unlock_irqrestore(&sess->ts_spinlock, flags);
- dst_buf_done(sess, vbuf, field, timestamp, timecode, vbuf_flags);
+ dst_buf_done(sess, vbuf, field, type, timestamp, timecode, vbuf_flags);
atomic_dec(&sess->esparser_queued_bufs);
}
EXPORT_SYMBOL_GPL(amvdec_dst_buf_done);
void amvdec_dst_buf_done_offset(struct amvdec_session *sess,
struct vb2_v4l2_buffer *vbuf,
- u32 offset, u32 field, bool allow_drop)
+ u32 offset, u32 field, u32 type, bool allow_drop)
{
struct device *dev = sess->core->dev_dec;
struct amvdec_timestamp *match = NULL;
@@ -411,14 +420,14 @@ void amvdec_dst_buf_done_offset(struct amvdec_session *sess,
}
spin_unlock_irqrestore(&sess->ts_spinlock, flags);
- dst_buf_done(sess, vbuf, field, timestamp, timecode, vbuf_flags);
+ dst_buf_done(sess, vbuf, field, type, timestamp, timecode, vbuf_flags);
if (match)
atomic_dec(&sess->esparser_queued_bufs);
}
EXPORT_SYMBOL_GPL(amvdec_dst_buf_done_offset);
void amvdec_dst_buf_done_idx(struct amvdec_session *sess,
- u32 buf_idx, u32 offset, u32 field)
+ u32 buf_idx, u32 offset, u32 field, u32 type)
{
struct vb2_v4l2_buffer *vbuf;
struct device *dev = sess->core->dev_dec;
@@ -434,9 +443,9 @@ void amvdec_dst_buf_done_idx(struct amvdec_session *sess,
}
if (offset != -1)
- amvdec_dst_buf_done_offset(sess, vbuf, offset, field, true);
+ amvdec_dst_buf_done_offset(sess, vbuf, offset, field, type, true);
else
- amvdec_dst_buf_done(sess, vbuf, field);
+ amvdec_dst_buf_done(sess, vbuf, field, type);
}
EXPORT_SYMBOL_GPL(amvdec_dst_buf_done_idx);
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
index 1a711679d26a..e30edb935e37 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.h
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
@@ -41,12 +41,12 @@ u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
* @field: V4L2 interlaced field
*/
void amvdec_dst_buf_done_idx(struct amvdec_session *sess, u32 buf_idx,
- u32 offset, u32 field);
+ u32 offset, u32 field, u32 type);
void amvdec_dst_buf_done(struct amvdec_session *sess,
- struct vb2_v4l2_buffer *vbuf, u32 field);
+ struct vb2_v4l2_buffer *vbuf, u32 field, u32 type);
void amvdec_dst_buf_done_offset(struct amvdec_session *sess,
struct vb2_v4l2_buffer *vbuf,
- u32 offset, u32 field, bool allow_drop);
+ u32 offset, u32 field, u32 type, bool allow_drop);
/**
* amvdec_add_ts() - Add a timestamp to the list
--
2.34.1

View File

@ -0,0 +1,949 @@
From 2efb62e0eaeeb3d2c84b7d12c94a5ba99c257b06 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sun, 26 May 2024 12:53:07 +0000
Subject: [PATCH 21/37] WIP: arm64: dts: meson: add Odroid-C2 HiFi-Shield
boards
Add experimental device-tree files for Odroid C2 with HiFi-Shield+ (pcm5102a)
and HiFi-Shield2 (pcm5242) mezzanine boards.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 4 +
.../meson-gxbb-odroidc2-hifishield.dts | 446 +++++++++++++++++
.../meson-gxbb-odroidc2-hifishield2.dts | 458 ++++++++++++++++++
3 files changed, 908 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 15e7901c1268..b593736ff60b 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -102,3 +102,7 @@ meson-g12a-fbx8am-brcm-dtbs := meson-g12a-fbx8am.dtb meson-g12a-fbx8am-brcm.dtbo
meson-g12a-fbx8am-realtek-dtbs := meson-g12a-fbx8am.dtb meson-g12a-fbx8am-realtek.dtbo
meson-g12b-a311d-khadas-vim3-ts050-dtbs := meson-g12b-a311d-khadas-vim3.dtb meson-khadas-vim3-ts050.dtbo
meson-sm1-khadas-vim3l-ts050-dtbs := meson-sm1-khadas-vim3l.dtb meson-khadas-vim3-ts050.dtbo
+
+# Experimental
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2-hifishield.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2-hifishield2.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts
new file mode 100644
index 000000000000..80b44c2abac2
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield.dts
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
+ model = "Hardkernel ODROID-C2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = &ethmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ usb_otg_pwr: regulator-usb-pwrs {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB_OTG_PWR";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ /*
+ * signal name from schematics: PWREN
+ */
+ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * signal name from schematics: USB_POWER
+ */
+ vin-supply = <&p5v0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led-blue {
+ label = "c2:blue:alive";
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ p5v0: regulator-p5v0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "P5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ hdmi_p5v0: regulator-hdmi-p5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "HDMI_P5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ /* AP2331SA-7 */
+ vin-supply = <&p5v0>;
+ };
+
+ tflash_vdd: regulator-tflash-vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ /*
+ * signal name from schematics: TFLASH_VDD_EN
+ */
+ gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /* U16 RT9179GB */
+ vin-supply = <&vddio_ao3v3>;
+ };
+
+ tf_io: gpio-regulator-tf-io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ /*
+ * signal name from schematics: TF_3V3N_1V8_EN
+ */
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ /* U12/U13 RT9179GB */
+ vin-supply = <&vddio_ao3v3>;
+ };
+
+ vcc1v8: regulator-vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ /* U18 RT9179GB */
+ vin-supply = <&vddio_ao3v3>;
+ };
+
+ vcc3v3: regulator-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao1v8: regulator-vddio-ao1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ /* U17 RT9179GB */
+ vin-supply = <&p5v0>;
+ };
+
+ vddio_ao3v3: regulator-vddio-ao3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ /* U11 MP2161GJ-C499 */
+ vin-supply = <&p5v0>;
+ };
+
+ ddr3_1v5: regulator-ddr3-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR3_1V5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ /* U15 MP2161GJ-C499 */
+ vin-supply = <&p5v0>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "ODROID-C2";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_ao_6_pins &i2s_am_clk_pins &i2s_out_ao_clk_pins &i2s_out_lr_clk_pins &i2s_out_ch01_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc {
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+};
+
+&ethmac {
+ status = "okay";
+ pinctrl-0 = <&eth_rgmii_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&eth_phy0>;
+ phy-mode = "rgmii";
+
+ amlogic,tx-delay-ns = <2>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_p5v0>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&i2c_A {
+ status = "okay";
+ pinctrl-0 = <&i2c_a_pins>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcm5102a: pcm5102a@4c {
+ compatible = "ti,pcm5102a";
+ reg = <0x4c>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+ linux,rc-map-name = "rc-odroid";
+};
+
+&gpio_ao {
+ gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
+ "USB HUB nRESET", "USB OTG Power En",
+ "SPDIF_OUTPUT", "IR In", "I2S_MCLK",
+ "I2S_SCLK", "I2S_LRCLK", "I2S_DATA_OUTPUT",
+ "HDMI CEC", "SYS LED",
+ /* GPIO_TEST_N */
+ "";
+};
+
+&gpio {
+ gpio-line-names = /* Bank GPIOZ */
+ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
+ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
+ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
+ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
+ "Eth PHY nRESET", "Eth PHY Intc",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
+ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
+ "eMMC Reset", "eMMC CMD",
+ "", "", "", "", "", "", "",
+ /* Bank CARD */
+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+ "SDCard D3", "SDCard D2", "SDCard Det",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "",
+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
+ "PWM D", "PWM B",
+ /* Bank GPIOY */
+ "Revision Bit0", "Revision Bit1", "",
+ "J2 Header Pin35", "", "", "", "J2 Header Pin36",
+ "J2 Header Pin31", "", "", "", "TF VDD En",
+ "J2 Header Pin32", "J2 Header Pin26", "", "",
+ /* Bank GPIOX */
+ "J2 Header Pin29", "J2 Header Pin24",
+ "J2 Header Pin23", "J2 Header Pin22",
+ "J2 Header Pin21", "J2 Header Pin18",
+ "J2 Header Pin33", "J2 Header Pin19",
+ "J2 Header Pin16", "J2 Header Pin15",
+ "J2 Header Pin12", "J2 Header Pin13",
+ "J2 Header Pin8", "J2 Header Pin10",
+ "", "", "", "", "",
+ "J2 Header Pin11", "", "J2 Header Pin7", "",
+ /* Bank GPIOCLK */
+ "", "", "", "";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc1v8>;
+};
+
+&scpi_clocks {
+ status = "disabled";
+};
+
+/* SD */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc3v3>;
+ vqmmc-supply = <&vcc1v8>;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "disabled";
+ phy-supply = <&usb_otg_pwr>;
+};
+
+&usb1_phy {
+ status = "okay";
+ phy-supply = <&usb_otg_pwr>;
+};
+
+&usb0 {
+ status = "disabled";
+};
+
+&usb1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub@1 {
+ /* Genesys Logic GL852G USB 2.0 hub */
+ compatible = "usb5e3,610";
+ reg = <1>;
+ vdd-supply = <&p5v0>;
+ reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts
new file mode 100644
index 000000000000..e94d6dc75fec
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2-hifishield2.dts
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
+ model = "Hardkernel ODROID-C2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = &ethmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ usb_otg_pwr: regulator-usb-pwrs {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB_OTG_PWR";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ /*
+ * signal name from schematics: PWREN
+ */
+ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * signal name from schematics: USB_POWER
+ */
+ vin-supply = <&p5v0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led-blue {
+ label = "c2:blue:alive";
+ gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ p5v0: regulator-p5v0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "P5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ hdmi_p5v0: regulator-hdmi-p5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "HDMI_P5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ /* AP2331SA-7 */
+ vin-supply = <&p5v0>;
+ };
+
+ tflash_vdd: regulator-tflash-vdd {
+ compatible = "regulator-fixed";
+
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ /*
+ * signal name from schematics: TFLASH_VDD_EN
+ */
+ gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /* U16 RT9179GB */
+ vin-supply = <&vddio_ao3v3>;
+ };
+
+ tf_io: gpio-regulator-tf-io {
+ compatible = "regulator-gpio";
+
+ regulator-name = "TF_IO";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ /*
+ * signal name from schematics: TF_3V3N_1V8_EN
+ */
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+
+ states = <3300000 0>,
+ <1800000 1>;
+ /* U12/U13 RT9179GB */
+ vin-supply = <&vddio_ao3v3>;
+ };
+
+ vcc1v8: regulator-vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ /* U18 RT9179GB */
+ vin-supply = <&vddio_ao3v3>;
+ };
+
+ vcc3v3: regulator-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao1v8: regulator-vddio-ao1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ /* U17 RT9179GB */
+ vin-supply = <&p5v0>;
+ };
+
+ vddio_ao3v3: regulator-vddio-ao3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ /* U11 MP2161GJ-C499 */
+ vin-supply = <&p5v0>;
+ };
+
+ ddr3_1v5: regulator-ddr3-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "DDR3_1V5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ /* U15 MP2161GJ-C499 */
+ vin-supply = <&p5v0>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "ODROID-C2";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&pcm5242>;
+ };
+ };
+
+ dai-link-5 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_ao_6_pins &i2s_am_clk_pins &i2s_out_ao_clk_pins &i2s_out_lr_clk_pins &i2s_out_ch01_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&clkc {
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+};
+
+&ethmac {
+ status = "okay";
+ pinctrl-0 = <&eth_rgmii_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&eth_phy0>;
+ phy-mode = "rgmii";
+
+ amlogic,tx-delay-ns = <2>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_p5v0>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&i2c_A {
+ status = "okay";
+ pinctrl-0 = <&i2c_a_pins>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcm5242: pcm5242@4c {
+ compatible = "ti,pcm5242";
+ reg = <0x4c>;
+ #sound-dai-cells = <0>;
+
+ AVDD-supply = <&vddio_ao3v3>;
+ DVDD-supply = <&vddio_ao3v3>;
+ CPVDD-supply = <&vddio_ao3v3>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+ linux,rc-map-name = "rc-odroid";
+};
+
+&gpio_ao {
+ gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
+ "USB HUB nRESET", "USB OTG Power En",
+ "SPDIF_OUTPUT", "IR In", "I2S_MCLK",
+ "I2S_SCLK", "I2S_LRCLK", "I2S_DATA_OUTPUT",
+ "HDMI CEC", "SYS LED",
+ /* GPIO_TEST_N */
+ "";
+};
+
+&gpio {
+ gpio-line-names = /* Bank GPIOZ */
+ "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
+ "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
+ "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
+ "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
+ "Eth PHY nRESET", "Eth PHY Intc",
+ /* Bank GPIOH */
+ "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "",
+ /* Bank BOOT */
+ "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
+ "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
+ "eMMC Reset", "eMMC CMD",
+ "", "", "", "", "", "", "",
+ /* Bank CARD */
+ "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
+ "SDCard D3", "SDCard D2", "SDCard Det",
+ /* Bank GPIODV */
+ "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "",
+ "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
+ "PWM D", "PWM B",
+ /* Bank GPIOY */
+ "Revision Bit0", "Revision Bit1", "",
+ "J2 Header Pin35", "", "", "", "J2 Header Pin36",
+ "J2 Header Pin31", "", "", "", "TF VDD En",
+ "J2 Header Pin32", "J2 Header Pin26", "", "",
+ /* Bank GPIOX */
+ "J2 Header Pin29", "J2 Header Pin24",
+ "J2 Header Pin23", "J2 Header Pin22",
+ "J2 Header Pin21", "J2 Header Pin18",
+ "J2 Header Pin33", "J2 Header Pin19",
+ "J2 Header Pin16", "J2 Header Pin15",
+ "J2 Header Pin12", "J2 Header Pin13",
+ "J2 Header Pin8", "J2 Header Pin10",
+ "", "", "", "", "",
+ "J2 Header Pin11", "", "J2 Header Pin7", "",
+ /* Bank GPIOCLK */
+ "", "", "", "";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vcc1v8>;
+};
+
+&scpi_clocks {
+ status = "disabled";
+};
+
+/* SD */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&tf_io>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc3v3>;
+ vqmmc-supply = <&vcc1v8>;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb0_phy {
+ status = "disabled";
+ phy-supply = <&usb_otg_pwr>;
+};
+
+&usb1_phy {
+ status = "okay";
+ phy-supply = <&usb_otg_pwr>;
+};
+
+&usb0 {
+ status = "disabled";
+};
+
+&usb1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub@1 {
+ /* Genesys Logic GL852G USB 2.0 hub */
+ compatible = "usb5e3,610";
+ reg = <1>;
+ vdd-supply = <&p5v0>;
+ reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
+ };
+};
--
2.34.1

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@ -0,0 +1,64 @@
From 21708d1bcb84d0d8260c143746df5bff8dbe7a77 Mon Sep 17 00:00:00 2001
From: Da Xue <da@libre.computer>
Date: Tue, 8 Aug 2023 01:00:15 -0400
Subject: [PATCH 22/37] WIP: net: phy: meson-gxl: implement
meson_gxl_phy_resume()
While testing the suspend/resume functionality, we found the ethernet
is broken if internal PHY of the Amlogic meson GXL SoC is used.
After system resume back, the ethernet is down, no carrier can be found.
eth0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq state
DOWN group default qlen 1000
In this patch, the internal PHY is re-initialized to fix this problem.
eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP
group default qlen 1000
Cc: stable@vger.kernel.org # v5.10+
Fixes: 7334b3e47aee ("net: phy: Add Meson GXL Internal PHY driver")
Signed-off-by: Da Xue <da@libre.computer>
Signed-off-by: Luke Lu <luke.lu@libre.computer>
---
drivers/net/phy/meson-gxl.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
index 962ebbbc1348..55f281202fd4 100644
--- a/drivers/net/phy/meson-gxl.c
+++ b/drivers/net/phy/meson-gxl.c
@@ -132,6 +132,21 @@ static int meson_gxl_config_init(struct phy_device *phydev)
return 0;
}
+static int meson_gxl_phy_resume(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = genphy_resume(phydev);
+ if (ret)
+ return ret;
+
+ ret = meson_gxl_config_init(phydev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
/* This function is provided to cope with the possible failures of this phy
* during aneg process. When aneg fails, the PHY reports that aneg is done
* but the value found in MII_LPA is wrong:
@@ -196,7 +211,7 @@ static struct phy_driver meson_gxl_phy[] = {
.config_intr = smsc_phy_config_intr,
.handle_interrupt = smsc_phy_handle_interrupt,
.suspend = genphy_suspend,
- .resume = genphy_resume,
+ .resume = meson_gxl_phy_resume,
.read_mmd = genphy_read_mmd_unsupported,
.write_mmd = genphy_write_mmd_unsupported,
}, {
--
2.34.1

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@ -1,120 +0,0 @@
From 1283c858520094cb01ff6fc133eab9cad8c7e276 Mon Sep 17 00:00:00 2001
From: Anand Moon <linux.amoon@gmail.com>
Date: Wed, 22 Nov 2023 23:53:46 +0530
Subject: [PATCH 23/53] FROMLIST(v4): dt-bindings: usb: Add the binding example
for the Genesys Logic GL3523 hub
Add the binding example for the USB3.1 Genesys Logic GL3523
integrates with USB 3.1 Gen 1 Super Speed and USB 2.0 High-Speed
hub.
Onboard USB hub supports USB 3.x and USB 2.0 peer controllers.
which has a common reset pin and power supply.
peer-hub phandle each peer controller with proper gpio reset
and help each peer power on during initialization
and power off during suspend.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
.../bindings/usb/genesys,gl850g.yaml | 67 +++++++++++++++++--
1 file changed, 63 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml
index 37cf5249e526..47b7789ce7a5 100644
--- a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml
+++ b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml
@@ -9,9 +9,6 @@ title: Genesys Logic USB hub controller
maintainers:
- Icenowy Zheng <uwu@icenowy.me>
-allOf:
- - $ref: usb-device.yaml#
-
properties:
compatible:
enum:
@@ -27,7 +24,16 @@ properties:
vdd-supply:
description:
- the regulator that provides 3.3V core power to the hub.
+ phandle to the regulator that provides power to the hub.
+
+ peer-hub:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ onboard USB hub supports USB 3.x and USB 2.0 peer controllers.
+ which has a common reset pin and power supply.
+ peer-hub phandle each peer controller with proper gpio reset
+ and help each peer power on during initialization
+ and power off during suspend.
peer-hub:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -38,6 +44,33 @@ required:
- compatible
- reg
+allOf:
+ - $ref: usb-device.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - usb5e3,608
+ then:
+ properties:
+ peer-hub: false
+ vdd-supply: false
+ reset-gpios: true
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - usb5e3,610
+ - usb5e3,620
+ then:
+ properties:
+ peer-hub: true
+ vdd-supply: true
+ reset-gpios: true
+
additionalProperties: false
examples:
@@ -54,3 +87,29 @@ examples:
reset-gpios = <&pio 7 2 GPIO_ACTIVE_LOW>;
};
};
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ usb {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_5v>;
+ };
+
+ /* 3.1 hub on port 4 */
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_5v>;
+ };
+ };
--
2.34.1

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@ -0,0 +1,62 @@
From 71facc1a41966252fd3368b8a6cfc02d3e91d85a Mon Sep 17 00:00:00 2001
From: Dongjin Kim <tobetter@gmail.com>
Date: Thu, 10 Sep 2020 11:01:33 +0900
Subject: [PATCH 23/37] WIP: drm/meson: add support for 2560x1440 resolution
output
Add support for Quad HD (QHD) 2560x1440 resolution output. Timings
have been adapted from the vendor kernel.
Signed-off-by: Joy Cho <joy.cho@hardkernel.com>
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
drivers/gpu/drm/meson/meson_vclk.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index dfe0c28a0f05..f5385b3e3796 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -357,6 +357,8 @@ enum {
MESON_VCLK_HDMI_594000,
/* 2970 /1 /1 /1 /5 /1 => /1 /2 */
MESON_VCLK_HDMI_594000_YUV420,
+/* 4830 /2 /1 /2 /5 /1 => /1 /1 */
+ MESON_VCLK_HDMI_241500,
};
struct meson_vclk_params {
@@ -467,6 +469,18 @@ struct meson_vclk_params {
.vid_pll_div = VID_PLL_DIV_5,
.vclk_div = 1,
},
+ [MESON_VCLK_HDMI_241500] = {
+ .pll_freq = 4830000000,
+ .phy_freq = 2415000000,
+ .venc_freq = 241500000,
+ .vclk_freq = 241500000,
+ .pixel_freq = 241500000,
+ .pll_od1 = 2,
+ .pll_od2 = 1,
+ .pll_od3 = 2,
+ .vid_pll_div = VID_PLL_DIV_5,
+ .vclk_div = 1,
+ },
{ /* sentinel */ },
};
@@ -894,6 +908,10 @@ static void meson_vclk_set(struct meson_drm *priv,
m = 0xf7;
frac = vic_alternate_clock ? 0x8148 : 0x10000;
break;
+ case 4830000:
+ m = 0xc9;
+ frac = 0xd560;
+ break;
}
meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
--
2.34.1

View File

@ -1,72 +0,0 @@
From 3b361c7741a8c9a7ba990eda872fcc7817d35b23 Mon Sep 17 00:00:00 2001
From: Anand Moon <linux.amoon@gmail.com>
Date: Tue, 10 Oct 2023 08:54:43 +0530
Subject: [PATCH 24/53] FROMLIST(v4): arm64: dts: amlogic: Used onboard usb hub
reset on odroid n2
On Odroid n2/n2+ previously use gpio-hog to reset the usb hub,
switch to used on-board usb hub reset to enable the usb hub
and enable power to hub.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
.../dts/amlogic/meson-g12b-odroid-n2.dtsi | 36 ++++++++++++-------
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
index d80dd9a3da31..86eb81112232 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
@@ -31,6 +31,30 @@ hub_5v: regulator-hub-5v {
enable-active-high;
};
+ /* USB hub supports both USB 2.0 and USB 3.0 root hub */
+ usb-hub {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ vdd-supply = <&usb_pwr_en>;
+ };
+
+ /* 3.0 hub on port 4 */
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_5v>;
+ };
+ };
+
sound {
compatible = "amlogic,axg-sound-card";
model = "ODROID-N2";
@@ -234,18 +258,6 @@ &gpio {
"PIN_3", /* GPIOX_17 */
"PIN_5", /* GPIOX_18 */
"PIN_36"; /* GPIOX_19 */
- /*
- * WARNING: The USB Hub on the Odroid-N2 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- usb-hub-hog {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
};
&i2c3 {
--
2.34.1

View File

@ -0,0 +1,89 @@
From 5d95e031c6517a910173b80c50b800ffdc6493fa Mon Sep 17 00:00:00 2001
From: Luke Lu <luke.lu@libre.computer>
Date: Mon, 21 Aug 2023 10:50:04 +0000
Subject: [PATCH 24/37] WIP: drm/meson: do setup after resumption to fix hdmi
output
Some HDMI displays connected to gxl-based boards go black after
resumption, but recover after disconnecting and reconnecting.
Redoing setup by calling dw_hdmi_poweron() fixes the problem, which
requires a call of dw_hdmi_poweroff() to maintain the internal state.
Signed-off-by: Luke Lu <luke.lu@libre.computer>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 ++++--
drivers/gpu/drm/meson/meson_dw_hdmi.c | 3 +++
include/drm/bridge/dw_hdmi.h | 3 ++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 8791408dd1ff..5eb864d2678e 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2378,7 +2378,7 @@ static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
}
-static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
+void dw_hdmi_poweron(struct dw_hdmi *hdmi)
{
hdmi->bridge_is_on = true;
@@ -2388,8 +2388,9 @@ static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
*/
dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
}
+EXPORT_SYMBOL_GPL(dw_hdmi_poweron);
-static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
+void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
{
if (hdmi->phy.enabled) {
hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
@@ -2398,6 +2399,7 @@ static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
hdmi->bridge_is_on = false;
}
+EXPORT_SYMBOL_GPL(dw_hdmi_poweroff);
static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
{
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index 0d7c68b29dff..8460c93d74cb 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -809,6 +809,8 @@ static int __maybe_unused meson_dw_hdmi_pm_suspend(struct device *dev)
meson_dw_hdmi->data->top_write(meson_dw_hdmi,
HDMITX_TOP_SW_RESET, 0);
+ dw_hdmi_poweroff(meson_dw_hdmi->hdmi);
+
return 0;
}
@@ -821,6 +823,7 @@ static int __maybe_unused meson_dw_hdmi_pm_resume(struct device *dev)
meson_dw_hdmi_init(meson_dw_hdmi);
+ dw_hdmi_poweron(meson_dw_hdmi->hdmi);
dw_hdmi_resume(meson_dw_hdmi->hdmi);
return 0;
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 6a46baa0737c..5eac26a51245 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -171,7 +171,8 @@ void dw_hdmi_unbind(struct dw_hdmi *hdmi);
struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
struct drm_encoder *encoder,
const struct dw_hdmi_plat_data *plat_data);
-
+void dw_hdmi_poweron(struct dw_hdmi *hdmi);
+void dw_hdmi_poweroff(struct dw_hdmi *hdmi);
void dw_hdmi_resume(struct dw_hdmi *hdmi);
void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
--
2.34.1

View File

@ -1,64 +0,0 @@
From 983b5729b97918d6c860bdfd01093cf60b0ea83e Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 30 Jan 2023 05:09:18 +0000
Subject: [PATCH 25/53] FROMLIST(v1): arm64: dts: meson: radxa-zero2: add
pwm-fan support
The A311D on Zero2 needs active cooling and the board includes a header to
connect a simple fan. Add pwm-fan support with basic thermal properties so
the fan runs when connected.
Suggested-by: Yuntian Zhang <yt@radxa.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../dts/amlogic/meson-g12b-radxa-zero2.dts | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
index 890f5bfebb03..895b6ea67180 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
@@ -33,6 +33,15 @@ memory@0 {
reg = <0x0 0x0 0x0 0x80000000>;
};
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-min-state = <0>;
+ cooling-max-state = <4>;
+ cooling-levels = <0 64 128 192 255>;
+ pwms = <&pwm_AO_ab 0 40000 0>;
+ };
+
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <100>;
@@ -286,6 +295,24 @@ &cpu103 {
clock-latency = <50000>;
};
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ trip = <&cpu_passive>;
+ cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&ddr_thermal {
+ cooling-maps {
+ map0 {
+ trip = <&ddr_passive>;
+ cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&frddr_a {
status = "okay";
};
--
2.34.1

View File

@ -0,0 +1,77 @@
From b31529fd0ef42632387ce46def44a4e847d88ce1 Mon Sep 17 00:00:00 2001
From: Luke Lu <luke.lu@libre.computer>
Date: Wed, 13 Dec 2023 03:47:44 +0000
Subject: [PATCH 25/37] WIP: drm/meson: poweron/off dw_hdmi only if dw_hdmi
enabled
dw_hdmi_poweron() assumes that hdmi->curr_conn is valid. Calling
dw_hdmi_poweron() in meson_dw_hdmi_pm_resume() only with the bridge
enabled ensures this, avoiding invalid memory access when resuming
with HDMI port disconnected.
dw_hdmi_poweroff() is called to maintain the internal state of dw_hdmi.
This is only needed when dw_hdmi_poweron() will be called later, i.e.
dw_hdmi is enabled.
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 ++++++
drivers/gpu/drm/meson/meson_dw_hdmi.c | 7 +++++--
include/drm/bridge/dw_hdmi.h | 1 +
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 5eb864d2678e..15a90b43d607 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -3644,6 +3644,12 @@ void dw_hdmi_resume(struct dw_hdmi *hdmi)
}
EXPORT_SYMBOL_GPL(dw_hdmi_resume);
+bool dw_hdmi_is_bridge_on(struct dw_hdmi *hdmi)
+{
+ return !hdmi->disabled;
+}
+EXPORT_SYMBOL_GPL(dw_hdmi_is_bridge_on);
+
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index 8460c93d74cb..c44ed72a1155 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -809,7 +809,8 @@ static int __maybe_unused meson_dw_hdmi_pm_suspend(struct device *dev)
meson_dw_hdmi->data->top_write(meson_dw_hdmi,
HDMITX_TOP_SW_RESET, 0);
- dw_hdmi_poweroff(meson_dw_hdmi->hdmi);
+ if (dw_hdmi_is_bridge_on(meson_dw_hdmi->hdmi))
+ dw_hdmi_poweroff(meson_dw_hdmi->hdmi);
return 0;
}
@@ -823,7 +824,9 @@ static int __maybe_unused meson_dw_hdmi_pm_resume(struct device *dev)
meson_dw_hdmi_init(meson_dw_hdmi);
- dw_hdmi_poweron(meson_dw_hdmi->hdmi);
+ if (dw_hdmi_is_bridge_on(meson_dw_hdmi->hdmi))
+ dw_hdmi_poweron(meson_dw_hdmi->hdmi);
+
dw_hdmi_resume(meson_dw_hdmi->hdmi);
return 0;
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index 5eac26a51245..e57d61009645 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -174,6 +174,7 @@ struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
void dw_hdmi_poweron(struct dw_hdmi *hdmi);
void dw_hdmi_poweroff(struct dw_hdmi *hdmi);
void dw_hdmi_resume(struct dw_hdmi *hdmi);
+bool dw_hdmi_is_bridge_on(struct dw_hdmi *hdmi);
void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
--
2.34.1

View File

@ -1,53 +0,0 @@
From a4c4025275bcce3c13ff2d2b46dfa49ff947804a Mon Sep 17 00:00:00 2001
From: Haoran Liu <liuhaoran14@163.com>
Date: Wed, 29 Nov 2023 03:34:05 -0800
Subject: [PATCH 26/53] FROMLIST(v2): meson_plane: Add error handling
This patch adds robust error handling to the meson_plane_create
function in drivers/gpu/drm/meson/meson_plane.c. The function
previously lacked proper handling for potential failure scenarios
of the drm_universal_plane_init call.
Signed-off-by: Haoran Liu <liuhaoran14@163.com>
---
drivers/gpu/drm/meson/meson_plane.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index 815dfe30492b..b43ac61201f3 100644
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -534,6 +534,7 @@ int meson_plane_create(struct meson_drm *priv)
struct meson_plane *meson_plane;
struct drm_plane *plane;
const uint64_t *format_modifiers = format_modifiers_default;
+ int ret;
meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
GFP_KERNEL);
@@ -548,12 +549,16 @@ int meson_plane_create(struct meson_drm *priv)
else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
format_modifiers = format_modifiers_afbc_g12a;
- drm_universal_plane_init(priv->drm, plane, 0xFF,
- &meson_plane_funcs,
- supported_drm_formats,
- ARRAY_SIZE(supported_drm_formats),
- format_modifiers,
- DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
+ ret = drm_universal_plane_init(priv->drm, plane, 0xFF,
+ &meson_plane_funcs,
+ supported_drm_formats,
+ ARRAY_SIZE(supported_drm_formats),
+ format_modifiers,
+ DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
+ if (ret) {
+ devm_kfree(priv->drm->dev, meson_plane);
+ return ret;
+ }
drm_plane_helper_add(plane, &meson_plane_helper_funcs);
--
2.34.1

View File

@ -0,0 +1,24 @@
From b2f06cfdd0e7d396d51aa733597f2a6631a4dc8c Mon Sep 17 00:00:00 2001
From: Da Xue <da@libre.computer>
Date: Sun, 22 Jun 2025 17:46:21 -0400
Subject: [PATCH 26/37] WIP: mmc: meson-gx-mmc: add delay during poweroff
---
drivers/mmc/host/meson-gx-mmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 694bb443d5f3..a39906079d29 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -605,6 +605,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
case MMC_POWER_OFF:
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
mmc_regulator_disable_vqmmc(mmc);
+ msleep(50);
break;
--
2.34.1

View File

@ -1,262 +0,0 @@
From 6fd27cae52fb7b81a1a00822cd1e378ebb3de32b Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Sun, 18 Feb 2024 18:50:35 +0100
Subject: [PATCH 27/53] FROMLIST(v1): drm/meson: improve encoder probe /
initialization error handling
Rename meson_encoder_{cvbs,dsi,hdmi}_init() to
meson_encoder_{cvbs,dsi,hdmi}_probe() so it's clear that these functions
are used at probe time during driver initialization. Also switch all
error prints inside those functions to use dev_err_probe() for
consistency.
This makes the code more straight forward to read and makes the error
prints within those functions consistent (by logging all -EPROBE_DEFER
with dev_dbg(), while actual errors are logged with dev_err() and get
the error value printed).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/gpu/drm/meson/meson_drv.c | 6 +++---
drivers/gpu/drm/meson/meson_encoder_cvbs.c | 24 ++++++++++------------
drivers/gpu/drm/meson/meson_encoder_cvbs.h | 2 +-
drivers/gpu/drm/meson/meson_encoder_dsi.c | 23 +++++++++------------
drivers/gpu/drm/meson/meson_encoder_dsi.h | 2 +-
drivers/gpu/drm/meson/meson_encoder_hdmi.c | 15 +++++++-------
drivers/gpu/drm/meson/meson_encoder_hdmi.h | 2 +-
7 files changed, 35 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
index cb674966e9ac..17a5cca007e2 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -312,7 +312,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
/* Encoder Initialization */
- ret = meson_encoder_cvbs_init(priv);
+ ret = meson_encoder_cvbs_probe(priv);
if (ret)
goto exit_afbcd;
@@ -326,12 +326,12 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
}
}
- ret = meson_encoder_hdmi_init(priv);
+ ret = meson_encoder_hdmi_probe(priv);
if (ret)
goto exit_afbcd;
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
- ret = meson_encoder_dsi_init(priv);
+ ret = meson_encoder_dsi_probe(priv);
if (ret)
goto exit_afbcd;
}
diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
index 3407450435e2..d1191de855d9 100644
--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c
+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c
@@ -219,7 +219,7 @@ static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = {
.atomic_reset = drm_atomic_helper_bridge_reset,
};
-int meson_encoder_cvbs_init(struct meson_drm *priv)
+int meson_encoder_cvbs_probe(struct meson_drm *priv)
{
struct drm_device *drm = priv->drm;
struct meson_encoder_cvbs *meson_encoder_cvbs;
@@ -240,10 +240,9 @@ int meson_encoder_cvbs_init(struct meson_drm *priv)
meson_encoder_cvbs->next_bridge = of_drm_find_bridge(remote);
of_node_put(remote);
- if (!meson_encoder_cvbs->next_bridge) {
- dev_err(priv->dev, "Failed to find CVBS Connector bridge\n");
- return -EPROBE_DEFER;
- }
+ if (!meson_encoder_cvbs->next_bridge)
+ return dev_err_probe(priv->dev, -EPROBE_DEFER,
+ "Failed to find CVBS Connector bridge\n");
/* CVBS Encoder Bridge */
meson_encoder_cvbs->bridge.funcs = &meson_encoder_cvbs_bridge_funcs;
@@ -259,10 +258,9 @@ int meson_encoder_cvbs_init(struct meson_drm *priv)
/* Encoder */
ret = drm_simple_encoder_init(priv->drm, &meson_encoder_cvbs->encoder,
DRM_MODE_ENCODER_TVDAC);
- if (ret) {
- dev_err(priv->dev, "Failed to init CVBS encoder: %d\n", ret);
- return ret;
- }
+ if (ret)
+ return dev_err_probe(priv->dev, ret,
+ "Failed to init CVBS encoder\n");
meson_encoder_cvbs->encoder.possible_crtcs = BIT(0);
@@ -276,10 +274,10 @@ int meson_encoder_cvbs_init(struct meson_drm *priv)
/* Initialize & attach Bridge Connector */
connector = drm_bridge_connector_init(priv->drm, &meson_encoder_cvbs->encoder);
- if (IS_ERR(connector)) {
- dev_err(priv->dev, "Unable to create CVBS bridge connector\n");
- return PTR_ERR(connector);
- }
+ if (IS_ERR(connector))
+ return dev_err_probe(priv->dev, PTR_ERR(connector),
+ "Unable to create CVBS bridge connector\n");
+
drm_connector_attach_encoder(connector, &meson_encoder_cvbs->encoder);
priv->encoders[MESON_ENC_CVBS] = meson_encoder_cvbs;
diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.h b/drivers/gpu/drm/meson/meson_encoder_cvbs.h
index 09710fec3c66..7b7bc85c03f7 100644
--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.h
+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.h
@@ -24,7 +24,7 @@ struct meson_cvbs_mode {
/* Modes supported by the CVBS output */
extern struct meson_cvbs_mode meson_cvbs_modes[MESON_CVBS_MODES_COUNT];
-int meson_encoder_cvbs_init(struct meson_drm *priv);
+int meson_encoder_cvbs_probe(struct meson_drm *priv);
void meson_encoder_cvbs_remove(struct meson_drm *priv);
#endif /* __MESON_VENC_CVBS_H */
diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c
index 311b91630fbe..7816902f5907 100644
--- a/drivers/gpu/drm/meson/meson_encoder_dsi.c
+++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c
@@ -100,7 +100,7 @@ static const struct drm_bridge_funcs meson_encoder_dsi_bridge_funcs = {
.atomic_reset = drm_atomic_helper_bridge_reset,
};
-int meson_encoder_dsi_init(struct meson_drm *priv)
+int meson_encoder_dsi_probe(struct meson_drm *priv)
{
struct meson_encoder_dsi *meson_encoder_dsi;
struct device_node *remote;
@@ -118,10 +118,9 @@ int meson_encoder_dsi_init(struct meson_drm *priv)
}
meson_encoder_dsi->next_bridge = of_drm_find_bridge(remote);
- if (!meson_encoder_dsi->next_bridge) {
- dev_dbg(priv->dev, "Failed to find DSI transceiver bridge\n");
- return -EPROBE_DEFER;
- }
+ if (!meson_encoder_dsi->next_bridge)
+ return dev_err_probe(priv->dev, -EPROBE_DEFER,
+ "Failed to find DSI transceiver bridge\n");
/* DSI Encoder Bridge */
meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs;
@@ -135,19 +134,17 @@ int meson_encoder_dsi_init(struct meson_drm *priv)
/* Encoder */
ret = drm_simple_encoder_init(priv->drm, &meson_encoder_dsi->encoder,
DRM_MODE_ENCODER_DSI);
- if (ret) {
- dev_err(priv->dev, "Failed to init DSI encoder: %d\n", ret);
- return ret;
- }
+ if (ret)
+ return dev_err_probe(priv->dev, ret,
+ "Failed to init DSI encoder\n");
meson_encoder_dsi->encoder.possible_crtcs = BIT(0);
/* Attach DSI Encoder Bridge to Encoder */
ret = drm_bridge_attach(&meson_encoder_dsi->encoder, &meson_encoder_dsi->bridge, NULL, 0);
- if (ret) {
- dev_err(priv->dev, "Failed to attach bridge: %d\n", ret);
- return ret;
- }
+ if (ret)
+ return dev_err_probe(priv->dev, ret,
+ "Failed to attach bridge\n");
/*
* We should have now in place:
diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.h b/drivers/gpu/drm/meson/meson_encoder_dsi.h
index 9277d7015193..85d5b61805f2 100644
--- a/drivers/gpu/drm/meson/meson_encoder_dsi.h
+++ b/drivers/gpu/drm/meson/meson_encoder_dsi.h
@@ -7,7 +7,7 @@
#ifndef __MESON_ENCODER_DSI_H
#define __MESON_ENCODER_DSI_H
-int meson_encoder_dsi_init(struct meson_drm *priv);
+int meson_encoder_dsi_probe(struct meson_drm *priv);
void meson_encoder_dsi_remove(struct meson_drm *priv);
#endif /* __MESON_ENCODER_DSI_H */
diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
index c4686568c9ca..22e07847a9a7 100644
--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c
@@ -354,7 +354,7 @@ static const struct drm_bridge_funcs meson_encoder_hdmi_bridge_funcs = {
.atomic_reset = drm_atomic_helper_bridge_reset,
};
-int meson_encoder_hdmi_init(struct meson_drm *priv)
+int meson_encoder_hdmi_probe(struct meson_drm *priv)
{
struct meson_encoder_hdmi *meson_encoder_hdmi;
struct platform_device *pdev;
@@ -374,8 +374,8 @@ int meson_encoder_hdmi_init(struct meson_drm *priv)
meson_encoder_hdmi->next_bridge = of_drm_find_bridge(remote);
if (!meson_encoder_hdmi->next_bridge) {
- dev_err(priv->dev, "Failed to find HDMI transceiver bridge\n");
- ret = -EPROBE_DEFER;
+ ret = dev_err_probe(priv->dev, -EPROBE_DEFER,
+ "Failed to find HDMI transceiver bridge\n");
goto err_put_node;
}
@@ -393,7 +393,7 @@ int meson_encoder_hdmi_init(struct meson_drm *priv)
ret = drm_simple_encoder_init(priv->drm, &meson_encoder_hdmi->encoder,
DRM_MODE_ENCODER_TMDS);
if (ret) {
- dev_err(priv->dev, "Failed to init HDMI encoder: %d\n", ret);
+ dev_err_probe(priv->dev, ret, "Failed to init HDMI encoder\n");
goto err_put_node;
}
@@ -403,7 +403,7 @@ int meson_encoder_hdmi_init(struct meson_drm *priv)
ret = drm_bridge_attach(&meson_encoder_hdmi->encoder, &meson_encoder_hdmi->bridge, NULL,
DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (ret) {
- dev_err(priv->dev, "Failed to attach bridge: %d\n", ret);
+ dev_err_probe(priv->dev, ret, "Failed to attach bridge\n");
goto err_put_node;
}
@@ -411,8 +411,9 @@ int meson_encoder_hdmi_init(struct meson_drm *priv)
meson_encoder_hdmi->connector = drm_bridge_connector_init(priv->drm,
&meson_encoder_hdmi->encoder);
if (IS_ERR(meson_encoder_hdmi->connector)) {
- dev_err(priv->dev, "Unable to create HDMI bridge connector\n");
- ret = PTR_ERR(meson_encoder_hdmi->connector);
+ ret = dev_err_probe(priv->dev,
+ PTR_ERR(meson_encoder_hdmi->connector),
+ "Unable to create HDMI bridge connector\n");
goto err_put_node;
}
drm_connector_attach_encoder(meson_encoder_hdmi->connector,
diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.h b/drivers/gpu/drm/meson/meson_encoder_hdmi.h
index a6cd38eb5f71..fd5485875db8 100644
--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.h
+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.h
@@ -7,7 +7,7 @@
#ifndef __MESON_ENCODER_HDMI_H
#define __MESON_ENCODER_HDMI_H
-int meson_encoder_hdmi_init(struct meson_drm *priv);
+int meson_encoder_hdmi_probe(struct meson_drm *priv);
void meson_encoder_hdmi_remove(struct meson_drm *priv);
#endif /* __MESON_ENCODER_HDMI_H */
--
2.34.1

View File

@ -1,7 +1,7 @@
From 7354c155f1956487683a192e629cda68bcd38bd8 Mon Sep 17 00:00:00 2001
From 59614ff80eb272009bc6bdfcb47e8df6ec93a2a7 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Tue, 18 Jan 2022 15:09:12 +0000
Subject: [PATCH 43/53] WIP: arm64: dts: meson: set p212/p23x/q20x SDIO to
Subject: [PATCH 27/37] WIP: arm64: dts: meson: set p212/p23x/q20x SDIO to
100MHz
Amlogic datasheets describe 50MHz max-frequency for SDIO on GXL/GXM but
@ -79,10 +79,10 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 08d6b69ba469..9ac5079019fa 100644
index 6da1316d97c6..f6ef4fc4a85c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -256,7 +256,7 @@ &sd_emmc_a {
@@ -258,7 +258,7 @@ &sd_emmc_a {
bus-width = <4>;
cap-sd-highspeed;
@ -92,10 +92,10 @@ index 08d6b69ba469..9ac5079019fa 100644
non-removable;
disable-wp;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index 7e7dc87ede2d..1c64b2d64ae8 100644
index 05a0d4de3ad7..ccaadb497880 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -121,7 +121,7 @@ &sd_emmc_a {
@@ -119,7 +119,7 @@ &sd_emmc_a {
bus-width = <4>;
cap-sd-highspeed;

View File

@ -1,57 +0,0 @@
From 9fa5e4f1d94a0ca01deb5bbe03299e415f0df8c3 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Tue, 9 Jan 2024 16:20:14 +0000
Subject: [PATCH 28/53] FROMLIST(v1): drm/meson: vclk: fix calculation of 59.94
fractional rates
Playing 4K media with 59.94 fractional rate (typically VP9) causes the screen to lose
sync with the following error reported in the system log:
[ 89.610280] Fatal Error, invalid HDMI vclk freq 593406
Modetest shows the following:
3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407 flags: phsync, pvsync; type: driver
drm calculated value -------------------------------------^
Change the fractional rate calculation to stop DIV_ROUND_CLOSEST rounding down which
results in vclk freq failing to match correctly.
Fixes: e5fab2ec9ca4 ("drm/meson: vclk: add support for YUV420 setup")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
drivers/gpu/drm/meson/meson_vclk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index 2a82119eb58e..2a942dc6a6dc 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -790,13 +790,13 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq,
FREQ_1000_1001(params[i].pixel_freq));
DRM_DEBUG_DRIVER("i = %d phy_freq = %d alt = %d\n",
i, params[i].phy_freq,
- FREQ_1000_1001(params[i].phy_freq/10)*10);
+ FREQ_1000_1001(params[i].phy_freq/1000)*1000);
/* Match strict frequency */
if (phy_freq == params[i].phy_freq &&
vclk_freq == params[i].vclk_freq)
return MODE_OK;
/* Match 1000/1001 variant */
- if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/10)*10) &&
+ if (phy_freq == (FREQ_1000_1001(params[i].phy_freq/1000)*1000) &&
vclk_freq == FREQ_1000_1001(params[i].vclk_freq))
return MODE_OK;
}
@@ -1070,7 +1070,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
if ((phy_freq == params[freq].phy_freq ||
- phy_freq == FREQ_1000_1001(params[freq].phy_freq/10)*10) &&
+ phy_freq == FREQ_1000_1001(params[freq].phy_freq/1000)*1000) &&
(vclk_freq == params[freq].vclk_freq ||
vclk_freq == FREQ_1000_1001(params[freq].vclk_freq))) {
if (vclk_freq != params[freq].vclk_freq)
--
2.34.1

View File

@ -1,7 +1,7 @@
From 5661824fa83b4eeb182286aa8ad3b97d1025852c Mon Sep 17 00:00:00 2001
From 087bb82aefa86c31f4ea92774452392763a4c83b Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Tue, 18 Jan 2022 15:18:32 +0000
Subject: [PATCH 45/53] WIP: arm64: dts: meson: remove SDIO node from Khadas
Subject: [PATCH 28/37] WIP: arm64: dts: meson: remove SDIO node from Khadas
VIM1
Now that SDIO 100MHz max-frequency is inherited from the p212 dtsi we
@ -13,10 +13,10 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
1 file changed, 4 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index dacbca73279c..aeda42d5d606 100644
index e137ebd48c5e..563e6e909363 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -217,10 +217,6 @@ &pwm_ef {
@@ -219,10 +219,6 @@ &pwm_ef {
pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
};

View File

@ -1,43 +0,0 @@
From 5cddc22049efb7e7aa5382ce789379c943170187 Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Fri, 23 Feb 2024 18:51:07 +0100
Subject: [PATCH 29/53] FROMLIST(v1): ASoC: meson: axg-tdm-interface: fix mclk
setup without mclk-fs
By default, when mclk-fs is not provided, the tdm-interface driver
requests an MCLK that is 4x the bit clock, SCLK.
However there is no justification for this:
* If the codec needs MCLK for its operation, mclk-fs is expected to be set
according to the codec requirements.
* If the codec does not need MCLK the minimum is 2 * SCLK, because this is
minimum the divider between SCLK and MCLK can do.
Multiplying by 4 may cause problems because the PLL limit may be reached
sooner than it should, so use 2x instead.
Fixes: d60e4f1e4be5 ("ASoC: meson: add tdm interface driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
sound/soc/meson/axg-tdm-interface.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-interface.c
index 1c3d433cefd2..cd5168e826df 100644
--- a/sound/soc/meson/axg-tdm-interface.c
+++ b/sound/soc/meson/axg-tdm-interface.c
@@ -264,8 +264,8 @@ static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
srate = iface->slots * iface->slot_width * params_rate(params);
if (!iface->mclk_rate) {
- /* If no specific mclk is requested, default to bit clock * 4 */
- clk_set_rate(iface->mclk, 4 * srate);
+ /* If no specific mclk is requested, default to bit clock * 2 */
+ clk_set_rate(iface->mclk, 2 * srate);
} else {
/* Check if we can actually get the bit clock from mclk */
if (iface->mclk_rate % srate) {
--
2.34.1

View File

@ -1,7 +1,7 @@
From fb6de4d2453abb6e9ff8f0b653eb12e94156958c Mon Sep 17 00:00:00 2001
From d05fd0dbca2f4e7233ca5c1fb9fc8ca5575d4dbc Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 19 Jan 2022 06:45:06 +0000
Subject: [PATCH 44/53] WIP: arm64: dts: meson: add UHS SDIO capabilities to
Subject: [PATCH 29/37] WIP: arm64: dts: meson: add UHS SDIO capabilities to
p212/p23x/q20x
Add UHS capabilities to the SDIO node to enable 100MHz speeds.
@ -13,10 +13,10 @@ Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 9ac5079019fa..e6f88ec58869 100644
index f6ef4fc4a85c..b3385f71bb48 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -256,6 +256,10 @@ &sd_emmc_a {
@@ -258,6 +258,10 @@ &sd_emmc_a {
bus-width = <4>;
cap-sd-highspeed;
@ -28,10 +28,10 @@ index 9ac5079019fa..e6f88ec58869 100644
non-removable;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index 1c64b2d64ae8..b83b38b2d9e1 100644
index ccaadb497880..59539eca8f42 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -121,6 +121,10 @@ &sd_emmc_a {
@@ -119,6 +119,10 @@ &sd_emmc_a {
bus-width = <4>;
cap-sd-highspeed;

View File

@ -1,80 +0,0 @@
From 69a95e8b2be63812ca0b8e3b59786a21f074cfe9 Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Fri, 23 Feb 2024 18:51:08 +0100
Subject: [PATCH 30/53] FROMLIST(v1): ASoC: meson: axg-tdm-interface: add frame
rate constraint
According to Amlogic datasheets for the SoCs supported by this driver, the
maximum bit clock rate is 100MHz.
The tdm interface allows the rates listed by the DAI driver, regardless of
the number slots or their width. However, these will impact the bit clock
rate.
Hitting the 100MHz limit is very unlikely for most use cases but it is
possible.
For example with 32 slots / 32 bits wide, the maximum rate is no longer
384kHz but ~96kHz.
Add the constraint accordingly if the component is not already active.
If it is active, the rate is already constrained by the first stream rate.
Fixes: d60e4f1e4be5 ("ASoC: meson: add tdm interface driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
sound/soc/meson/axg-tdm-interface.c | 25 ++++++++++++++++++-------
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-interface.c
index cd5168e826df..2cedbce73837 100644
--- a/sound/soc/meson/axg-tdm-interface.c
+++ b/sound/soc/meson/axg-tdm-interface.c
@@ -12,6 +12,9 @@
#include "axg-tdm.h"
+/* Maximum bit clock frequency according the datasheets */
+#define MAX_SCLK 100000000 /* Hz */
+
enum {
TDM_IFACE_PAD,
TDM_IFACE_LOOPBACK,
@@ -153,19 +156,27 @@ static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
return -EINVAL;
}
- /* Apply component wide rate symmetry */
if (snd_soc_component_active(dai->component)) {
+ /* Apply component wide rate symmetry */
ret = snd_pcm_hw_constraint_single(substream->runtime,
SNDRV_PCM_HW_PARAM_RATE,
iface->rate);
- if (ret < 0) {
- dev_err(dai->dev,
- "can't set iface rate constraint\n");
- return ret;
- }
+
+ } else {
+ /* Limit rate according to the slot number and width */
+ unsigned int max_rate =
+ MAX_SCLK / (iface->slots * iface->slot_width);
+ ret = snd_pcm_hw_constraint_minmax(substream->runtime,
+ SNDRV_PCM_HW_PARAM_RATE,
+ 0, max_rate);
}
- return 0;
+ if (ret < 0)
+ dev_err(dai->dev, "can't set iface rate constraint\n");
+ else
+ ret = 0;
+
+ return ret;
}
static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
--
2.34.1

View File

@ -0,0 +1,28 @@
From 595ae18972bfb55b20eecf724cf73d3c3b133910 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Thu, 9 Feb 2023 09:59:58 +0000
Subject: [PATCH 30/37] WIP: dt-bindings: arm: amlogic: add support for Tanix
TX9 Pro
The Oranth Tanix TX9 Pro is an Android STB using the Amlogic S912 chip
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 05edf22e6c30..13dd7abbdcf8 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -134,6 +134,7 @@ properties:
- libretech,aml-s912-pc
- minix,neo-u9h
- nexbox,a1
+ - oranth,tx9-pro
- tronsmart,vega-s96
- videostrong,gxm-kiii-pro
- wetek,core2
--
2.34.1

View File

@ -1,32 +0,0 @@
From 9b3d51967fcfe47d82f280e8030aa3dc5fcc5c02 Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Fri, 23 Feb 2024 18:51:09 +0100
Subject: [PATCH 31/53] FROMLIST(v1): ASoC: meson: axg-tdm-interface: update
error format error traces
ASoC stopped using CBS_CFS and CBM_CFM a few years ago but the traces in
the amlogic tdm interface driver did not follow.
Update this to match the new format names
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
sound/soc/meson/axg-tdm-interface.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/meson/axg-tdm-interface.c b/sound/soc/meson/axg-tdm-interface.c
index 2cedbce73837..bf708717635b 100644
--- a/sound/soc/meson/axg-tdm-interface.c
+++ b/sound/soc/meson/axg-tdm-interface.c
@@ -133,7 +133,7 @@ static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_BP_FC:
case SND_SOC_DAIFMT_BC_FP:
- dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n");
+ dev_err(dai->dev, "only BP_FP and BC_FC are supported\n");
fallthrough;
default:
return -EINVAL;
--
2.34.1

View File

@ -0,0 +1,139 @@
From 08187f15dc8ca4b29e2b847b3c5ed0026191480e Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Thu, 9 Feb 2023 10:01:14 +0000
Subject: [PATCH 31/37] WIP: arm64: dts: meson: add initial device-tree for
Tanix TX9 Pro
Oranth Tanix TX9 Pro is based on the Amlogic Q200 reference design with
an S912 chip and the following specs:
- 3GB DDR3 RAM
- 32GB eMMC
- 10/100/1000 Base-T Ethernet
- AP6356 Wireless (802.11 b/g/n/ac, BT 5.0)
- HDMI 2.0a video
- VFD for clock/status
- 2x USB 2.0 ports
- IR receiver
- 1x Power LED (white)
- 1x Update/Reset button (underside)
- 1x micro SD card slot
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../boot/dts/amlogic/meson-gxm-tx9-pro.dts | 90 +++++++++++++++++++
2 files changed, 91 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index b593736ff60b..9e57cc56bfa7 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-tx9-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts
new file mode 100644
index 000000000000..9a62176cfe5a
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ compatible = "oranth,tx9-pro", "amlogic,s912", "amlogic,meson-gxm";
+ model = "Tanix TX9 Pro";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1710000>;
+
+ button-function {
+ label = "Update";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ button {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ethmac {
+ pinctrl-0 = <&eth_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&external_phy>;
+ amlogic,tx-delay-ns = <2>;
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_15 */
+ interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&ir {
+ linux,rc-map-name = "rc-tanix-tx3mini";
+};
+
+&sd_emmc_a {
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ max-speed = <2000000>;
+ clocks = <&wifi32k>;
+ clock-names = "lpo";
+ };
+};
--
2.34.1

View File

@ -1,47 +0,0 @@
From b399257ec04a93856fd0f1ebf5b6060dddf6aaed Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Fri, 23 Feb 2024 18:51:10 +0100
Subject: [PATCH 32/53] FROMLIST(v1): ASoC: meson: axg-spdifin: use max width
for rate detection
Use maximum width between 2 edges to setup spdifin thresholds
and detect the input sample rate. This comes from Amlogic SDK and
seems to be marginally more reliable than minimum width.
This is done to align with a future eARC support.
No issue was reported with minimum width so far, this is considered
to be an update so no Fixes tag is set.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
sound/soc/meson/axg-spdifin.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/soc/meson/axg-spdifin.c b/sound/soc/meson/axg-spdifin.c
index bc2f2849ecfb..e721f579321e 100644
--- a/sound/soc/meson/axg-spdifin.c
+++ b/sound/soc/meson/axg-spdifin.c
@@ -179,9 +179,9 @@ static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
SPDIFIN_CTRL1_BASE_TIMER,
FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000));
- /* Threshold based on the minimum width between two edges */
+ /* Threshold based on the maximum width between two edges */
regmap_update_bits(priv->map, SPDIFIN_CTRL0,
- SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL);
+ SPDIFIN_CTRL0_WIDTH_SEL, 0);
/* Calculate the last timer which has no threshold */
t_next = axg_spdifin_mode_timer(priv, i, rate);
@@ -199,7 +199,7 @@ static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
axg_spdifin_write_timer(priv->map, i, t);
/* Set the threshold value */
- axg_spdifin_write_threshold(priv->map, i, t + t_next);
+ axg_spdifin_write_threshold(priv->map, i, 3 * (t + t_next));
/* Save the current timer for the next threshold calculation */
t_next = t;
--
2.34.1

View File

@ -1,26 +1,21 @@
From 58d3f1f106febd55da1b5e56016fb8e33fde09bd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
From bb0a8ba6c365a8dd979f2e3d040f565a1d1f36b0 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Sun, 20 Feb 2022 08:23:12 +0000
Subject: [PATCH 13/53] FROMLIST(v5): dt-bindings: vendor-prefixes: Add Titan
Micro Electronics
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Subject: [PATCH 32/37] WIP: dt-bindings: vendor-prefixes: add Titan Micro
Electronics
Assign vendor prefix "titanmec", matching their domain name.
Add a vendor prefix for Shenzhen Titan Micro Electronics Co., Ltd.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Heiner Kallweit <christianshewitt@gmail.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 1a0dc04f1db4..a3c08f859ab1 100644
index 5d2a7a8d3ac6..32f8f24ec809 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1427,6 +1427,8 @@ patternProperties:
@@ -1548,6 +1548,8 @@ patternProperties:
description: Texas Instruments
"^tianma,.*":
description: Tianma Micro-electronics Co., Ltd.

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@ -1,90 +0,0 @@
From 453af3a1ee8cea68dfdbdaed7a0a41f4a3743c76 Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Fri, 23 Feb 2024 18:51:11 +0100
Subject: [PATCH 33/53] FROMLIST(v1): ASoC: meson: axg-fifo: take continuous
rates
The rate of the stream does not matter for the fifos of the axg family.
Fifos will just push or pull data to/from the DDR according to consumption
or production of the downstream element, which is the DPCM backend.
Drop the rate list and allow continuous rates. The lower and upper rate are
set according what is known to work with the different backends
This allows the PDM input backend to also use continuous rates.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
sound/soc/meson/axg-fifo.h | 2 --
sound/soc/meson/axg-frddr.c | 8 ++++++--
sound/soc/meson/axg-toddr.c | 8 ++++++--
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h
index df528e8cb7c9..a14c31eb06d8 100644
--- a/sound/soc/meson/axg-fifo.h
+++ b/sound/soc/meson/axg-fifo.h
@@ -21,8 +21,6 @@ struct snd_soc_dai_driver;
struct snd_soc_pcm_runtime;
#define AXG_FIFO_CH_MAX 128
-#define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \
- SNDRV_PCM_RATE_8000_384000)
#define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_LE | \
diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c
index 8c166a5f338c..98140f449eb3 100644
--- a/sound/soc/meson/axg-frddr.c
+++ b/sound/soc/meson/axg-frddr.c
@@ -109,7 +109,9 @@ static struct snd_soc_dai_driver axg_frddr_dai_drv = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
- .rates = AXG_FIFO_RATES,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ .rate_min = 5515,
+ .rate_max = 384000,
.formats = AXG_FIFO_FORMATS,
},
.ops = &axg_frddr_ops,
@@ -184,7 +186,9 @@ static struct snd_soc_dai_driver g12a_frddr_dai_drv = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
- .rates = AXG_FIFO_RATES,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ .rate_min = 5515,
+ .rate_max = 384000,
.formats = AXG_FIFO_FORMATS,
},
.ops = &g12a_frddr_ops,
diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c
index 1a0be177b8fe..32ee45cce7f8 100644
--- a/sound/soc/meson/axg-toddr.c
+++ b/sound/soc/meson/axg-toddr.c
@@ -131,7 +131,9 @@ static struct snd_soc_dai_driver axg_toddr_dai_drv = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
- .rates = AXG_FIFO_RATES,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ .rate_min = 5515,
+ .rate_max = 384000,
.formats = AXG_FIFO_FORMATS,
},
.ops = &axg_toddr_ops,
@@ -226,7 +228,9 @@ static struct snd_soc_dai_driver g12a_toddr_dai_drv = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = AXG_FIFO_CH_MAX,
- .rates = AXG_FIFO_RATES,
+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
+ .rate_min = 5515,
+ .rate_max = 384000,
.formats = AXG_FIFO_FORMATS,
},
.ops = &g12a_toddr_ops,
--
2.34.1

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@ -0,0 +1,29 @@
From ea1f663261cea2fe53626fd2d96c5e8b4d475e28 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Thu, 12 Jun 2025 10:25:29 +0000
Subject: [PATCH 33/37] WIP: dt-bindings: vendor-prefixes: add Fuda Hisi
Microelectronics
Add the "fdhisi" prefix for Fuda Hisi Microelectronics Co, Ltd.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 32f8f24ec809..d02615496b2b 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -531,6 +531,8 @@ patternProperties:
description: Fastrax Oy
"^fcs,.*":
description: Fairchild Semiconductor
+ "^fdhisi,.*":
+ description: Fuzhou Fuda Hisi Microelectronics Co., Ltd.
"^feixin,.*":
description: Shenzhen Feixin Photoelectic Co., Ltd
"^feiyang,.*":
--
2.34.1

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@ -1,176 +0,0 @@
From 3e72fee0fba2026ba5c16a4a3f329fc04fcce310 Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Fri, 23 Feb 2024 18:51:12 +0100
Subject: [PATCH 34/53] FROMLIST(v1): ASoC: meson: axg-fifo: use FIELD helpers
Use FIELD_GET() and FIELD_PREP() helpers instead of doing it manually.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
sound/soc/meson/axg-fifo.c | 24 ++++++++++++------------
sound/soc/meson/axg-fifo.h | 12 +++++-------
sound/soc/meson/axg-frddr.c | 4 ++--
sound/soc/meson/axg-toddr.c | 21 +++++++++------------
4 files changed, 28 insertions(+), 33 deletions(-)
diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c
index 65541fdb0038..597fd39e6e48 100644
--- a/sound/soc/meson/axg-fifo.c
+++ b/sound/soc/meson/axg-fifo.c
@@ -145,8 +145,8 @@ int axg_fifo_pcm_hw_params(struct snd_soc_component *component,
/* Enable irq if necessary */
irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT;
regmap_update_bits(fifo->map, FIFO_CTRL0,
- CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
- CTRL0_INT_EN(irq_en));
+ CTRL0_INT_EN,
+ FIELD_PREP(CTRL0_INT_EN, irq_en));
return 0;
}
@@ -176,9 +176,9 @@ int axg_fifo_pcm_hw_free(struct snd_soc_component *component,
{
struct axg_fifo *fifo = axg_fifo_data(ss);
- /* Disable the block count irq */
+ /* Disable irqs */
regmap_update_bits(fifo->map, FIFO_CTRL0,
- CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
+ CTRL0_INT_EN, 0);
return 0;
}
@@ -187,13 +187,13 @@ EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free);
static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
{
regmap_update_bits(fifo->map, FIFO_CTRL1,
- CTRL1_INT_CLR(FIFO_INT_MASK),
- CTRL1_INT_CLR(mask));
+ CTRL1_INT_CLR,
+ FIELD_PREP(CTRL1_INT_CLR, mask));
/* Clear must also be cleared */
regmap_update_bits(fifo->map, FIFO_CTRL1,
- CTRL1_INT_CLR(FIFO_INT_MASK),
- 0);
+ CTRL1_INT_CLR,
+ FIELD_PREP(CTRL1_INT_CLR, 0));
}
static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
@@ -204,7 +204,7 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
regmap_read(fifo->map, FIFO_STATUS1, &status);
- status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
+ status = FIELD_GET(STATUS1_INT_STS, status);
if (status & FIFO_INT_COUNT_REPEAT)
snd_pcm_period_elapsed(ss);
else
@@ -254,15 +254,15 @@ int axg_fifo_pcm_open(struct snd_soc_component *component,
/* Setup status2 so it reports the memory pointer */
regmap_update_bits(fifo->map, FIFO_CTRL1,
- CTRL1_STATUS2_SEL_MASK,
- CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
+ CTRL1_STATUS2_SEL,
+ FIELD_PREP(CTRL1_STATUS2_SEL, STATUS2_SEL_DDR_READ));
/* Make sure the dma is initially disabled */
__dma_enable(fifo, false);
/* Disable irqs until params are ready */
regmap_update_bits(fifo->map, FIFO_CTRL0,
- CTRL0_INT_EN(FIFO_INT_MASK), 0);
+ CTRL0_INT_EN, 0);
/* Clear any pending interrupt */
axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
diff --git a/sound/soc/meson/axg-fifo.h b/sound/soc/meson/axg-fifo.h
index a14c31eb06d8..4c48c0a08481 100644
--- a/sound/soc/meson/axg-fifo.h
+++ b/sound/soc/meson/axg-fifo.h
@@ -40,21 +40,19 @@ struct snd_soc_pcm_runtime;
#define FIFO_CTRL0 0x00
#define CTRL0_DMA_EN BIT(31)
-#define CTRL0_INT_EN(x) ((x) << 16)
+#define CTRL0_INT_EN GENMASK(23, 16)
#define CTRL0_SEL_MASK GENMASK(2, 0)
#define CTRL0_SEL_SHIFT 0
#define FIFO_CTRL1 0x04
-#define CTRL1_INT_CLR(x) ((x) << 0)
-#define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8)
-#define CTRL1_STATUS2_SEL(x) ((x) << 8)
+#define CTRL1_INT_CLR GENMASK(7, 0)
+#define CTRL1_STATUS2_SEL GENMASK(11, 8)
#define STATUS2_SEL_DDR_READ 0
-#define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24)
-#define CTRL1_FRDDR_DEPTH(x) ((x) << 24)
+#define CTRL1_FRDDR_DEPTH GENMASK(31, 24)
#define FIFO_START_ADDR 0x08
#define FIFO_FINISH_ADDR 0x0c
#define FIFO_INT_ADDR 0x10
#define FIFO_STATUS1 0x14
-#define STATUS1_INT_STS(x) ((x) << 0)
+#define STATUS1_INT_STS GENMASK(7, 0)
#define FIFO_STATUS2 0x18
#define FIFO_INIT_ADDR 0x24
#define FIFO_CTRL2 0x28
diff --git a/sound/soc/meson/axg-frddr.c b/sound/soc/meson/axg-frddr.c
index 98140f449eb3..97ca0ea5faa5 100644
--- a/sound/soc/meson/axg-frddr.c
+++ b/sound/soc/meson/axg-frddr.c
@@ -59,8 +59,8 @@ static int axg_frddr_dai_hw_params(struct snd_pcm_substream *substream,
/* Trim the FIFO depth if the period is small to improve latency */
depth = min(period, fifo->depth);
val = (depth / AXG_FIFO_BURST) - 1;
- regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,
- CTRL1_FRDDR_DEPTH(val));
+ regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH,
+ FIELD_PREP(CTRL1_FRDDR_DEPTH, val));
return 0;
}
diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c
index 32ee45cce7f8..5b08b4e841ad 100644
--- a/sound/soc/meson/axg-toddr.c
+++ b/sound/soc/meson/axg-toddr.c
@@ -19,12 +19,9 @@
#define CTRL0_TODDR_EXT_SIGNED BIT(29)
#define CTRL0_TODDR_PP_MODE BIT(28)
#define CTRL0_TODDR_SYNC_CH BIT(27)
-#define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13)
-#define CTRL0_TODDR_TYPE(x) ((x) << 13)
-#define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8)
-#define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
-#define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
-#define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
+#define CTRL0_TODDR_TYPE GENMASK(15, 13)
+#define CTRL0_TODDR_MSB_POS GENMASK(12, 8)
+#define CTRL0_TODDR_LSB_POS GENMASK(7, 3)
#define CTRL1_TODDR_FORCE_FINISH BIT(25)
#define CTRL1_SEL_SHIFT 28
@@ -76,12 +73,12 @@ static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream,
width = params_width(params);
regmap_update_bits(fifo->map, FIFO_CTRL0,
- CTRL0_TODDR_TYPE_MASK |
- CTRL0_TODDR_MSB_POS_MASK |
- CTRL0_TODDR_LSB_POS_MASK,
- CTRL0_TODDR_TYPE(type) |
- CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) |
- CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1)));
+ CTRL0_TODDR_TYPE |
+ CTRL0_TODDR_MSB_POS |
+ CTRL0_TODDR_LSB_POS,
+ FIELD_PREP(CTRL0_TODDR_TYPE, type) |
+ FIELD_PREP(CTRL0_TODDR_MSB_POS, TODDR_MSB_POS) |
+ FIELD_PREP(CTRL0_TODDR_LSB_POS, TODDR_MSB_POS - (width - 1)));
return 0;
}
--
2.34.1

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@ -0,0 +1,159 @@
From 793c581ca351bfa08e185c3625ede56cc4cabf3f Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Thu, 12 Jun 2025 10:30:51 +0000
Subject: [PATCH 34/37] WIP: dt-bindings: auxdisplay: add Titan Micro
Electronics TM16XX
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add documentation for auxiliary displays based on TM16XX and compatible
LED controllers.
Signed-off-by: Jean-François Lessard <jefflessard3@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../bindings/auxdisplay/tm16xx.yaml | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
create mode 100644 Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml
diff --git a/Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml b/Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml
new file mode 100644
index 000000000000..80b54572926c
--- /dev/null
+++ b/Documentation/devicetree/bindings/auxdisplay/tm16xx.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/auxdisplay/tm16xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TM16XX and Compatible Auxiliary Display Driver
+
+maintainers:
+ - Jean-François Lessard <jefflessard3@gmail.com>
+
+description: |
+ Bindings for auxiliary displays based on TM16XX and compatible LED controllers.
+
+properties:
+ compatible:
+ enum:
+ - titanmec,tm1618
+ - titanmec,tm1620
+ - titanmec,tm1628
+ - titanmec,tm1650
+ - fdhisi,fd620
+ - fdhisi,fd628
+ - fdhisi,fd650
+ - fdhisi,fd6551
+ - fdhisi,fd655
+ - princeton,pt6964
+ - hbs,hbs658
+
+ reg:
+ maxItems: 1
+
+ tm16xx,digits:
+ description: Array of grid indexes for each digit
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ items:
+ minimum: 0
+ maximum: 7
+ minItems: 1
+ maxItems: 8
+
+ tm16xx,segment-mapping:
+ description: Array specifying segment mapping (must be exactly 7 elements)
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ items:
+ minimum: 0
+ maximum: 7
+ minItems: 7
+ maxItems: 7
+
+ tm16xx,transposed:
+ description: |
+ Optional boolean flag indicating if the device output is transposed.
+ If not present, the default value is false.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^led@[0-7],[0-7]$":
+ $ref: /schemas/leds/common.yaml#
+ properties:
+ reg:
+ description: Grid and segment indexes
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - tm16xx,digits
+ - tm16xx,segment-mapping
+
+additionalProperties: true
+
+examples:
+ - |
+ display_client: i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@24 {
+ compatible = "titanmec,tm1650";
+ reg = <0x24>;
+ tm16xx,digits = /bits/ 8 <0 1 2 3>;
+ tm16xx,segment-mapping = /bits/ 8 <0 1 2 3 4 5 6>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ led@4,0 {
+ reg = <4 0>;
+ function = "lan";
+ };
+
+ led@4,1 {
+ reg = <4 1>;
+ function = "wlan";
+ };
+ };
+ };
+ - |
+ display_client: spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0 {
+ compatible = "titanmec,tm1628";
+ reg = <0>;
+ tm16xx,transposed;
+ tm16xx,digits = /bits/ 8 <1 2 3 4>;
+ tm16xx,segment-mapping = /bits/ 8 <0 1 2 3 4 5 6>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ led@0,2 {
+ reg = <0 2>;
+ function = "usb";
+ };
+
+ led@0,3 {
+ reg = <0 3>;
+ function = "power";
+ };
+ };
+ };
--
2.34.1

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@ -1,58 +0,0 @@
From 75a8df6a4644ae9399d277c164e591130ee1c776 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 20 Mar 2024 13:28:08 +0000
Subject: [PATCH 35/53] FROMLIST(v1): drm/panfrost: fix power transition
timeout warnings
Increase the timeout value to prevent system logs on Amlogic boards flooding
with power transition warnings:
[ 13.047638] panfrost ffe40000.gpu: shader power transition timeout
[ 13.048674] panfrost ffe40000.gpu: l2 power transition timeout
[ 13.937324] panfrost ffe40000.gpu: shader power transition timeout
[ 13.938351] panfrost ffe40000.gpu: l2 power transition timeout
...
[39829.506904] panfrost ffe40000.gpu: shader power transition timeout
[39829.507938] panfrost ffe40000.gpu: l2 power transition timeout
[39949.508369] panfrost ffe40000.gpu: shader power transition timeout
[39949.509405] panfrost ffe40000.gpu: l2 power transition timeout
The 2000 value has been found through trial and error testing on Amlogic boards
with G52 and G31 GPU's.
Fixes: 22aa1a209018 ("drm/panfrost: Really power off GPU cores in panfrost_gpu_power_off()")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
drivers/gpu/drm/panfrost/panfrost_gpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
index 9063ce254642..fd8e44992184 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
@@ -441,19 +441,19 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev)
gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present);
ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO,
- val, !val, 1, 1000);
+ val, !val, 1, 2000);
if (ret)
dev_err(pfdev->dev, "shader power transition timeout");
gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present);
ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO,
- val, !val, 1, 1000);
+ val, !val, 1, 2000);
if (ret)
dev_err(pfdev->dev, "tiler power transition timeout");
gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present);
ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO,
- val, !val, 0, 1000);
+ val, !val, 0, 2000);
if (ret)
dev_err(pfdev->dev, "l2 power transition timeout");
}
--
2.34.1

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@ -0,0 +1,100 @@
From 536382633e9e399907fe06f34f426184965b5ab1 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 11 Jun 2025 11:23:44 +0000
Subject: [PATCH 35/37] WIP: arm64: dts: meson-gxl-s905w-tx3-mini: support the
fd628 display
The TX3-mini has an FD628 display. Add support using the tm166xx
kernel driver and userspace tools [0].
[0] https://github.com/jefflessard/tm16xx-display
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
index 6705c2082a78..94cae3a59554 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts
@@ -10,6 +10,8 @@
#include "meson-gxl-s905x.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
/ {
compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl";
@@ -19,6 +21,67 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */
};
+
+ display_client: spi {
+ compatible = "spi-gpio";
+ sck-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio_ao 4 GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0 {
+ compatible = "fdhisi,fd628";
+ reg = <0x0>;
+ spi-3wire;
+ spi-lsb-first;
+ spi-rx-delay-us = <1>;
+ spi-max-frequency = <500000>;
+
+ tm16xx,digits = [03 02 01 00];
+ tm16xx,segment-mapping = [03 04 05 00 01 02 06];
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ led@4,0 {
+ reg = <4 0>;
+ function = LED_FUNCTION_ALARM;
+ };
+
+ led@4,1 {
+ reg = <4 1>;
+ function = LED_FUNCTION_USB;
+ };
+
+ led@4,2 {
+ reg = <4 2>;
+ function = "play";
+ };
+
+ led@4,3 {
+ reg = <4 3>;
+ function = "pause";
+ };
+
+ led@4,4 {
+ reg = <4 4>;
+ function = "colon";
+ };
+
+ led@4,5 {
+ reg = <4 5>;
+ function = LED_FUNCTION_LAN;
+ };
+
+ led@4,6 {
+ reg = <4 6>;
+ function = LED_FUNCTION_WLAN;
+ };
+ };
+ };
};
&ir {
--
2.34.1

View File

@ -1,66 +0,0 @@
From ff1b40e46c3498843e616b364e8f985b0146255f Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Sat, 23 Mar 2024 20:04:49 +0100
Subject: [PATCH 36/53] FROMLIST(v1): iio: adc: meson: fix voltage reference
selection field name typo
The field should be called "vref_voltage", without a typo in the word
voltage. No functional changes intended.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/meson_saradc.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 13b473d8c6c7..2615d74534df 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -327,7 +327,7 @@ struct meson_sar_adc_param {
u8 vref_select;
u8 cmv_select;
u8 adc_eoc;
- enum meson_sar_adc_vref_sel vref_volatge;
+ enum meson_sar_adc_vref_sel vref_voltage;
};
struct meson_sar_adc_data {
@@ -1001,7 +1001,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
}
regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,
- priv->param->vref_volatge);
+ priv->param->vref_voltage);
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
@@ -1225,7 +1225,7 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 10,
.has_reg11 = true,
- .vref_volatge = 1,
+ .vref_voltage = 1,
.cmv_select = 1,
};
@@ -1237,7 +1237,7 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_volatge = 1,
+ .vref_voltage = 1,
.cmv_select = 1,
};
@@ -1249,7 +1249,7 @@ static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_volatge = 1,
+ .vref_voltage = 1,
.has_vref_select = true,
.vref_select = VREF_VDDA,
.cmv_select = 1,
--
2.34.1

View File

@ -0,0 +1,99 @@
From 6bf5753f848d4c9e66d5e55929b307715ee1d5c5 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Thu, 9 Feb 2023 10:11:39 +0000
Subject: [PATCH 36/37] WIP: arm64: dts: meson-gxm-tx9-pro: support the fd628
display
The TX9-Pro has an FD628 display. Add support using the tm166xx
kernel driver and userspace tools [0].
[0] https://github.com/jefflessard/tm16xx-display
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../boot/dts/amlogic/meson-gxm-tx9-pro.dts | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts
index 9a62176cfe5a..08603b035868 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-tx9-pro.dts
@@ -9,6 +9,7 @@
#include "meson-gxm.dtsi"
#include "meson-gx-p23x-q20x.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
compatible = "oranth,tx9-pro", "amlogic,s912", "amlogic,meson-gxm";
@@ -37,6 +38,67 @@ button {
gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
};
};
+
+ display_client: spi {
+ compatible = "spi-gpio";
+ sck-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio 53 GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0 {
+ compatible = "fdhisi,fd628";
+ reg = <0x0>;
+ spi-3wire;
+ spi-lsb-first;
+ spi-rx-delay-us = <1>;
+ spi-max-frequency = <500000>;
+
+ tm16xx,digits = [00 01 02 03];
+ tm16xx,segment-mapping = [03 01 02 06 04 05 00];
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ led@4,0 {
+ reg = <4 0>;
+ function = LED_FUNCTION_ALARM;
+ };
+
+ led@4,1 {
+ reg = <4 1>;
+ function = LED_FUNCTION_USB;
+ };
+
+ led@4,2 {
+ reg = <4 2>;
+ function = "play";
+ };
+
+ led@4,3 {
+ reg = <4 3>;
+ function = "pause";
+ };
+
+ led@4,4 {
+ reg = <4 4>;
+ function = "colon";
+ };
+
+ led@4,5 {
+ reg = <4 5>;
+ function = LED_FUNCTION_LAN;
+ };
+
+ led@4,6 {
+ reg = <4 6>;
+ function = LED_FUNCTION_WLAN;
+ };
+ };
+ };
};
&ethmac {
--
2.34.1

View File

@ -1,142 +0,0 @@
From e75fe79643d8d1be19c91d195b9fa1cc16bfffa8 Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Sat, 23 Mar 2024 20:30:02 +0100
Subject: [PATCH 37/53] FROMLIST(v1): iio: adc: consistently use bool and enum
in struct meson_sar_adc_param
Consistently use bool for any register bit that enables/disables
functionality and enum for register values where there's a choice
between different settings. The aim is to make the code easier to read
and understand by being more consistent. No functional changes intended.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/meson_saradc.c | 47 +++++++++++++++++++---------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 2615d74534df..6b2af0c2bbc7 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -156,9 +156,9 @@
#define MESON_SAR_ADC_REG11 0x2c
#define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
#define MESON_SAR_ADC_REG11_CMV_SEL BIT(6)
- #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5)
- #define MESON_SAR_ADC_REG11_EOC BIT(1)
- #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)
+ #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5)
+ #define MESON_SAR_ADC_REG11_EOC BIT(1)
+ #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)
#define MESON_SAR_ADC_REG13 0x34
#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
@@ -224,6 +224,11 @@ enum meson_sar_adc_vref_sel {
VREF_VDDA = 1,
};
+enum meson_sar_adc_vref_voltage {
+ VREF_VOLTAGE_0V9 = 0,
+ VREF_VOLTAGE_1V8 = 1,
+};
+
enum meson_sar_adc_avg_mode {
NO_AVERAGING = 0x0,
MEAN_AVERAGING = 0x1,
@@ -321,13 +326,13 @@ struct meson_sar_adc_param {
u8 temperature_trimming_bits;
unsigned int temperature_multiplier;
unsigned int temperature_divider;
- u8 disable_ring_counter;
+ bool disable_ring_counter;
bool has_reg11;
bool has_vref_select;
- u8 vref_select;
- u8 cmv_select;
- u8 adc_eoc;
- enum meson_sar_adc_vref_sel vref_voltage;
+ bool cmv_select;
+ bool adc_eoc;
+ enum meson_sar_adc_vref_sel vref_select;
+ enum meson_sar_adc_vref_voltage vref_voltage;
};
struct meson_sar_adc_data {
@@ -982,14 +987,16 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
}
- regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
- priv->param->disable_ring_counter);
+ if (priv->param->disable_ring_counter)
+ regval = MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN;
+ else
+ regval = 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
regval);
if (priv->param->has_reg11) {
- regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);
+ regval = priv->param->adc_eoc ? MESON_SAR_ADC_REG11_EOC : 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_EOC, regval);
@@ -1005,8 +1012,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
- regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,
- priv->param->cmv_select);
+ regval = priv->param->cmv_select ? MESON_SAR_ADC_REG11_CMV_SEL : 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_CMV_SEL, regval);
}
@@ -1225,8 +1231,8 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 10,
.has_reg11 = true,
- .vref_voltage = 1,
- .cmv_select = 1,
+ .vref_voltage = VREF_VOLTAGE_1V8,
+ .cmv_select = true,
};
static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
@@ -1237,8 +1243,8 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_voltage = 1,
- .cmv_select = 1,
+ .vref_voltage = VREF_VOLTAGE_1V8,
+ .cmv_select = true,
};
static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
@@ -1249,10 +1255,10 @@ static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_voltage = 1,
+ .vref_voltage = VREF_VOLTAGE_1V8,
.has_vref_select = true,
.vref_select = VREF_VDDA,
- .cmv_select = 1,
+ .cmv_select = true,
};
static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
@@ -1263,7 +1269,8 @@ static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .adc_eoc = 1,
+ .vref_voltage = VREF_VOLTAGE_0V9,
+ .adc_eoc = true,
.has_vref_select = true,
.vref_select = VREF_VDDA,
};
--
2.34.1

View File

@ -0,0 +1,100 @@
From 7f3cc57dc50d31414a284761cfb5372942229571 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 11 Jun 2025 11:47:31 +0000
Subject: [PATCH 37/37] WIP: arm64: dts: meson-g12a-x96-max: support the fd628
display
The X96-Max has an FD628 display. Add support using the tm166xx
kernel driver and userspace tools [0].
[0] https://github.com/jefflessard/tm16xx-display
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../boot/dts/amlogic/meson-g12a-x96-max.dts | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
index 5ab460a3e637..879276d6f6e9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
@@ -7,6 +7,7 @@
#include "meson-g12a.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
@@ -54,6 +55,68 @@ hdmi_connector_in: endpoint {
};
};
+ display_client: spi {
+ compatible = "spi-gpio";
+ sck-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio_ao 10 GPIO_ACTIVE_LOW>;
+ num-chipselects = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ display@0 {
+ compatible = "fdhisi,fd628";
+ reg = <0x0>;
+ spi-3wire;
+ spi-lsb-first;
+ spi-rx-delay-us = <1>;
+ spi-max-frequency = <500000>;
+
+ tm16xx,transposed;
+ tm16xx,digits = [00 01 02 03];
+ tm16xx,segment-mapping = [00 01 02 03 04 05 06];
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ led@4,0 {
+ reg = <4 0>;
+ function = "apps";
+ };
+
+ led@4,1 {
+ reg = <4 1>;
+ function = "setup";
+ };
+
+ led@4,2 {
+ reg = <4 2>;
+ function = LED_FUNCTION_USB;
+ };
+
+ led@4,3 {
+ reg = <4 3>;
+ function = LED_FUNCTION_SD;
+ };
+
+ led@4,4 {
+ reg = <4 4>;
+ function = "colon";
+ };
+
+ led@4,5 {
+ reg = <4 5>;
+ function = "hdmi";
+ };
+
+ led@4,6 {
+ reg = <4 6>;
+ function = "video";
+ };
+ };
+ };
+
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
--
2.34.1

View File

@ -1,135 +0,0 @@
From c6a0829ea93c2460d1fcc79eb59f9704832a073c Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Sat, 23 Mar 2024 20:35:58 +0100
Subject: [PATCH 38/53] FROMLIST(v1): iio: adc: meson: simplify
MESON_SAR_ADC_REG11 register access
Simply check the max_register value to decide whether
MESON_SAR_ADC_REG11 is present on the current IP revision. This allows
dropping two additional bool fields from struct meson_sar_adc_param
which previously had to be manually kept in sync. No functional changes
intended.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/meson_saradc.c | 29 ++++++++---------------------
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 6b2af0c2bbc7..8c1e542c0ab7 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -320,14 +320,12 @@ static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
struct meson_sar_adc_param {
bool has_bl30_integration;
unsigned long clock_rate;
- u32 bandgap_reg;
unsigned int resolution;
const struct regmap_config *regmap_config;
u8 temperature_trimming_bits;
unsigned int temperature_multiplier;
unsigned int temperature_divider;
bool disable_ring_counter;
- bool has_reg11;
bool has_vref_select;
bool cmv_select;
bool adc_eoc;
@@ -995,7 +993,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
regval);
- if (priv->param->has_reg11) {
+ if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) {
regval = priv->param->adc_eoc ? MESON_SAR_ADC_REG11_EOC : 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_EOC, regval);
@@ -1031,16 +1029,15 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
- const struct meson_sar_adc_param *param = priv->param;
- u32 enable_mask;
- if (param->bandgap_reg == MESON_SAR_ADC_REG11)
- enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
+ if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11)
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN,
+ on_off ? MESON_SAR_ADC_REG11_BANDGAP_EN : 0);
else
- enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
-
- regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
- on_off ? enable_mask : 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
+ MESON_SAR_ADC_DELTA_10_TS_VBG_EN,
+ on_off ? MESON_SAR_ADC_DELTA_10_TS_VBG_EN : 0);
}
static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
@@ -1205,7 +1202,6 @@ static const struct iio_info meson_sar_adc_iio_info = {
static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
.has_bl30_integration = false,
.clock_rate = 1150000,
- .bandgap_reg = MESON_SAR_ADC_DELTA_10,
.regmap_config = &meson_sar_adc_regmap_config_meson8,
.resolution = 10,
.temperature_trimming_bits = 4,
@@ -1216,7 +1212,6 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
.has_bl30_integration = false,
.clock_rate = 1150000,
- .bandgap_reg = MESON_SAR_ADC_DELTA_10,
.regmap_config = &meson_sar_adc_regmap_config_meson8,
.resolution = 10,
.temperature_trimming_bits = 5,
@@ -1227,10 +1222,8 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
.has_bl30_integration = true,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 10,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_1V8,
.cmv_select = true,
};
@@ -1238,11 +1231,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
.has_bl30_integration = true,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 12,
.disable_ring_counter = 1,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_1V8,
.cmv_select = true,
};
@@ -1250,11 +1241,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
.has_bl30_integration = true,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 12,
.disable_ring_counter = 1,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_1V8,
.has_vref_select = true,
.vref_select = VREF_VDDA,
@@ -1264,11 +1253,9 @@ static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
.has_bl30_integration = false,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 12,
.disable_ring_counter = 1,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_0V9,
.adc_eoc = true,
.has_vref_select = true,
--
2.34.1

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@ -1,30 +0,0 @@
From 8d6f4eb8a8a7bd35dd10bb4d942b0e3182042ac1 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 5 Apr 2021 13:48:34 +0000
Subject: [PATCH 39/53] WIP: dt-bindings: arm: amlogic: add support for
Dreambox One/Two
The Dreambox One and Dreambox Two are DVBS/T2 receiver boxes based
on the Amlogic W400 reference board with an S922X chip.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index caab7ceeda45..922380d6139e 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -175,6 +175,8 @@ properties:
- azw,gtking
- azw,gtking-pro
- bananapi,bpi-m2s
+ - dream,dreambox-one
+ - dream,dreambox-two
- hardkernel,odroid-go-ultra
- hardkernel,odroid-n2
- hardkernel,odroid-n2l
--
2.34.1

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@ -1,272 +0,0 @@
From ffbb462ad7261792d8642717b1d17407afe81d94 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 5 Apr 2021 13:51:20 +0000
Subject: [PATCH 40/53] WIP: arm64: dts: meson: add initial device-trees for
Dreambox One/Two
Dreambox One and Dreambox Two are based on the Amlogic W400 reference
board with an S922X chip and the following specs:
- 2GB DDR3 RAM
- 16GB eMMC
- 10/100/1000 Base-T Ethernet
- AP6356 Wireless (802.11 b/g/n/ac, BT 5.0)
- HDMI 2.1 video
- S/PDIF optical output
- 2x DVB-S2/T2
- Smartcard Reader Slot
- 2x USB 2.0 port (1x micro-USB for service)
- 1x USB 3.0 port
- IR receiver
- 1x Power LED (blue)
- 1x Power button (top)
- 1x Update/Reset button (underside)
- 1x micro SD card slot
Dreambox Two differences:
- 3" Colour LCD display (MIPI-DSI)
- Common Interface Slot
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 2 +
.../dts/amlogic/meson-g12b-dreambox-one.dts | 17 ++
.../dts/amlogic/meson-g12b-dreambox-two.dts | 20 +++
.../boot/dts/amlogic/meson-g12b-dreambox.dtsi | 160 ++++++++++++++++++
4 files changed, 199 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index cc8b34bd583d..edb22c57f11d 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -15,6 +15,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-bananapi-m2s.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-cm4io.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-dreambox-one.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12b-dreambox-two.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts
new file mode 100644
index 000000000000..ecfa1c683dde
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-one.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-dreambox.dtsi"
+
+/ {
+ compatible = "dream,dreambox-one", "amlogic,s922x", "amlogic,g12b";
+ model = "Dreambox One";
+};
+
+&sd_emmc_a {
+ sd-uhs-sdr12;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts
new file mode 100644
index 000000000000..df0d71983c3d
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox-two.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-g12b-dreambox.dtsi"
+
+/ {
+ compatible = "dream,dreambox-two", "amlogic,s922x", "amlogic,g12b";
+ model = "Dreambox Two";
+};
+
+&sd_emmc_a {
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi
new file mode 100644
index 000000000000..a76045fd739c
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+#include "meson-g12b-w400.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ cvbs-connector {
+ status = "disabled";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOA_11 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ spdif_dit: audio-codec-1 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "DREAMBOX";
+ audio-aux-devs = <&tdmout_b>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "SPDIFOUT_A IN 0", "FRDDR_A OUT 3",
+ "SPDIFOUT_A IN 1", "FRDDR_B OUT 3",
+ "SPDIFOUT_A IN 2", "FRDDR_C OUT 3";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-3 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+ };
+
+ /* spdif hdmi or toslink interface */
+ dai-link-4 {
+ sound-dai = <&spdifout_a>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+
+ codec-1 {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
+ };
+ };
+
+ /* spdif hdmi interface */
+ dai-link-5 {
+ sound-dai = <&spdifout_b>;
+
+ codec {
+ sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-6 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+ };
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&ir {
+ linux,rc-map-name = "rc-dreambox";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+&spdifout_a {
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spdifout_b {
+ status = "okay";
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
--
2.34.1

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@ -1,36 +0,0 @@
From 2fa9dc2253ed3266db28b0a3ebb5d942427ef7a9 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 1 Jan 2024 06:15:40 +0000
Subject: [PATCH 41/53] WIP: arm64: dts: meson: increase SD speeds on Minix Neo
U9-H
Lets see what happens/breaks when all the fancy modes are added
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
index b929682805dd..c3fb523fd18e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
@@ -106,6 +106,15 @@ brcmf: wifi@1 {
};
};
+&sd_emmc_b {
+ /* experimental */
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ max-frequency = <200000000>;
+};
+
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
--
2.34.1

View File

@ -1,33 +0,0 @@
From 6302dc4b0ec1ce8d343ca620f1fc82e8fa5e1dda Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Fri, 5 Jan 2024 03:07:58 +0000
Subject: [PATCH 42/53] WIP: arm64: dts: meson: fixup Minix U9-H wifi
I think the 'drop compatible' change conflicted so remove this too.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
index c3fb523fd18e..bed70c5c2d9c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts
@@ -99,13 +99,6 @@ rtc: rtc@51 {
};
};
-&sd_emmc_a {
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
&sd_emmc_b {
/* experimental */
sd-uhs-sdr12;
--
2.34.1

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@ -1,126 +0,0 @@
From e77b259c064cd7b8c672c96834fdb1c4d2a98ff4 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 3 Jan 2024 03:14:06 +0000
Subject: [PATCH 46/53] WIP: arm64: dts: meson: drop broadcom compatible from
reference board SDIO nodes
Remove the Broadcom compatible to allow Android STB boards using Qualcom QCA9377
and Realtek RTL8189ES/FS SDIO modules to also have working WiFi when booting with
the reference board device-tree(s). Also do the same to the Vega S95 dtsi as this
is commonly used in the same way.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 3 +--
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 3 +--
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 3 +--
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts | 3 +--
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi | 3 +--
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 3 +--
arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts | 3 +--
7 files changed, 7 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 52d57773a77f..1736bd2e96e2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -178,9 +178,8 @@ &sd_emmc_a {
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
- brcmf: wifi@1 {
+ sdio: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm4329-fmac";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 255e93a0b36d..b5e8b1cbafa9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -251,9 +251,8 @@ &sd_emmc_a {
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
- brcmf: wifi@1 {
+ sdio: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm4329-fmac";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index c1470416faad..7dffeb5931c9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -102,8 +102,7 @@ hdmi_tx_tmds_out: endpoint {
};
&sd_emmc_a {
- brcmf: wifi@1 {
+ sdio: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm4329-fmac";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
index 92c425d0259c..ff9145d49090 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
@@ -21,8 +21,7 @@ &ethmac {
};
&sd_emmc_a {
- brcmf: wifi@1 {
+ sdio: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm4329-fmac";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index b83b38b2d9e1..c74308499786 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -138,9 +138,8 @@ &sd_emmc_a {
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
- brcmf: wifi@1 {
+ sdio: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm4329-fmac";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index d4858afa0e9c..feb31207773f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -72,8 +72,7 @@ external_phy: ethernet-phy@0 {
};
&sd_emmc_a {
- brcmf: wifi@1 {
+ sdio: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm4329-fmac";
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
index d02b80d77378..6c8bec1853ac 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
@@ -21,8 +21,7 @@ &ethmac {
};
&sd_emmc_a {
- brcmf: wifi@1 {
+ sdio: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm4329-fmac";
};
};
--
2.34.1

View File

@ -1,27 +0,0 @@
From 642e23b3f8a96c89390eb0ff05a6e46e63f9a98f Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 19 Jan 2022 02:40:20 +0000
Subject: [PATCH 47/53] WIP: dt-bindings: arm: amlogic: add OSMC Vero 4K
Add support for the OSMC Vero 4K
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 922380d6139e..73598f7992fd 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -99,6 +99,7 @@ properties:
- libretech,aml-s905x-cc
- libretech,aml-s905x-cc-v2
- nexbox,a95x
+ - osmc,vero4k
- const: amlogic,s905x
- const: amlogic,meson-gxl
--
2.34.1

View File

@ -1,259 +0,0 @@
From e4062d9479c72b37e7093a424f969829018d5a48 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Wed, 19 Jan 2022 04:06:17 +0000
Subject: [PATCH 48/53] WIP: arm64: dts: meson: add support for OSMC Vero 4K
The OSMC Vero 4K device is based on the Amlogic S905X (P212) reference
design with the following specifications:
- 2GB DDR4 RAM
- 16GB eMMC
- HDMI 2.1 video
- S/PDIF optical output
- AV output
- 10/100 Ethernet
- AP6255 Wireless (802.11 a/b/g/n/ac, BT 4.2)
- 2x USB 2.0 ports (1x OTG)
- IR receiver (internal)
- IR extender port (external)
- 1x micro SD card slot
- 1x Power LED (red)
- 1x Reset button (in AV jack)
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
arch/arm64/boot/dts/amlogic/Makefile | 8 +
.../dts/amlogic/meson-gxl-s905x-vero4k.dts | 202 ++++++++++++++++++
2 files changed, 210 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index edb22c57f11d..936cd1989463 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -49,6 +49,14 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905l-p271.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-vero4k.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts
new file mode 100644
index 000000000000..a2be35d63c96
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x-p212.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/meson-aiu.h>
+
+/ {
+ compatible = "osmc,vero4k", "amlogic,s905x", "amlogic,meson-gxl";
+ model = "OSMC Vero 4K";
+
+ reserved-memory {
+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
+ secmon_reserved_bl32: secmon@5300000 {
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <20>;
+
+ button@0 {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-standby {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ panic-indicator;
+ };
+ };
+
+ dio2133: analog-amplifier {
+ compatible = "simple-audio-amplifier";
+ sound-name-prefix = "AU2";
+ VCC-supply = <&hdmi_5v>;
+ enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
+ };
+
+ spdif_dit: audio-codec-0 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ sound-name-prefix = "DIT";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "amlogic,gx-sound-card";
+ model = "VERO4K";
+ audio-aux-devs = <&dio2133>;
+ audio-widgets = "Line", "Lineout";
+ audio-routing = "AU2 INL", "ACODEC LOLP",
+ "AU2 INR", "ACODEC LORP",
+ "AU2 INL", "ACODEC LOLN",
+ "AU2 INR", "ACODEC LORN",
+ "Lineout", "AU2 OUTL",
+ "Lineout", "AU2 OUTR";
+ assigned-clocks = <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>,
+ <&clkc CLKID_MPLL2>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
+ dai-format = "i2s";
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
+ };
+
+ codec-1 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
+ };
+ };
+
+ dai-link-3 {
+ sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
+
+ codec-0 {
+ sound-dai = <&spdif_dit>;
+ };
+ };
+
+ dai-link-4 {
+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ dai-link-5 {
+ sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
+
+ codec-0 {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddio_ao18>;
+ status = "okay";
+};
+
+&aiu {
+ status = "okay";
+ pinctrl-0 = <&spdif_out_h_pins>;
+ pinctrl-names = "default";
+};
+
+&cec_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_cec_pins>;
+ pinctrl-names = "default";
+ hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ethmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&hdmi_5v>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&internal_phy {
+ pinctrl-0 = <&eth_link_led_pins>, <&eth_act_led_pins>;
+ pinctrl-names = "default";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+};
--
2.34.1

View File

@ -1,36 +0,0 @@
From 1d5c42d5f84a1b022365b4ae00c3c6325a4b8f16 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 1 Jan 2024 07:13:19 +0000
Subject: [PATCH 49/53] WIP: dt-bindings: arm: amlogic: add S905L and p271
reference board
Add bindings for the Amlogic S905L SoC and reference design board. S905L is similar
to P281 (S905W) and derived from P212 (S905X) but with silicon differences to omit
VP9 codec support and using a Mali 450-MP2 (not MP3).
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
index 73598f7992fd..515d58587f7c 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
@@ -81,6 +81,13 @@ properties:
- const: amlogic,s805x
- const: amlogic,meson-gxl
+ - description: Boards with the Amlogic Meson GXL S905L SoC
+ items:
+ - enum:
+ - amlogic,p271
+ - const: amlogic,s905l
+ - const: amlogic,meson-gxl
+
- description: Boards with the Amlogic Meson GXL S905W SoC
items:
- enum:
--
2.34.1

View File

@ -1,29 +0,0 @@
From f5ab209b7240f1251e100f9e7919f165bdb26f96 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 1 Jan 2024 07:48:39 +0000
Subject: [PATCH 50/53] WIP: soc: amlogic: meson-gx-socinfo: Add S905L ID
Add the S905L SoC id observed in several P271 boards:
LibreELEC kernel: soc soc0: Amlogic Meson GXLX (S905L) Revision 26:a (c1:2) Detected
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
drivers/soc/amlogic/meson-gx-socinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c
index 6abb730344ab..7e255acf5430 100644
--- a/drivers/soc/amlogic/meson-gx-socinfo.c
+++ b/drivers/soc/amlogic/meson-gx-socinfo.c
@@ -64,6 +64,7 @@ static const struct meson_gx_package_id {
{ "962E", 0x24, 0x20, 0xf0 },
{ "A113X", 0x25, 0x37, 0xff },
{ "A113D", 0x25, 0x22, 0xff },
+ { "S905L", 0x26, 0, 0x0 },
{ "S905D2", 0x28, 0x10, 0xf0 },
{ "S905Y2", 0x28, 0x30, 0xf0 },
{ "S905X2", 0x28, 0x40, 0xf0 },
--
2.34.1

View File

@ -1,30 +0,0 @@
From b2cbf810a3310389b2691797e487396aa1f621da Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Sat, 23 Mar 2024 20:38:59 +0100
Subject: [PATCH 51/53] WIP: dt-bindings: iio: adc: amlogic,meson-saradc: Add
GXLX SoC compatible
Add a compatible string for the GXLX SoC. It's very similar to GXL but
has three additional bits in MESON_SAR_ADC_REG12 for the three MPLL
clocks.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
.../devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
index 7e8328e9ce13..b2fef72267b4 100644
--- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -23,6 +23,7 @@ properties:
- amlogic,meson8m2-saradc
- amlogic,meson-gxbb-saradc
- amlogic,meson-gxl-saradc
+ - amlogic,meson-gxlx-saradc
- amlogic,meson-gxm-saradc
- amlogic,meson-axg-saradc
- amlogic,meson-g12a-saradc
--
2.34.1

View File

@ -1,97 +0,0 @@
From a3fe76499d3b186e1b964cc24fe49afc0c12eca7 Mon Sep 17 00:00:00 2001
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date: Sat, 23 Mar 2024 20:44:41 +0100
Subject: [PATCH 52/53] WIP: iio: adc: meson: add support for the GXLX SoC
The SARADC IP on the GXLX SoC itself is identical to the one found on
GXL SoCs. However, GXLX SoCs require poking the first three bits in the
MESON_SAR_ADC_REG12 register to get the three MPLL clocks (used as clock
generators for the audio frequencies) to work.
WiP: the purpose of these three bits needs to be clarified
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/meson_saradc.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 8c1e542c0ab7..6ad1a6f33f7d 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -160,6 +160,11 @@
#define MESON_SAR_ADC_REG11_EOC BIT(1)
#define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)
+#define MESON_SAR_ADC_REG12 0x30
+ #define MESON_SAR_ADC_REG12_MPLL0_UNKNOWN BIT(0)
+ #define MESON_SAR_ADC_REG12_MPLL1_UNKNOWN BIT(1)
+ #define MESON_SAR_ADC_REG12_MPLL2_UNKNOWN BIT(2)
+
#define MESON_SAR_ADC_REG13 0x34
#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
@@ -329,6 +334,7 @@ struct meson_sar_adc_param {
bool has_vref_select;
bool cmv_select;
bool adc_eoc;
+ bool mpll_clock_bits;
enum meson_sar_adc_vref_sel vref_select;
enum meson_sar_adc_vref_voltage vref_voltage;
};
@@ -1013,6 +1019,12 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
regval = priv->param->cmv_select ? MESON_SAR_ADC_REG11_CMV_SEL : 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_CMV_SEL, regval);
+
+ if (priv->param->mpll_clock_bits)
+ regmap_write(priv->regmap, MESON_SAR_ADC_REG12,
+ MESON_SAR_ADC_REG12_MPLL0_UNKNOWN |
+ MESON_SAR_ADC_REG12_MPLL1_UNKNOWN |
+ MESON_SAR_ADC_REG12_MPLL2_UNKNOWN);
}
ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
@@ -1238,6 +1250,17 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
.cmv_select = true,
};
+static const struct meson_sar_adc_param meson_sar_adc_gxlx_param = {
+ .has_bl30_integration = true,
+ .clock_rate = 1200000,
+ .regmap_config = &meson_sar_adc_regmap_config_gxbb,
+ .resolution = 12,
+ .disable_ring_counter = 1,
+ .vref_voltage = VREF_VOLTAGE_1V8,
+ .cmv_select = true,
+ .mpll_clock_bits = true,
+};
+
static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
.has_bl30_integration = true,
.clock_rate = 1200000,
@@ -1287,6 +1310,11 @@ static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
.name = "meson-gxl-saradc",
};
+static const struct meson_sar_adc_data meson_sar_adc_gxlx_data = {
+ .param = &meson_sar_adc_gxlx_param,
+ .name = "meson-gxlx-saradc",
+};
+
static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
.param = &meson_sar_adc_gxl_param,
.name = "meson-gxm-saradc",
@@ -1318,6 +1346,9 @@ static const struct of_device_id meson_sar_adc_of_match[] = {
}, {
.compatible = "amlogic,meson-gxl-saradc",
.data = &meson_sar_adc_gxl_data,
+ }, {
+ .compatible = "amlogic,meson-gxlx-saradc",
+ .data = &meson_sar_adc_gxlx_data,
}, {
.compatible = "amlogic,meson-gxm-saradc",
.data = &meson_sar_adc_gxm_data,
--
2.34.1

View File

@ -1,73 +0,0 @@
From 75671e34bec14c140e4e81ae742de16b2a29d174 Mon Sep 17 00:00:00 2001
From: Christian Hewitt <christianshewitt@gmail.com>
Date: Mon, 1 Jan 2024 07:40:15 +0000
Subject: [PATCH 53/53] WIP: arm64: dts: meson: add p271 support
Add a device-tree for the Amlogic P271 (S905L) reference design board. This is
similar to the P212 (S905X) but with silicon differences to omit the VP9 codec
and use Mali 450-MP2 not MP3. The SoC is marked with S905L and a "2" (believed
to denote the MP2) and is sometimes wrongly described on some distributor stock
lists (and box vendor marketing) as an S905L2 chip.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
.../boot/dts/amlogic/meson-gxl-s905l-p271.dts | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts
new file mode 100644
index 000000000000..a902e4af7c15
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905l-p271.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Christian Hewitt <christianshewitt@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "meson-gxl-s905x.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+
+/ {
+ compatible = "amlogic,p271", "amlogic,s905l", "amlogic,meson-gxl";
+ model = "Amlogic Meson GXLX (S905L) P271 Development Board";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ sound {
+ model = "P271";
+ };
+};
+
+&apb {
+ mali: gpu@c0000 {
+ /* Mali 450-MP2 */
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1";
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-gxlx-saradc", "amlogic,meson-saradc";
+};
+
+&usb {
+ dr_mode = "host";
+};
--
2.34.1

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