Update RPI firmware (#537)

* VirtIO MMIO kernel module

* Update kernel.config

* Update kernel.config

.github/release-drafter.yml

@@ -0,0 +1,17 @@
+categories:
+  - title: 'HassOS Core'
+    label: 'os'
+  - title: 'Build'
+    label: 'build'
+  - title: 'Raspberry Pi'
+    label: 'board/raspberrypi'
+  - title: 'Open Virtual Appliance'
+    label: 'board/ova'
+  - title: 'Intel-Nuc'
+    label: 'board/intel-nuc'
+  - title: 'Hardkernel'
+    label: 'board/hardkernel'
+template: |
+  ## Changes
+
+  $CHANGES

.github/stale.yml

@@ -0,0 +1,17 @@
+# Number of days of inactivity before an issue becomes stale
+daysUntilStale: 60
+# Number of days of inactivity before a stale issue is closed
+daysUntilClose: 7
+# Issues with these labels will never be considered stale
+exemptLabels:
+  - pinned
+  - security
+# Label to use when marking an issue as stale
+staleLabel: wontfix
+# Comment to post when marking an issue as stale. Set to `false` to disable
+markComment: >
+  This issue has been automatically marked as stale because it has not had
+  recent activity. It will be closed if no further activity occurs. Thank you
+  for your contributions.
+# Comment to post when closing a stale issue. Set to `false` to disable
+closeComment: false

.hadolint.yaml

@@ -0,0 +1,2 @@
+ignored:
+  - DL3008

.travis.yml

@@ -1,25 +0,0 @@
-language: bash
-
-sudo: required
-service: docker
-
-addons:
-  apt:
-    packages:
-     - docker-ce
-
-before_install:
-  - shopt -s globstar
-  - docker pull koalaman/shellcheck
-
-script:
- - docker run -v $(pwd):/mnt koalaman/shellcheck scripts/*.sh
- - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/scripts/*.sh
- - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/scripts/*.sh
- - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/board/**/*.sh
- - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/rootfs-overlay/usr/sbin/*
- - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/rootfs-overlay/usr/libexec/*
- - docker run -v $(pwd):/mnt koalaman/shellcheck buildroot-external/rootfs-overlay/usr/lib/rauc/*
-
-matrix:
-  fast_finish: true

Dockerfile

@@ -1,20 +1,24 @@
 FROM ubuntu:18.04
 
+# Set shell
+SHELL ["/bin/bash", "-o", "pipefail", "-c"]
+
 # Docker
-RUN apt-get update && apt-get install -y \
+RUN apt-get update && apt-get install -y --no-install-recommends \
         apt-transport-https \
         ca-certificates \
         curl \
+        gpg-agent \
         software-properties-common \
-    && rm -rf /var/lib/apt/lists/* \
     && curl -fsSL https://download.docker.com/linux/ubuntu/gpg | apt-key add - \
     && add-apt-repository "deb https://download.docker.com/linux/ubuntu $(lsb_release -cs) stable" \
-    && apt-get update && apt-get install -y docker-ce \
+    && apt-get update && apt-get install -y --no-install-recommends \
+        docker-ce \
     && rm -rf /var/lib/apt/lists/*
 
 # Build Tools
-RUN apt-get update && apt-get install -y \
-        wget patch vim cpio python unzip rsync bc bzip2 ncurses-dev \
+RUN apt-get update && apt-get install -y --no-install-recommends \
+        wget patch vim cpio python unzip rsync bc bzip2 ncurses-dev sudo \
         git make g++ file perl bash binutils locales qemu-utils bison flex \
     && rm -rf /var/lib/apt/lists/*
 

Documentation/boards/odroid-xu4.md

@@ -0,0 +1,27 @@
+# Odroid-XU4
+
+## eMMC
+
+The Odroid XU4 has a hidden boot sector that is only visible on the Odroid itself (can't be written by a card reader). There are a couple possibilities:
+1) If the eMMC already had a working image before flashing HassOS:
+* It will be booting to uBoot (but no further). 
+    * If you have the serial adapter, you should be able to enter `distro_bootcmd` at the uboot prompt to continue booting.
+    * If not, flash the HassOS image to an SD card and boot off that temporarily (while the eMMC is also plugged in).
+* Once booted, login at the prompts and then enter `dd if=/dev/mmcblk0 of=/dev/mmcblk0boot0 bs=512 skip=63 seek=62 count=1440` at the linux prompt.
+* Reboot with eMMC (don't forget to flip the boot switch to eMMC)
+2) Clean/wiped/corruped boot sector:
+* You'll need to follow [Hardkernel's instructions](https://forum.odroid.com/viewtopic.php?f=53&t=6173) to get a working boot sector. Then flash HassOS and follow instructions above.
+* Alternatively, you can try flash HassOS to both an SD and eMMC, then boot off the SD with the eMMC also plugged in, then run `dd if=/dev/mmcblk1 of=/dev/mmcblk0boot0 bs=512 skip=1 seek=0 count=16381` at the Linux prompt. Note that this is untested, but in theory should work..
+
+If you are getting permissions issues when using the dd command, try disabling RO:
+`echo 0 > /sys/block/mmcblk0boot0/force_ro`
+to re-enable after running dd:
+`echo 1 > /sys/block/mmcblk0boot0/force_ro`
+## Console
+
+By default, console access is granted over the serial header and over HDMI. Certain startup messages will only appear on the serial console by default. To show the messages on the HDMI console instead, swap the order of the two consoles in the `cmdline.txt` file on the boot partition. You can also delete the SAC2 console if you don't plan on using the serial adapter.
+eg. `console=tty1 console=ttySAC2,115200`
+
+## GPIO
+
+Refer to [the odroid wiki](https://wiki.odroid.com/odroid-xu4/hardware/expansion_connectors).

Documentation/boards/orangepi.md

@@ -1,20 +0,0 @@
-# Raspberry PI
-
-Supported Hardware:
-
-| Device | Board | 
-|--------|-----------|
-| Orange Pi Prime | opi-prime |
-
-## Serial console
-
-The serial port on the Orange Pi Prime is a 3 pin header located between the
-power and reset buttons. The pins are labelled away from the board edge. Flow
-control must be disabled in order to send data. The serial specs are 3.3V TTL,
-115200,8,n,1
-
-## I2C
-
-Add `dtparam=i2c0=on` to `cmdline.txt`
-
-[config]: ../configuration.md#automatic

Documentation/boards/ova.md

@@ -1,16 +1,18 @@
-# OVA
+# Virtual Machine
+
+Using this VMDK in a virtual machine requires the following:
+
+- Operating system: Other 4.x or later Linux (64-bit)
+- Enabled support for UEFI boot
+- SATA disk controller
+- Minimal of 1GB RAM
+- At least 2x vCPU
+- An assigned network
+
+# OVA (Open Virtual Appliance)
+
+Currently, we only publish a VMDK virtual disk, due to issues with our previous OVA distribution. We are currently investigating our options to bring back the OVA distribution. However, the VMDK works on the following hypervisors:
 
-OVA stands for Open Virtual Appliance. Currently we had remove the ova files and publish a vmdk virtual disk,
-until we have better OVF template to generate our OVA. This VMDK work with (maybe you need convert the disk):
 - HyperV
 - VirtualBox
-- VMware
-
-## Virtual Machine
-
-You can use this vmdk in a virtual machine with follow requirements:
-- OS: Linux 64bit
-- UEFI boot
-- min. 1GB RAM
-- 2x vcpu
-- 1x Network
+- VMware

Documentation/boards/raspberrypi.md

@@ -2,13 +2,14 @@
 
 Supported Hardware:
 
-| Device | Board | 
+| Device | Board |
 |--------|-----------|
 | Raspberry Pi A+/B/B+| rpi |
 | Raspberry Pi Zero | rpi |
 | Raspberry Pi Zero W | rpi0-w |
 | Raspberry Pi 2 B | rpi2 |
 | Raspberry Pi 3 B/B+ | rpi3 / rpi3-64 |
+| Raspberry Pi 4 B | rpi4 / rpi4-64 |
 
 ## Limitation 64bit
 
@@ -20,7 +21,7 @@ For access to terminal over serial console, add `console=ttyAMA0,115200` to `cmd
 
 ## I2C
 
-Add `dtparam=i2c1=on` and `dtparam=i2c_arm=on` to `config.txt`. After that we create a module file on host with [config usb stick][config] or direct into `/etc/modules-load.d`. 
+Add `dtparam=i2c1=on` and `dtparam=i2c_arm=on` to `config.txt`. After that we create a module file on host with [config usb stick][config] or direct into `/etc/modules-load.d`.
 
 rpi-i2c.conf:
 ```
@@ -28,6 +29,19 @@ i2c-dev
 i2c-bcm2708
 ```
 
+## USB Boot
+
+USB mass storage boot is available on Raspberry Pi 3B, 3B+, 3A+, and 2B v1.2.
+To enable USB boot, add `program_usb_boot_mode=1` into `config.txt`. Note that this **permanently** alters the one-time programmable memory of the device.
+
+For more information see [RaspberryPi](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/msd.md).
+
+### Caveats
+
+* All bootable SD cards must be removed.
+* Boot time can be significantly longer with USB. This is due to the boot process first attempting to boot from SD card, failing, and resorting to USB.
+* Many USB drives simply do not work for boot. This is likely due to minimal driver support in uboot and will not be fixed. If you can't get it to boot on one drive, try a different brand/model. SanDisk Cruzer drives seem to have a higher rate of issues.
+
 ## Tweaks
 
 If you don't need bluetooth, disabled it with add `dtoverlay=pi3-disable-bt` into `config.txt`.

Documentation/boards/tinker.md

@@ -7,11 +7,11 @@ Supported Hardware:
 | Tinker RK3288 | tinker |
 | Tinker S RK3288 | tinker |
 
-## EMMC
+## eMMC
 
-Actual we support only SD cards. The support for EMMC will follow.
+eMMC support is provided transparently. Just flash the image to the eMMC by connecting your Tinker Board S to your PC via Micro-USB.
 
 ## Serial console
 
-For access to terminal over serial console, add `console=ttyS2,115200` to `cmdline.txt`. GPIO pins are: 34 = GND / 32 = UART TXD / 33 = UART RXD.
+To access the terminal over serial console, add `console=ttyS2,115200` to `cmdline.txt`. GPIO pins are: 34 = GND / 32 = UART TXD / 33 = UART RXD.
 

Documentation/configuration.md

@@ -8,18 +8,20 @@ Format a USB stick with FAT32/EXT4/NTFS and name it `CONFIG`. Alternative you ca
 ```text
 network/
 modules/
+modprobe/
 udev/
 authorized_keys
 timesyncd.conf
 hassos-xy.raucb
 ```
 
-- The `network` folder can contain any kind of NetworkManager connection files. For more information see [Network][network.md]. 
+- The `network` folder can contain any kind of NetworkManager connection files. For more information see [Network][network.md].
 - The `modules` folder is for modules-load configuration files.
+- The `modprobe` folder is for modules configuration files (/etc/modprobe.d)
 - The `udev` folder is for udev rules files.
 - The `authorized_keys` file activates debug SSH access on port `22222`. See [Debugging Hassio][debug-hassio].
 - The `timesyncd.conf` file allow you to set different NTP servers. HassOS won't boot without correct working time servers!
-- The `hassos-*.raucb` file is a firmware OTA update which will be installed. These can be found on on the [release][hassos-release] page. 
+- The `hassos-*.raucb` file is a firmware OTA update which will be installed. These can be found on on the [release][hassos-release] page.
 
 You can put this USB stick into the device and it will be read on startup. You can also trigger this process later over the
 API/UI or by calling `systemctl restart hassos-config` on the host.
@@ -32,7 +34,7 @@ You can edit or create a `cmdline.txt` in your boot partition. That will be read
 
 ### Kernel-Module
 
-The kernel module folder `/etc/modules-load.d` is persistent and you can add your configuration files there. See [Systemd modules load][systemd-modules].
+The kernel module folder `/etc/modules-load.d` is persistent and you can add your configuration files there. See [Systemd modules load][systemd-modules]. You can add the modules configuration files in `/etc/modprobe.d` that is also persistent.
 
 ### Udev rules
 

Documentation/kernel.md

@@ -3,10 +3,9 @@
 
 | Board | Version |
 |-------|---------|
-| Open Virtual Applicance | 4.14.82 |
-| Raspberry Pi | 4.14.81 |
-| Tinker Board | 4.14.82 |
-| Odroid-C2 | 4.19.15 |
-| Odroid-XU4 | 4.19.15 |
-| Orangepi-Prime | 4.19.13 |
-| Intel NUC | 4.14.82 |
+| Open Virtual Applicance | 4.19.94 |
+| Raspberry Pi | 4.19.93 |
+| Tinker Board | 4.19.94 |
+| Odroid-C2 | 4.19.72 |
+| Odroid-XU4 | 4.19.72 |
+| Intel NUC | 4.19.94 |

Documentation/network.md

@@ -12,7 +12,7 @@ We have a preinstalled connection profile:
 
 ```ini
 [connection]
-id=HassOS default
+id=my-network
 uuid=f62bf7c2-e565-49ff-bbfc-a4cf791e6add
 type=802-3-ethernet
 
@@ -28,7 +28,7 @@ method=auto
 
 ```ini
 [connection]
-id=hassos-network
+id=my-network
 uuid=d55162b4-6152-4310-9312-8f4c54d86afa
 type=802-3-ethernet
 
@@ -44,7 +44,7 @@ method=auto
 
 ```ini
 [connection]
-id=hassos-network
+id=my-network
 uuid=72111c67-4a5d-4d5c-925e-f8ee26efb3c3
 type=802-11-wireless
 

README.md

@@ -1,3 +1,5 @@
+[![Build Status](https://dev.azure.com/home-assistant/Hass.io/_apis/build/status/hassos?branchName=dev)](https://dev.azure.com/home-assistant/Hass.io/_build/latest?definitionId=13&branchName=dev)
+
 # HassOS
 Hass.io OS based on [buildroot](https://buildroot.org/). It's a hypervisor for Docker and supports various kind of IoT hardware. It is also available as virtual appliance. The whole system is optimized for embedded system and  security. You can update the system simple with OTA updates or offline updates.
 

azure-pipelines-ci.yml

@@ -0,0 +1,49 @@
+# https://dev.azure.com/home-assistant
+
+trigger:
+  batch: true
+  branches:
+    include:
+    - dev
+pr:
+- dev
+
+variables:
+  - name: versionHadolint
+    value: 'v1.16.3'
+  - name: versionShellCheck
+    value: 'v0.6.0'
+
+jobs:
+
+- job: 'Hadolint'
+  pool:
+    vmImage: 'ubuntu-16.04'
+  steps:
+  - script: |
+      sudo docker pull hadolint/hadolint:$(versionHadolint)
+    displayName: 'Install Hadolint'
+  - script: |
+      sudo docker run --rm -i \
+        -v $(pwd)/.hadolint.yaml:/.hadolint.yaml:ro \
+        hadolint/hadolint:$(versionHadolint) < Dockerfile
+    displayName: 'Run Hadolint'
+
+
+- job: 'ShellCheck'
+  pool:
+    vmImage: 'ubuntu-16.04'
+  steps:
+  - script: |
+      sudo docker pull koalaman/shellcheck:$(versionShellCheck)
+    displayName: 'Install ShellCheck'
+  - script: |
+      sudo docker run --rm -i \
+        -v $(pwd):/mnt:ro koalaman/shellcheck:$(versionShellCheck) \
+          scripts/*.sh \
+          buildroot-external/scripts/*.sh \
+          buildroot-external/board/**/*.sh \
+          buildroot-external/rootfs-overlay/usr/sbin/* \
+          buildroot-external/rootfs-overlay/usr/libexec/* \
+          buildroot-external/rootfs-overlay/usr/lib/rauc/*
+    displayName: 'Run ShellCheck'

azure-pipelines-release.yml

@@ -0,0 +1,93 @@
+# https://dev.azure.com/home-assistant
+
+trigger:
+  batch: true
+  tags:
+    include:
+    - '*'
+    exclude:
+    - untagged*
+pr: none
+
+variables:
+  - name: versionGHR
+    value: 'v0.12.1'
+  - group: github
+  - group: hassos
+
+jobs:
+
+- job: 'VersionValidate'
+  condition: startsWith(variables['Build.SourceBranch'], 'refs/tags')
+  pool:
+    vmImage: 'ubuntu-latest'
+  steps:
+  - script: |
+      . buildroot-external/meta
+
+      if [ "${VERSION_MAJOR}.${VERSION_BUILD}" != "$(Build.SourceBranchName)" ]; then
+        exit 1
+      fi
+    displayName: 'Check version of branch/tag'
+
+
+- job: 'Release'
+  dependsOn:
+  - 'VersionValidate'
+  timeoutInMinutes: 240
+  pool:
+    name: 'Buildroot'
+  strategy:
+    maxParallel: 1
+    matrix:
+      OpenVirtualAppliance:
+        board: 'ova'
+      IntelNuc:
+        board: 'intel_nuc'
+      OdroidC2:
+        board: 'odroid_c2'
+      OdroidXU4:
+        board: 'odroid_xu4'
+      RaspberryPi:
+        board: 'rpi'
+      RaspberryPi0-W:
+        board: 'rpi0_w'
+      RaspberryPi2:
+        board: 'rpi2'
+      RaspberryPi3:
+        board: 'rpi3'
+      RaspberryPi3-64:
+        board: 'rpi3_64'
+      RaspberryPi4:
+        board: 'rpi4'
+      RaspberryPi4-64:
+        board: 'rpi4_64'
+      AsusTinker:
+        board: 'tinker'
+  workspace:
+    clean: 'all'
+  steps:
+  - script: |
+      echo -e "-----BEGIN CERTIFICATE-----\n$(releaseCertificate)\n-----END CERTIFICATE-----" > cert.pem
+      echo -e "-----BEGIN PRIVATE KEY-----\n$(releaseKey)\n-----END PRIVATE KEY-----" > key.pem
+    displayName: 'Add release PKI certs'
+  - script: |
+      sudo docker build -t hassos:azure .
+    displayName: 'Build container for HassOS'
+  - script: |
+      curl -SsL https://github.com/tcnksm/ghr/releases/download/$(versionGHR)/ghr_$(versionGHR)_linux_amd64.tar.gz | tar xzf -
+      cp ghr_$(versionGHR)_linux_amd64/ghr .
+      rm -rf ghr_$(versionGHR)_linux_amd64
+    displayName: 'Install GHR'
+  - script: |
+      BUILDER_UID="$(id -u)"
+      BUILDER_GID="$(id -g)"
+
+      sudo docker run --rm --privileged -v "$(pwd):/build" \
+        -e BUILDER_UID="${BUILDER_UID}" -e BUILDER_GID="${BUILDER_GID}" \
+        -v "/mnt/build-cache:/cache" \
+        hassos:azure make $(board)
+    displayName: 'Build $(board)'
+  - script: |
+      ./ghr -t $(githubToken) $(Build.SourceBranchName) release/
+    displayName: 'Upload $(board)'

buildroot-external/Config.in

@@ -4,3 +4,4 @@ source "$BR2_EXTERNAL_HASSOS_PATH/package/apparmor/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/bluetooth-bcm43xx/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/bluetooth-rtl8723/Config.in"
 source "$BR2_EXTERNAL_HASSOS_PATH/package/hardkernel-boot/Config.in"
+source "$BR2_EXTERNAL_HASSOS_PATH/package/qemu-guest-agent/Config.in"

buildroot-external/board/asus/tinker/patches/linux/0006-gpu-arm-Midgard-setup_timer-timer_setup.patch

@@ -0,0 +1,98 @@
+From ee7f0a678fff8316ec0be973f1b3780a63f50942 Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Mon, 11 Dec 2017 21:04:56 +0100
+Subject: [PATCH] gpu: arm: Midgard: setup_timer() -> timer_setup()
+
+This patch is due the changes provoked by series of commit ending
+at 513ae785c63c30741e46f43960213d4ae5382ec0, and removing the
+setup_timer macros.
+The previous patches replaced made sure that timers were all set
+up with setup_timer and replaced setup_timer calls by timer_setup
+calls.
+
+This changed was introduced in the 4.15-rc1.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ drivers/gpu/arm/midgard/mali_kbase.h          | 2 +-
+ drivers/gpu/arm/midgard/mali_kbase_context.c  | 4 ++--
+ drivers/gpu/arm/midgard/mali_kbase_softjobs.c | 4 ++--
+ drivers/gpu/arm/midgard/mali_kbase_tlstream.c | 6 ++----
+ 4 files changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/arm/midgard/mali_kbase.h b/drivers/gpu/arm/midgard/mali_kbase.h
+index a4ceab9e0..27bde3b71 100644
+--- a/drivers/gpu/arm/midgard/mali_kbase.h
++++ b/drivers/gpu/arm/midgard/mali_kbase.h
+@@ -213,7 +213,7 @@ int kbase_soft_event_update(struct kbase_context *kctx,
+ 
+ bool kbase_replay_process(struct kbase_jd_atom *katom);
+ 
+-void kbasep_soft_job_timeout_worker(unsigned long data);
++void kbasep_soft_job_timeout_worker(struct timer_list *t);
+ void kbasep_complete_triggered_soft_events(struct kbase_context *kctx, u64 evt);
+ 
+ /* api used internally for register access. Contains validation and tracing */
+diff --git a/drivers/gpu/arm/midgard/mali_kbase_context.c b/drivers/gpu/arm/midgard/mali_kbase_context.c
+index f43db48fd..589df768c 100644
+--- a/drivers/gpu/arm/midgard/mali_kbase_context.c
++++ b/drivers/gpu/arm/midgard/mali_kbase_context.c
+@@ -165,9 +165,9 @@ kbase_create_context(struct kbase_device *kbdev, bool is_compat)
+ 
+ 	mutex_init(&kctx->vinstr_cli_lock);
+ 
+-	setup_timer(&kctx->soft_job_timeout,
++	timer_setup(&kctx->soft_job_timeout,
+ 		    kbasep_soft_job_timeout_worker,
+-		    (uintptr_t)kctx);
++		    0);
+ 
+ 	return kctx;
+ 
+diff --git a/drivers/gpu/arm/midgard/mali_kbase_softjobs.c b/drivers/gpu/arm/midgard/mali_kbase_softjobs.c
+index 127ada07f..019edf562 100644
+--- a/drivers/gpu/arm/midgard/mali_kbase_softjobs.c
++++ b/drivers/gpu/arm/midgard/mali_kbase_softjobs.c
+@@ -370,9 +370,9 @@ static void kbase_fence_debug_timeout(struct kbase_jd_atom *katom)
+ }
+ #endif /* CONFIG_MALI_FENCE_DEBUG */
+ 
+-void kbasep_soft_job_timeout_worker(unsigned long data)
++void kbasep_soft_job_timeout_worker(struct timer_list *t)
+ {
+-	struct kbase_context *kctx = (struct kbase_context *)data;
++	struct kbase_context *kctx = from_timer(kctx, t, soft_job_timeout);
+ 	u32 timeout_ms = (u32)atomic_read(
+ 			&kctx->kbdev->js_data.soft_job_timeout_ms);
+ 	struct timer_list *timer = &kctx->soft_job_timeout;
+diff --git a/drivers/gpu/arm/midgard/mali_kbase_tlstream.c b/drivers/gpu/arm/midgard/mali_kbase_tlstream.c
+index d01aa23b2..11d8b59c7 100644
+--- a/drivers/gpu/arm/midgard/mali_kbase_tlstream.c
++++ b/drivers/gpu/arm/midgard/mali_kbase_tlstream.c
+@@ -1042,13 +1042,11 @@ static void kbasep_tlstream_flush_stream(enum tl_stream_type stype)
+  * Timer is executed periodically to check if any of the stream contains
+  * buffer ready to be submitted to user space.
+  */
+-static void kbasep_tlstream_autoflush_timer_callback(unsigned long data)
++static void kbasep_tlstream_autoflush_timer_callback(struct timer_list *unused)
+ {
+ 	enum tl_stream_type stype;
+ 	int                 rcode;
+ 
+-	CSTD_UNUSED(data);
+-
+ 	for (stype = 0; stype < TL_STREAM_TYPE_COUNT; stype++) {
+ 		struct tl_stream *stream = tl_stream[stype];
+ 		unsigned long    flags;
+@@ -1371,7 +1369,7 @@ int kbase_tlstream_init(void)
+ 
+ 	/* Initialize autoflush timer. */
+ 	atomic_set(&autoflush_timer_active, 0);
+-	setup_timer(&autoflush_timer,
++	timer_setup(&autoflush_timer,
+ 			kbasep_tlstream_autoflush_timer_callback,
+ 			0);
+ 
+-- 
+2.14.1
+

buildroot-external/board/asus/tinker/patches/linux/0007-drivers-gpu-Arm-Midgard-Replace-ACCESS_ONCE-by-READ_.patch

@@ -0,0 +1,35 @@
+From 44a5ba2e969adfb64c84f294c16490194988dcc7 Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Sun, 24 Dec 2017 19:30:12 +0100
+Subject: [PATCH] drivers: gpu: Arm: Midgard: Replace ACCESS_ONCE by READ_ONCE
+
+The ACCESS_ONCE macro has now been removed in the 4.15.0-rc4,
+and every ACCESS_ONCE call has been replaced by either READ_ONCE or
+WRITE_ONCE calls.
+Since the Midgard GPU drivers are not mainlined, the change
+needs to be applied manually.
+
+See commit b899a850431e2dd0943205a63a68573f3e312d0d and its parents,
+for more informations.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ drivers/gpu/arm/midgard/mali_kbase_mem.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/arm/midgard/mali_kbase_mem.h b/drivers/gpu/arm/midgard/mali_kbase_mem.h
+index e9a8d5dd6..eac685699 100644
+--- a/drivers/gpu/arm/midgard/mali_kbase_mem.h
++++ b/drivers/gpu/arm/midgard/mali_kbase_mem.h
+@@ -591,7 +591,7 @@ void kbase_mem_pool_free_pages(struct kbase_mem_pool *pool, size_t nr_pages,
+  */
+ static inline size_t kbase_mem_pool_size(struct kbase_mem_pool *pool)
+ {
+-	return ACCESS_ONCE(pool->cur_size);
++	return READ_ONCE(pool->cur_size);
+ }
+ 
+ /**
+-- 
+2.14.1
+

buildroot-external/board/asus/tinker/patches/linux/0008-gpu-arm-midgard-Remove-sys_close-references.patch

@@ -0,0 +1,32 @@
+From 47e8aad9419ff8843a373c3e5aa2c9d261d8cd07 Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Mon, 23 Apr 2018 20:54:13 +0200
+Subject: [PATCH] gpu: arm: midgard: Remove sys_close references
+
+sys_close is now replaced by ksys_close in an effort to remove
+in-kernel system calls references.
+
+See 2ca2a09d6215fd9621aa3e2db7cc9428a61f2911 and
+https://lkml.org/lkml/2018/3/25/93 for more details.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ drivers/gpu/arm/midgard/mali_kbase_sync.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/arm/midgard/mali_kbase_sync.h b/drivers/gpu/arm/midgard/mali_kbase_sync.h
+index de72147d..33b58059 100644
+--- a/drivers/gpu/arm/midgard/mali_kbase_sync.h
++++ b/drivers/gpu/arm/midgard/mali_kbase_sync.h
+@@ -156,7 +156,7 @@ void kbase_sync_fence_out_remove(struct kbase_jd_atom *katom);
+  */
+ static inline void kbase_sync_fence_close_fd(int fd)
+ {
+-	sys_close(fd);
++	ksys_close(fd);
+ }
+ 
+ /**
+-- 
+2.14.1
+

buildroot-external/board/asus/tinker/patches/linux/0010-GPU-Mali-Midgard-remove-rcu_read_lock-references.patch

@@ -0,0 +1,76 @@
+From 9bf91a052d8ceddfd5808547a51e167fb7463754 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Wed, 18 Jul 2018 19:59:21 +0200
+Subject: [PATCH] GPU: Mali: Midgard: remove rcu_read_lock references
+
+This patch is actually based on @mihailescu2m patch.
+This removes references to rcu_read_lock when acquiring the OPP table,
+as it is useless since.
+See :
+https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/base/power/opp/core.c?id=5b650b388844f26c61c70564865598836d05dcb3
+
+The current rcu_read_lock actually generates some issues with recent
+kernels.
+See here :
+https://community.arm.com/graphics/f/discussions/9207/midgard-r20p0-kernel-drivers-errors
+
+The patch has been recreated since it does not apply directly on r19p0
+sources (I guess the affected line numbers slightly differ...).
+
+@mihailescu2m patch for the Mali Midgard r20p0 kernel driver can be
+acquired here :
+https://github.com/mihailescu2m/linux/commit/bbe73c3c1143e5991bdcaee3afaecf5c31af0647
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c b/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
+index e280322e..bf69d897 100644
+--- a/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
++++ b/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
+@@ -87,10 +87,9 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
+ 
+ 	freq = *target_freq;
+ 
+-	rcu_read_lock();
+ 	opp = devfreq_recommended_opp(dev, &freq, flags);
+ 	voltage = dev_pm_opp_get_voltage(opp);
+-	rcu_read_unlock();
++
+ 	if (IS_ERR_OR_NULL(opp)) {
+ 		dev_err(dev, "Failed to get opp (%ld)\n", PTR_ERR(opp));
+ 		return PTR_ERR(opp);
+@@ -186,20 +185,17 @@ static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev,
+ 	unsigned long freq;
+ 	struct dev_pm_opp *opp;
+ 
+-	rcu_read_lock();
+ 	count = dev_pm_opp_get_opp_count(kbdev->dev);
+ 	if (count < 0) {
+ 		rcu_read_unlock();
+ 		return count;
+ 	}
+-	rcu_read_unlock();
+ 
+ 	dp->freq_table = kmalloc_array(count, sizeof(dp->freq_table[0]),
+ 				GFP_KERNEL);
+ 	if (!dp->freq_table)
+ 		return -ENOMEM;
+ 
+-	rcu_read_lock();
+ 	for (i = 0, freq = ULONG_MAX; i < count; i++, freq--) {
+ 		opp = dev_pm_opp_find_freq_floor(kbdev->dev, &freq);
+ 		if (IS_ERR(opp))
+@@ -207,7 +203,6 @@ static int kbase_devfreq_init_freq_table(struct kbase_device *kbdev,
+ 
+ 		dp->freq_table[i] = freq;
+ 	}
+-	rcu_read_unlock();
+ 
+ 	if (count != i)
+ 		dev_warn(kbdev->dev, "Unable to enumerate all OPPs (%d!=%d\n",
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/1-2-regulator-act8865-add-restart-handler-for-act8846.patch

@@ -0,0 +1,74 @@
+Patches act8846 regulator providing the proper reset handle and exploit
+the SIPC bit in GLB_POWER_OFF register. Mainly used to reset some rockchip
+boards.
+
+Origin: <https://patchwork.kernel.org/patch/6409521/>
+
+diff --git a/drivers/regulator/act8865-regulator.c b/drivers/regulator/act8865-regulator.c
+index 2ff73d7..836d10b 100644
+--- a/drivers/regulator/act8865-regulator.c
++++ b/drivers/regulator/act8865-regulator.c
+@@ -27,6 +27,7 @@
+ #include <linux/of_device.h>
+ #include <linux/regulator/of_regulator.h>
+ #include <linux/regmap.h>
++#include <linux/reboot.h>
+ 
+ /*
+  * ACT8600 Global Register Map.
+@@ -133,6 +134,8 @@
+ #define	ACT8865_VOLTAGE_NUM	64
+ #define ACT8600_SUDCDC_VOLTAGE_NUM	255
+ 
++#define ACT8846_SIPC_MASK 0x01
++
+ struct act8865 {
+ 	struct regmap *regmap;
+ 	int off_reg;
+@@ -402,6 +405,22 @@ static void act8865_power_off(void)
+ 	while (1);
+ }
+ 
++static int act8846_power_cycle(struct notifier_block *this,
++	unsigned long code, void *unused)
++{
++	struct act8865 *act8846;
++
++	act8846 = i2c_get_clientdata(act8865_i2c_client);
++	regmap_write(act8846->regmap, ACT8846_GLB_OFF_CTRL, ACT8846_SIPC_MASK);
++
++	return NOTIFY_DONE;
++}
++
++static struct notifier_block act8846_restart_handler = {
++	.notifier_call = act8846_power_cycle,
++	.priority = 129,
++};
++
+ static int act8865_pmic_probe(struct i2c_client *client,
+ 			      const struct i2c_device_id *i2c_id)
+ {
+@@ -484,6 +503,8 @@ static int act8865_pmic_probe(struct i2c_client *client,
+ 	}
+ 
+ 	if (of_device_is_system_power_controller(dev->of_node)) {
++		int ret;
++
+ 		if (!pm_power_off && (off_reg > 0)) {
+ 			act8865_i2c_client = client;
+ 			act8865->off_reg = off_reg;
+@@ -492,6 +513,14 @@ static int act8865_pmic_probe(struct i2c_client *client,
+ 		} else {
+ 			dev_err(dev, "Failed to set poweroff capability, already defined\n");
+ 		}
++
++		if (type == ACT8846) {
++			act8865_i2c_client = client;
++			ret = register_restart_handler(&act8846_restart_handler);
++			if (ret)
++				pr_err("%s: cannot register restart handler, %d\n",
++					__func__, ret);
++		}
+ 	}
+ 
+ 	/* Finally register devices */

buildroot-external/board/asus/tinker/patches/linux/1001-Integrating-the-Mali-drivers.patch

@@ -1,65 +0,0 @@
-From 7de25b73e152830587740d8f2ffaad94c72d90ac Mon Sep 17 00:00:00 2001
-From: Myy <myy@miouyouyou.fr>
-Date: Mon, 17 Jul 2017 11:24:47 +0000
-Subject: [PATCH 1/5] Integrating the Mali drivers
-
-Changses required in order to select and compile the previously copied
-Mali Midgard drivers.
-
-Signed-off-by: Myy <myy@miouyouyou.fr>
-
----
- drivers/base/Kconfig  | 2 ++
- drivers/base/Makefile | 1 +
- drivers/gpu/Makefile  | 2 +-
- drivers/video/Kconfig | 1 +
- 4 files changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
-index f046d21..b0982fc 100644
---- a/drivers/base/Kconfig
-+++ b/drivers/base/Kconfig
-@@ -348,3 +348,5 @@ config GENERIC_ARCH_TOPOLOGY
- 	  runtime.
- 
- endmenu
-+
-+source "drivers/base/ump/Kconfig"
-diff --git a/drivers/base/Makefile b/drivers/base/Makefile
-index 397e5c3..251e0cf 100644
---- a/drivers/base/Makefile
-+++ b/drivers/base/Makefile
-@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL) += pinctrl.o
- obj-$(CONFIG_DEV_COREDUMP) += devcoredump.o
- obj-$(CONFIG_GENERIC_MSI_IRQ_DOMAIN) += platform-msi.o
- obj-$(CONFIG_GENERIC_ARCH_TOPOLOGY) += arch_topology.o
-+obj-$(CONFIG_UMP) += ump/
- 
- obj-y			+= test/
- 
-diff --git a/drivers/gpu/Makefile b/drivers/gpu/Makefile
-index e9ed439..66386b4 100644
---- a/drivers/gpu/Makefile
-+++ b/drivers/gpu/Makefile
-@@ -2,5 +2,5 @@
- # taken to initialize them in the correct order. Link order is the only way
- # to ensure this currently.
- obj-$(CONFIG_TEGRA_HOST1X)	+= host1x/
--obj-y			+= drm/ vga/
-+obj-y			+= drm/ vga/ arm/
- obj-$(CONFIG_IMX_IPUV3_CORE)	+= ipu-v3/
-diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
-index 3c20af9..041e15f 100644
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -17,6 +17,7 @@ source "drivers/gpu/vga/Kconfig"
- 
- source "drivers/gpu/host1x/Kconfig"
- source "drivers/gpu/ipu-v3/Kconfig"
-+source "drivers/gpu/arm/midgard/Kconfig"
- 
- source "drivers/gpu/drm/Kconfig"
- 
--- 
-2.10.2
-

buildroot-external/board/asus/tinker/patches/linux/1001-drivers-Integrating-Mali-Midgard-video-and-gpu-drive.patch

@@ -0,0 +1,39 @@
+From fe85565d9ed8212cbda2148d4731418a36a8d088 Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Mon, 11 Dec 2017 21:53:28 +0100
+Subject: [PATCH 1/3] drivers: Integrating Mali Midgard video and gpu drivers.
+
+I'm dropping the UMP drivers. They are not maintained.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ drivers/gpu/Makefile  | 2 +-
+ drivers/video/Kconfig | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/Makefile b/drivers/gpu/Makefile
+index e9ed439a5..66386b42a 100644
+--- a/drivers/gpu/Makefile
++++ b/drivers/gpu/Makefile
+@@ -2,5 +2,5 @@
+ # taken to initialize them in the correct order. Link order is the only way
+ # to ensure this currently.
+ obj-$(CONFIG_TEGRA_HOST1X)	+= host1x/
+-obj-y			+= drm/ vga/
++obj-y			+= drm/ vga/ arm/
+ obj-$(CONFIG_IMX_IPUV3_CORE)	+= ipu-v3/
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index 3c20af999..041e15f2c 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -17,6 +17,7 @@ source "drivers/gpu/vga/Kconfig"
+ 
+ source "drivers/gpu/host1x/Kconfig"
+ source "drivers/gpu/ipu-v3/Kconfig"
++source "drivers/gpu/arm/midgard/Kconfig"
+ 
+ source "drivers/gpu/drm/Kconfig"
+ 
+-- 
+2.14.1
+

buildroot-external/board/asus/tinker/patches/linux/1003-clk-rockchip-rk3288-prefer-vdpu-for-vcodec-clock-sou.patch

@@ -1,41 +0,0 @@
-From b82f540967f6a732a22bbd236457b864951aeda7 Mon Sep 17 00:00:00 2001
-From: Myy <myy@miouyouyou.fr>
-Date: Sun, 14 May 2017 10:13:26 +0000
-Subject: [PATCH] clk: rockchip: rk3288: prefer vdpu for vcodec clock source
-
-Patch provided by Randy Li. The original commit message reads :
-
-_______________
-The RK3288 CRU system clock solution would suggest use
-the vdpu clock source for the VPU(aclk_vpu and hclk_vpu).
-
-Reading the registers of VPU(both VEPU and VDPU) would become all high
-when the vepu is used as the clock source. It may be a bug in the SoC,
-not sure whether it is fixed at RK3288W.
-
-Signed-off-by: Randy Li <ayaka@soulik.info>
-_______________
-
-This also resolves a freeze when loading the OOT Video Codec driver
-
-Signed-off-by: Myy <myy@miouyouyou.fr>
----
- drivers/clk/rockchip/clk-rk3288.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
-index 1227f74..f218256 100644
---- a/drivers/clk/rockchip/clk-rk3288.c
-+++ b/drivers/clk/rockchip/clk-rk3288.c
-@@ -215,7 +215,7 @@ PNAME(mux_hsadcout_p)	= { "hsadc_src", "ext_hsadc" };
- PNAME(mux_edp_24m_p)	= { "ext_edp_24m", "xin24m" };
- PNAME(mux_tspout_p)	= { "cpll", "gpll", "npll", "xin27m" };
- 
--PNAME(mux_aclk_vcodec_pre_p)	= { "aclk_vepu", "aclk_vdpu" };
-+PNAME(mux_aclk_vcodec_pre_p)	= { "aclk_vdpu", "aclk_vepu" };
- PNAME(mux_usbphy480m_p)		= { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
- 				    "sclk_otgphy0_480m" };
- PNAME(mux_hsicphy480m_p)	= { "cpll", "gpll", "usbphy480m_src" };
--- 
-2.10.2
-

buildroot-external/board/asus/tinker/patches/linux/1005-ASUS-Tinkerboard-Stupid-reboot.patch

@@ -1,32 +1,38 @@
-From 1aeeeeaf10ad5888c1a5b3ab9b780be91c7dada9 Mon Sep 17 00:00:00 2001
-From: Myy <myy@miouyouyou.fr>
-Date: Mon, 24 Jul 2017 23:09:31 +0000
-Subject: [PATCH] Last try for the reboot hack
+From bf9b932f6ae506baf5b79c8407089448ed77fc56 Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Sun, 17 Dec 2017 16:15:03 +0100
+Subject: [PATCH] ASUS Tinkerboard: Stupid reboot patch
 
-If this one does not work, get a refund for your CantRebootBoard.
+This patch is ugly as shit and will be reworked when possible.
 
-Signed-off-by: Myy <myy@miouyouyou.fr>
+Meanwhile, this fixes an issue with the ASUS Tinkerboard which
+cannot reboot correctly. The issue is that the MMC hardware is
+shutdown during the reboot phase and is not powered again after
+the power cycle, leading to a dead board awaiting a hard power
+cycle.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
 ---
  drivers/mmc/host/dw_mmc-rockchip.c | 24 ++++++++++++++++++++++++
- drivers/mmc/host/dw_mmc.c          | 26 ++++++++++++++++++++++++++
- include/linux/reboot.h             |  3 +++
+ drivers/mmc/host/dw_mmc.c          | 28 ++++++++++++++++++++++++++++
+ include/linux/reboot.h             |  2 ++
  kernel/reboot.c                    |  1 +
- 4 files changed, 54 insertions(+)
+ 4 files changed, 55 insertions(+)
 
 diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
-index aaed6f9b..71131020 100644
+index a3f1c2b30..52c13733f 100644
 --- a/drivers/mmc/host/dw_mmc-rockchip.c
 +++ b/drivers/mmc/host/dw_mmc-rockchip.c
 @@ -14,10 +14,12 @@
  #include <linux/of_address.h>
  #include <linux/mmc/slot-gpio.h>
  #include <linux/pm_runtime.h>
-+#include <linux/regulator/consumer.h> // Hack
++#include <linux/regulator/consumer.h> // Stupid Tinkerboard Hack
  #include <linux/slab.h>
  
  #include "dw_mmc.h"
  #include "dw_mmc-pltfm.h"
-+#include "../core/core.h" // Hack
++#include "../core/core.h" // Stupid Tinkerboard Hack
  
  #define RK3288_CLKGEN_DIV       2
  
@@ -34,6 +40,7 @@ index aaed6f9b..71131020 100644
  	return 0;
  }
  
++/* Stupid Tinkerboard Hack */
 +static void dw_mci_rockchip_platfm_shutdown(struct platform_device *pdev)
 +{
 +	struct dw_mci *host = platform_get_drvdata(pdev);
@@ -53,7 +60,6 @@ index aaed6f9b..71131020 100644
 +			regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
 +	}
 +}
-+
 +
  static int dw_mci_rockchip_remove(struct platform_device *pdev)
  {
@@ -62,29 +68,30 @@ index aaed6f9b..71131020 100644
  static struct platform_driver dw_mci_rockchip_pltfm_driver = {
  	.probe		= dw_mci_rockchip_probe,
  	.remove		= dw_mci_rockchip_remove,
-+	.shutdown	= dw_mci_rockchip_platfm_shutdown,
++	.shutdown	= dw_mci_rockchip_platfm_shutdown, // Stupid Tinkerboard Hack
  	.driver		= {
  		.name		= "dwmmc_rockchip",
  		.of_match_table	= dw_mci_rockchip_match,
 diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
-index a9dfb269..ee956a57 100644
+index 0aa39975f..70f7ce21b 100644
 --- a/drivers/mmc/host/dw_mmc.c
 +++ b/drivers/mmc/host/dw_mmc.c
 @@ -39,8 +39,10 @@
  #include <linux/of.h>
  #include <linux/of_gpio.h>
  #include <linux/mmc/slot-gpio.h>
-+#include <linux/reboot.h> // Hack
++#include <linux/reboot.h> // Stupid Tinkerboard Hack
  
  #include "dw_mmc.h"
-+#include "../core/core.h" // Hack
++#include "../core/core.h" // Stupid Tinkerboard Hack
  
  /* Common flag combinations */
  #define DW_MCI_DATA_ERROR_FLAGS	(SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
-@@ -2687,6 +2689,28 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
+@@ -2778,6 +2780,29 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
  	return IRQ_HANDLED;
  }
  
++/* Stupid Tinkerboard Hack */
 +struct dw_mci *mSdhost;
 +void setmmcEmergency() {
 +	struct mmc_host *mmc;
@@ -110,47 +117,41 @@ index a9dfb269..ee956a57 100644
  static int dw_mci_init_slot(struct dw_mci *host)
  {
  	struct mmc_host *mmc;
-@@ -2718,6 +2742,8 @@ static int dw_mci_init_slot(struct dw_mci *host)
+@@ -2809,6 +2834,9 @@ static int dw_mci_init_slot(struct dw_mci *host)
  		mmc->f_max = freq[1];
  	}
  
++	/* Stupid Tinkerboard Hack */
 +	if (of_find_property(host->dev->of_node, "supports-sd", NULL))
 +		mSdhost = host;
  	/*if there are external regulators, get them*/
  	ret = mmc_regulator_get_supply(mmc);
- 	if (ret == -EPROBE_DEFER)
+ 	if (ret)
 diff --git a/include/linux/reboot.h b/include/linux/reboot.h
-index a7ff409f..586e4504 100644
+index e63799a6e..057d3ce0c 100644
 --- a/include/linux/reboot.h
 +++ b/include/linux/reboot.h
-@@ -72,12 +72,15 @@ extern char poweroff_cmd[POWEROFF_CMD_PATH_LEN];
+@@ -77,6 +77,8 @@ extern char poweroff_cmd[POWEROFF_CMD_PATH_LEN];
  
  extern void orderly_poweroff(bool force);
  extern void orderly_reboot(void);
-+// Wonderful ASUS hack
++/* Stupid Tinkerboard Hack */
 +extern void setmmcEmergency(void);
  
  /*
   * Emergency restart, callable from an interrupt handler.
-  */
- 
- extern void emergency_restart(void);
-+
- #include <asm/emergency-restart.h>
- 
- #endif /* _LINUX_REBOOT_H */
 diff --git a/kernel/reboot.c b/kernel/reboot.c
-index bd30a973..9f99488f 100644
+index e4ced883d..c8e678ce6 100644
 --- a/kernel/reboot.c
 +++ b/kernel/reboot.c
 @@ -61,6 +61,7 @@ void (*pm_power_off_prepare)(void);
  void emergency_restart(void)
  {
  	kmsg_dump(KMSG_DUMP_EMERG);
-+	setmmcEmergency();
++	setmmcEmergency(); // Stupid Tinkerboard Hack
  	machine_emergency_restart();
  }
  EXPORT_SYMBOL_GPL(emergency_restart);
 -- 
-2.13.0
+2.14.1
 

buildroot-external/board/asus/tinker/patches/linux/1005-drivers-mmc-dw-mci-rockchip-Handle-ASUS-Tinkerboard.patch

@@ -0,0 +1,116 @@
+From 302cd9b8a9f1f8a7735fabea3b9a7645dc40f9cc Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Sun, 7 Jan 2018 01:52:44 +0100
+Subject: [PATCH] drivers: mmc: dw-mci-rockchip: Handle ASUS Tinkerboard reboot
+
+On ASUS Tinkerboard systems, if the SDMMC hardware is shutdown before
+rebooting, the system will be dead, as the SDMMC is the only way to
+boot anything, and the hardware doesn't power up the SDMMC hardware
+automatically when rebooting.
+
+So, when using an ASUS Tinkerboard system, a new reboot handler is
+installed. This reboot handler takes care of powering the SDMMC
+hardware again before restarting the system, resolving the issue.
+
+The code was inspired by the pwrseq_emmc.c, which seems to overcome
+similar effects with eMMC hardware.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ drivers/mmc/host/dw_mmc-rockchip.c | 66 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 66 insertions(+)
+
+diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
+index a3f1c2b30..7eac1f221 100644
+--- a/drivers/mmc/host/dw_mmc-rockchip.c
++++ b/drivers/mmc/host/dw_mmc-rockchip.c
+@@ -16,6 +16,11 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/slab.h>
+ 
++#include <linux/regulator/consumer.h>
++#include <linux/reboot.h>
++#include <linux/delay.h>
++#include "../core/core.h"
++
+ #include "dw_mmc.h"
+ #include "dw_mmc-pltfm.h"
+ 
+@@ -334,6 +339,66 @@ static const struct of_device_id dw_mci_rockchip_match[] = {
+ };
+ MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
+ 
++struct dw_mci_rockchip_broken_boards_data {
++	struct notifier_block reset_nb;
++	struct platform_device *pdev;
++};
++
++/* This reboot handler handles cases where disabling the SDMMC on
++ * reboot will cause the hardware to be unable to start correctly
++ * after rebooting.
++ * 
++ * This happens with Tinkerboard systems...
++ */
++static int dw_mci_rockchip_broken_boards_reset_nb(
++	struct notifier_block *this,
++	unsigned long mode, void *cmd)
++{
++	struct dw_mci_rockchip_broken_boards_data const *data =
++		container_of(this,
++			struct dw_mci_rockchip_broken_boards_data,
++			reset_nb);
++	struct dw_mci *host = platform_get_drvdata(data->pdev);
++	struct mmc_host *mmc = host->slot->mmc;
++
++	printk(KERN_ERR "Meow.\n");
++
++	mmc_power_off(mmc);
++
++	mdelay(20);
++
++	if (!IS_ERR(mmc->supply.vmmc))
++		regulator_enable(mmc->supply.vmmc);
++
++	if (!IS_ERR(mmc->supply.vqmmc))
++		regulator_set_voltage(mmc->supply.vqmmc, 3000000, 3300000);
++
++	printk(KERN_ERR "woeM.\n");
++
++	return NOTIFY_DONE;
++}
++
++static void dw_mci_rockchip_register_broken_boards_reboot_handler(
++	struct platform_device *pdev)
++{
++	struct dw_mci_rockchip_broken_boards_data *data;
++
++	if (!of_machine_is_compatible("asus,rk3288-tinker"))
++		return;
++
++	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++
++	if (!data)
++		return;
++
++	data->reset_nb.notifier_call =
++		dw_mci_rockchip_broken_boards_reset_nb;
++	data->reset_nb.priority = 255;
++	register_restart_handler(&data->reset_nb);
++
++	data->pdev = pdev;
++}
++
+ static int dw_mci_rockchip_probe(struct platform_device *pdev)
+ {
+ 	const struct dw_mci_drv_data *drv_data;
+@@ -361,6 +426,7 @@ static int dw_mci_rockchip_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	pm_runtime_put_autosuspend(&pdev->dev);
++	dw_mci_rockchip_register_broken_boards_reboot_handler(pdev);
+ 
+ 	return 0;
+ }
+-- 
+2.14.1
+

buildroot-external/board/asus/tinker/patches/linux/1006-soc-rockchip-power-domain-export-idle-request.patch

@@ -0,0 +1,82 @@
+From 4ffe79de7272234408a9179aa4c403ee1b67a362 Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Thu, 7 Dec 2017 21:27:52 +0100
+Subject: [PATCH] soc: rockchip: power-domain: export idle request
+
+We need to put the power status of HEVC/RKVDEC IP into IDLE
+unless we can't reset that IP or the SoC would crash down.
+rockchip_pmu_idle_request(dev, true)---> enter idle
+rockchip_pmu_idle_request(dev, false)---> exit idle
+
+Only the video codec drivers of rockchip platform would
+request this patch currently.
+
+I am not sure whether it is necessary to add a new function
+at generic power domain. I want someone give me some advises
+here.
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ drivers/soc/rockchip/pm_domains.c | 23 +++++++++++++++++++++++
+ include/linux/rockchip_pmu.h      | 15 +++++++++++++++
+ 2 files changed, 38 insertions(+)
+ create mode 100644 include/linux/rockchip_pmu.h
+
+diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
+index 40b75748..0006ed53 100644
+--- a/drivers/soc/rockchip/pm_domains.c
++++ b/drivers/soc/rockchip/pm_domains.c
+@@ -180,6 +180,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
+ 	return 0;
+ }
+ 
++int rockchip_pmu_idle_request(struct device *dev, bool idle)
++{
++	struct generic_pm_domain *genpd;
++	struct rockchip_pm_domain *pd;
++	int ret;
++
++	if (IS_ERR_OR_NULL(dev))
++		return -EINVAL;
++
++	if (IS_ERR_OR_NULL(dev->pm_domain))
++		return -EINVAL;
++
++	genpd = pd_to_genpd(dev->pm_domain);
++	pd = to_rockchip_pd(genpd);
++
++	mutex_lock(&pd->pmu->mutex);
++	ret = rockchip_pmu_set_idle_request(pd, idle);
++	mutex_unlock(&pd->pmu->mutex);
++
++	return ret;
++}
++EXPORT_SYMBOL(rockchip_pmu_idle_request);
++
+ static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
+ {
+ 	int i;
+diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h
+new file mode 100644
+index 00000000..720b3314
+--- /dev/null
++++ b/include/linux/rockchip_pmu.h
+@@ -0,0 +1,15 @@
++/*
++ * pm_domain.h - Definitions and headers related to device power domains.
++ *
++ * Copyright (C) 2017 Randy Li <ayaka@soulik.info>.
++ *
++ * This file is released under the GPLv2.
++ */
++
++#ifndef _LINUX_ROCKCHIP_PM_H
++#define _LINUX_ROCKCHIP_PM_H
++#include <linux/device.h>
++
++int rockchip_pmu_idle_request(struct device *dev, bool idle);
++
++#endif /* _LINUX_ROCKCHIP_PM_H */
+-- 
+2.14.1
+

buildroot-external/board/asus/tinker/patches/linux/1007-dt-bindings-Document-the-Rockchip-RGA-bindings.patch

@@ -1,59 +0,0 @@
-From c9f505dba7e4a3adc62054b852349e8bbae10326 Mon Sep 17 00:00:00 2001
-From: Jacob Chen <jacob-chen@iotwrt.com>
-Date: Mon, 26 Jun 2017 22:53:22 +0800
-Subject: [PATCH 5/9] dt-bindings: Document the Rockchip RGA bindings
-
-Add DT bindings documentation for Rockchip RGA
-
-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
-Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
----
- .../devicetree/bindings/media/rockchip-rga.txt     | 36 ++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/media/rockchip-rga.txt
-
-diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.txt b/Documentation/devicetree/bindings/media/rockchip-rga.txt
-new file mode 100644
-index 00000000..48a260e5
---- /dev/null
-+++ b/Documentation/devicetree/bindings/media/rockchip-rga.txt
-@@ -0,0 +1,36 @@
-+device-tree bindings for rockchip 2D raster graphic acceleration controller (RGA)
-+
-+RGA is a separate 2D raster graphic acceleration unit. It accelerates 2D
-+graphics operations, such as point/line drawing, image scaling, rotation,
-+BitBLT, alpha blending and image blur/sharpness.
-+
-+Required properties:
-+- compatible: value should be one of the following
-+		"rockchip,rk3228-rga";
-+		"rockchip,rk3288-rga";
-+		"rockchip,rk3399-rga";
-+
-+- interrupts: RGA interrupt number.
-+
-+- clocks: phandle to RGA sclk/hclk/aclk clocks
-+
-+- clock-names: should be "aclk" "hclk" and "sclk"
-+
-+- resets: Must contain an entry for each entry in reset-names.
-+  See ../reset/reset.txt for details.
-+- reset-names: should be "core" "axi" and "ahb"
-+
-+Example:
-+SoC specific DT entry:
-+	rga: rga@ff680000 {
-+		compatible = "rockchip,rk3399-rga";
-+		reg = <0xff680000 0x10000>;
-+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "rga";
-+		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
-+		clock-names = "aclk", "hclk", "sclk";
-+
-+		resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
-+		reset-names = "core, "axi", "ahb";
-+		status = "disabled";
-+	};
--- 
-2.13.0
-

buildroot-external/board/asus/tinker/patches/linux/1008-dwc2-avoid_nak_for_csplit.patch

@@ -1,83 +0,0 @@
-diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
-index 7b6eb0ad513b..96b6935dc0d7 100644
---- a/drivers/usb/dwc2/hcd.c
-+++ b/drivers/usb/dwc2/hcd.c
-@@ -2748,6 +2748,8 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
- 	chan->xfer_len = urb->length - urb->actual_length;
- 	chan->xfer_count = 0;
- 
-+	chan->csplit_nak = 0;
-+
- 	/* Set the split attributes if required */
- 	if (qh->do_split)
- 		dwc2_hc_init_split(hsotg, chan, qtd, urb);
-diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h
-index 78e9e01051b5..e54f1351225b 100644
---- a/drivers/usb/dwc2/hcd.h
-+++ b/drivers/usb/dwc2/hcd.h
-@@ -143,6 +143,7 @@ struct dwc2_host_chan {
- 	u8 halt_pending;
- 	u8 do_split;
- 	u8 complete_split;
-+	u8 csplit_nak;
- 	u8 hub_addr;
- 	u8 hub_port;
- 	u8 xact_pos;
-diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
-index 916d991b96b8..551cfacd2252 100644
---- a/drivers/usb/dwc2/hcd_intr.c
-+++ b/drivers/usb/dwc2/hcd_intr.c
-@@ -691,6 +691,7 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
- 	enum dwc2_transaction_type tr_type;
- 	u32 haintmsk;
- 	int free_qtd = 0;
-+	int continue_trans = 1;
- 
- 	if (dbg_hc(chan))
- 		dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
-@@ -719,6 +720,7 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
- 		 * deactivated. Don't want to do anything except release the
- 		 * host channel and try to queue more transfers.
- 		 */
-+		continue_trans = 0;
- 		goto cleanup;
- 	case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
- 		dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
-@@ -730,6 +732,11 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
- 		break;
- 	}
- 
-+	if (chan->csplit_nak) {
-+		continue_trans = 0;
-+		chan->csplit_nak = 0;
-+	}
-+
- 	dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
- 
- cleanup:
-@@ -767,9 +774,11 @@ static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
- 	dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
- 
- 	/* Try to queue more transfers now that there's a free channel */
--	tr_type = dwc2_hcd_select_transactions(hsotg);
--	if (tr_type != DWC2_TRANSACTION_NONE)
--		dwc2_hcd_queue_transactions(hsotg, tr_type);
-+	if (continue_trans) {
-+		tr_type = dwc2_hcd_select_transactions(hsotg);
-+		if (tr_type != DWC2_TRANSACTION_NONE)
-+			dwc2_hcd_queue_transactions(hsotg, tr_type);
-+	}
- }
- 
- /*
-@@ -1205,6 +1214,7 @@ static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
- 	if (chan->do_split) {
- 		if (chan->complete_split)
- 			qtd->error_count = 0;
-+		chan->csplit_nak = 1;
- 		qtd->complete_split = 0;
- 		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
- 		goto handle_nak_done;
--- 
-2.11.0
-

buildroot-external/board/asus/tinker/patches/linux/1009-drivers-clk-rk3288-support-for-dedicating-NPLL-to-a-.patch

@@ -0,0 +1,228 @@
+From bc16cd0aa3cdaaff27b9bf2d3282ccfff81d8784 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Sat, 29 Sep 2018 02:56:32 +0200
+Subject: [PATCH 5/6] drivers: clk-rk3288: support for dedicating NPLL to a VOP
+
+This patch is taken from Urja Rannikko ( @urjaman ) patchset here :
+https://github.com/urjaman/arch-c201/blob/master/linux-c201/0020-RK3288-HDMI-clock-hacks-combined.patch
+https://www.spinics.net/lists/arm-kernel/msg673156.html
+
+I'm not really sure what this does exactly. It basically sets the
+parent clock of the newly added clocks, if the newly added property
+"rockchip,npll-for-vop" is detected and set.
+
+I have no clear idea how HDMI Neuronal PLL (and PLL in general) work,
+so I cannot comment on what it's doing and if it's a good idea in
+general.
+
+The only thing I know from this patchset is that it works and have
+resolved some purple line issue at the left of my HDMI screen, when
+connected to MiQi or Tinkerboard devices.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ drivers/clk/rockchip/clk-rk3288.c | 98 ++++++++++++++++++++++++++++++++-------
+ drivers/clk/rockchip/clk.h        |  3 ++
+ 2 files changed, 85 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
+index fd2058f7d..b5b56169d 100644
+--- a/drivers/clk/rockchip/clk-rk3288.c
++++ b/drivers/clk/rockchip/clk-rk3288.c
+@@ -83,22 +83,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
+ 	RK3066_PLL_RATE( 768000000, 1, 64, 2),
+ 	RK3066_PLL_RATE( 742500000, 8, 495, 2),
+ 	RK3066_PLL_RATE( 696000000, 1, 58, 2),
++	RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),
+ 	RK3066_PLL_RATE( 600000000, 1, 50, 2),
+ 	RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
+ 	RK3066_PLL_RATE( 552000000, 1, 46, 2),
+ 	RK3066_PLL_RATE( 504000000, 1, 84, 4),
+ 	RK3066_PLL_RATE( 500000000, 3, 125, 2),
+ 	RK3066_PLL_RATE( 456000000, 1, 76, 4),
++	RK3066_PLL_RATE( 428000000, 1, 107, 6),
+ 	RK3066_PLL_RATE( 408000000, 1, 68, 4),
+ 	RK3066_PLL_RATE( 400000000, 3, 100, 2),
++	RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),
+ 	RK3066_PLL_RATE( 384000000, 2, 128, 4),
+ 	RK3066_PLL_RATE( 360000000, 1, 60, 4),
++	RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),
++	RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),
+ 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
+-	RK3066_PLL_RATE( 300000000, 1, 50, 4),
+-	RK3066_PLL_RATE( 297000000, 2, 198, 8),
++	RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1),
++	RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),
++	RK3066_PLL_RATE( 300000000, 1, 75, 6),
++	RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),
++	RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),
++	RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),
++	RK3066_PLL_RATE( 273600000, 1, 114, 10),
++	RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1),
++	RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1),
++	RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1),
++	RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1),
+ 	RK3066_PLL_RATE( 252000000, 1, 84, 8),
+-	RK3066_PLL_RATE( 216000000, 1, 72, 8),
+-	RK3066_PLL_RATE( 148500000, 2, 99, 8),
++	RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1),
++	RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1),
++	RK3066_PLL_RATE( 238000000, 1, 119, 12),
++	RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1),
++	RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1),
++	RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1),
++	RK3066_PLL_RATE( 195428571, 1, 114, 14),
++	RK3066_PLL_RATE( 160000000, 1, 80, 12),
++	RK3066_PLL_RATE( 157500000, 1, 105, 16),
+ 	RK3066_PLL_RATE( 126000000, 1, 84, 16),
+ 	RK3066_PLL_RATE(  48000000, 1, 64, 32),
+ 	{ /* sentinel */ },
+@@ -194,10 +215,14 @@ PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
+ PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu" };
+ 
+ PNAME(mux_pll_src_cpll_gpll_p)		= { "cpll", "gpll" };
+-PNAME(mux_pll_src_npll_cpll_gpll_p)	= { "npll", "cpll", "gpll" };
+-PNAME(mux_pll_src_cpll_gpll_npll_p)	= { "cpll", "gpll", "npll" };
++PNAME_ED(mux_pll_src_npll_cpll_gpll_p)	= { "npll", "cpll", "gpll" };
++
++PNAME_ED(mux_pll_src_cgn_pll_nonvop_p)	= { "cpll", "gpll", "npll" };
++PNAME_ED(mux_pll_src_cgn_pll_vop0_p) = { "cpll", "gpll", "npll" };
++PNAME_ED(mux_pll_src_cgn_pll_vop1_p) = { "cpll", "gpll", "npll" };
++
+ PNAME(mux_pll_src_cpll_gpll_usb480m_p)	= { "cpll", "gpll", "usbphy480m_src" };
+-PNAME(mux_pll_src_cpll_gll_usb_npll_p)	= { "cpll", "gpll", "usbphy480m_src", "npll" };
++PNAME_ED(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
+ 
+ PNAME(mux_mmc_src_p)	= { "cpll", "gpll", "xin24m", "xin24m" };
+ PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
+@@ -443,24 +468,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 			RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 4, GFLAGS),
+ 
+-	COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cgn_pll_vop0_p, 0,
+ 			RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 1, GFLAGS),
+-	COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cgn_pll_vop1_p, 0,
+ 			RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 3, GFLAGS),
+ 
+ 	COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
+ 			RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
+ 			RK3288_CLKGATE_CON(3), 12, GFLAGS),
+-	COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cgn_pll_nonvop_p, 0,
+ 			RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 13, GFLAGS),
+ 
+-	COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cgn_pll_nonvop_p, 0,
+ 			RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 14, GFLAGS),
+-	COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cgn_pll_nonvop_p, 0,
+ 			RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ 			RK3288_CLKGATE_CON(3), 15, GFLAGS),
+ 
+@@ -469,16 +494,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 	GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
+ 			RK3288_CLKGATE_CON(5), 11, GFLAGS),
+ 
+-	COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cgn_pll_nonvop_p, 0,
+ 			RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ 			RK3288_CLKGATE_CON(13), 13, GFLAGS),
+ 	DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
+ 			RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
+ 
+-	COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cgn_pll_nonvop_p, 0,
+ 			RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ 			RK3288_CLKGATE_CON(13), 14, GFLAGS),
+-	COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cgn_pll_nonvop_p, 0,
+ 			RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ 			RK3288_CLKGATE_CON(13), 15, GFLAGS),
+ 
+@@ -552,7 +577,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
+ 	COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
+ 			RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ 			RK3288_CLKGATE_CON(4), 11, GFLAGS),
+-	COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
++	COMPOSITE(0, "sclk_tsp", mux_pll_src_cgn_pll_nonvop_p, 0,
+ 			RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ 			RK3288_CLKGATE_CON(4), 10, GFLAGS),
+ 
+@@ -912,6 +937,7 @@ static void __init rk3288_clk_init(struct device_node *np)
+ {
+ 	struct rockchip_clk_provider *ctx;
+ 	struct clk *clk;
++	s32 npll_vop = -1;
+ 
+ 	rk3288_cru_base = of_iomap(np, 0);
+ 	if (!rk3288_cru_base) {
+@@ -919,6 +945,46 @@ static void __init rk3288_clk_init(struct device_node *np)
+ 		return;
+ 	}
+ 
++	if (!of_property_read_s32(np, "rockchip,npll-for-vop", &npll_vop)) {
++		if ((npll_vop < -1) || (npll_vop > 1)) {
++			pr_warn("%s: invalid VOP to dedicate NPLL to: %d\n",
++				__func__, npll_vop);
++		} else if (npll_vop >= 0) {
++			unsigned int vop_clk_id;
++			const char ** npll_names;
++			const char ** non_npll_names;
++			int i;
++
++			/* Firstly, not-VOP needs to not use npll */
++			mux_pll_src_npll_cpll_gpll_p[0] = "dummy_npll";
++			mux_pll_src_cgn_pll_nonvop_p[2] = "dummy_npll";
++			mux_pll_src_cpll_gll_usb_npll_p[3] = "dummy_npll";
++
++			/* Then the npll VOP needs to only use npll, and the other one not use npll. */
++			if (npll_vop) {
++				vop_clk_id = DCLK_VOP1;
++				npll_names = mux_pll_src_cgn_pll_vop1_p;
++				non_npll_names = mux_pll_src_cgn_pll_vop0_p;
++			} else {
++				vop_clk_id = DCLK_VOP0;
++				npll_names = mux_pll_src_cgn_pll_vop0_p;
++				non_npll_names = mux_pll_src_cgn_pll_vop1_p;
++			}
++			npll_names[0] = "dummy_cpll";
++			npll_names[1] = "dummy_gpll";
++			non_npll_names[2] = "dummy_npll";
++
++			/* Lastly the npll-dedicated-VOP needs to be able to control npll. */
++			for (i = 0; i < ARRAY_SIZE(rk3288_clk_branches); i++) {
++				if (rk3288_clk_branches[i].id == vop_clk_id) {
++					rk3288_clk_branches[i].flags |= CLK_SET_RATE_PARENT;
++					break;
++				}
++			}
++			pr_debug("%s: npll dedicated for VOP %d\n", __func__, npll_vop);
++		}
++	}
++
+ 	ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
+ 	if (IS_ERR(ctx)) {
+ 		pr_err("%s: rockchip clk init failed\n", __func__);
+diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
+index 6b53fff4c..dbda9d281 100644
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -382,6 +382,9 @@ struct clk *rockchip_clk_register_muxgrf(const char *name,
+ 
+ #define PNAME(x) static const char *const x[] __initconst
+ 
++/* For when you want to be able to modify the pointers. */
++#define PNAME_ED(x) static const char * x[] __initdata
++
+ enum rockchip_clk_branch_type {
+ 	branch_composite,
+ 	branch_mux,
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/1010-drm-dw_hdmi-rockchip-better-clock-selection-logic-an.patch

@@ -0,0 +1,424 @@
+From 6c86916e81fa18394d9b57b4af44f9948e100e96 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Sat, 29 Sep 2018 03:02:10 +0200
+Subject: [PATCH 6/6] drm: dw_hdmi-rockchip: better clock selection logic and
+ dts-based rate list
+
+This patch is taken from Urja Rannikko ( @urjaman ) patchset here :
+https://github.com/urjaman/arch-c201/blob/master/linux-c201/0020-RK3288-HDMI-clock-hacks-combined.patch
+https://www.spinics.net/lists/arm-kernel/msg673156.html
+
+The original description was :
+    This contains traces of the following commits from the ChromeOS 3.14
+    tree, which improve RF/EMI performance and detach the clock selection
+    logic from the HDMI PHY configurations, plus support for configuring
+    the allowed clock rates via device tree as they are dependent on
+    PLL configuration and maybe even the PCB layout and other hardware things,
+    eg. interference to wifi or such (EMI).
+
+    Rates that were allowed previous to this patch are added as the fallback
+    list if no dts configuration exists.
+
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Adjust rockchip_mpll_cfg for 146.25
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: expand the informal mpll config
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: add slop to more tables
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: redo rockchip hdmi to allow slop
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Use auto-generated tables
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Fixup the clock to be what we expect
+    CHROMIUM: drm/rockchip: hdmi: adjust cklvl & txlvl for RF/EMI
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Set cur_ctr to 0 always
+    CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Decrease slop
+
+https://www.spinics.net/lists/arm-kernel/msg673163.html
+
+This is the patch that takes into account the new property
+"rockchip,hdmi-rates-hz" that allows the definition of the HDMI
+frequencies in the DTS file.
+This also change a lot of HDMI frequencies definition, so that
+*will* require some extensive testing.
+
+Still, if it works fine, this should make tinkering the HDMI
+frequencies easier, in case you have a very special HDMI screen.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 269 ++++++++++++++++++----------
+ 1 file changed, 175 insertions(+), 94 deletions(-)
+
+diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+index 11309a2a4..740b0aeea 100644
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -49,122 +49,141 @@ struct rockchip_hdmi {
+ 	struct clk *vpll_clk;
+ 	struct clk *grf_clk;
+ 	struct dw_hdmi *hdmi;
++	u32* rates;
++	u32 rates_cnt;
+ };
+ 
++#define CLK_SLOP(clk)		((clk) / 1000)
++#define CLK_PLUS_SLOP(clk)	((clk) + CLK_SLOP(clk))
++
+ #define to_rockchip_hdmi(x)	container_of(x, struct rockchip_hdmi, x)
+ 
++/* These were the rates allowed by the driver before rates list in device tree,
++ * so keep them around as a fallback */
++static const u32 dw_hdmi_fallback_rates[] = {
++	27000000,
++	36000000,
++	40000000,
++	54000000,
++	65000000,
++	66000000,
++	74250000,
++	83500000,
++	106500000,
++	108000000,
++	146250000,
++	148500000
++};
++
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	{
+-		27000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++		30666000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40f3, 0x0000 },
++		},
++	},  {
++		36800000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		36000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++	},  {
++		46000000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		40000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++	},  {
++		61333000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+-	}, {
+-		54000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++	},  {
++		73600000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		65000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++	},  {
++		92000000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		66000000, {
+-			{ 0x013e, 0x0003},
+-			{ 0x217e, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		122666000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+-	}, {
+-		74250000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		147200000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		83500000, {
+-			{ 0x0072, 0x0001},
++	},  {
++		184000000, {
++			{ 0x0051, 0x0002 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		108000000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		226666000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+-	}, {
+-		106500000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		272000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
+-		146250000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++	},  {
++		340000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
+-		148500000, {
+-			{ 0x0051, 0x0003},
+-			{ 0x214c, 0x0003},
+-			{ 0x4064, 0x0003}
++	},  {
++		600000000, {
++			{ 0x1a40, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
++	},  {
+ 		~0UL, {
+-			{ 0x00a0, 0x000a },
+-			{ 0x2001, 0x000f },
+-			{ 0x4002, 0x000f },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
+ 		},
+ 	}
+ };
+ 
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+-	/*      pixelclk    bpp8    bpp10   bpp12 */
++	/*      pixelclk     bpp8    bpp10   bpp12 */
+ 	{
+-		40000000,  { 0x0018, 0x0018, 0x0018 },
+-	}, {
+-		65000000,  { 0x0028, 0x0028, 0x0028 },
+-	}, {
+-		66000000,  { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		74250000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		83500000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		146250000, { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		148500000, { 0x0000, 0x0038, 0x0038 },
+-	}, {
+-		~0UL,      { 0x0000, 0x0000, 0x0000},
+-	}
++		600000000, { 0x0000, 0x0000, 0x0000 },
++	},  {
++		~0UL,      { 0x0000, 0x0000, 0x0000 },
++	},
+ };
+ 
+ static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
+ 	/*pixelclk   symbol   term   vlev*/
+-	{ 74250000,  0x8009, 0x0004, 0x0272},
+-	{ 148500000, 0x802b, 0x0004, 0x028d},
+-	{ 297000000, 0x8039, 0x0005, 0x028d},
+-	{ ~0UL,	     0x0000, 0x0000, 0x0000}
++	{ CLK_PLUS_SLOP(74250000),  0x8009, 0x0004, 0x0272},
++	{ CLK_PLUS_SLOP(165000000), 0x802b, 0x0004, 0x0209},
++	{ CLK_PLUS_SLOP(297000000), 0x8039, 0x0005, 0x028d},
++	{ ~0UL,	                    0x0000, 0x0000, 0x0000}
+ };
+ 
+ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
+ {
+ 	struct device_node *np = hdmi->dev->of_node;
++	int rates_cnt;
+ 
+ 	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ 	if (IS_ERR(hdmi->regmap)) {
+@@ -192,26 +211,55 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
+ 		return PTR_ERR(hdmi->grf_clk);
+ 	}
+ 
++	if ((rates_cnt = of_property_count_u32_elems(np, "rockchip,hdmi-rates-hz")) > 0) {
++		int rv;
++		u32 *rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL);
++		if (!rates)
++			return -ENOMEM;
++		rv = of_property_read_u32_array(np, "rockchip,hdmi-rates-hz", rates, rates_cnt);
++		if (rv)
++			return rv;
++		hdmi->rates = rates;
++		hdmi->rates_cnt = rates_cnt;
++	} else {
++		rates_cnt = ARRAY_SIZE(dw_hdmi_fallback_rates);
++		hdmi->rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL);
++		if (!hdmi->rates)
++			return -ENOMEM;
++		memcpy(hdmi->rates, dw_hdmi_fallback_rates, rates_cnt * sizeof(u32));
++		hdmi->rates_cnt = rates_cnt;
++	}
++
++
+ 	return 0;
+ }
+ 
+ static enum drm_mode_status
+-dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
++dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder,
+ 			    const struct drm_display_mode *mode)
+ {
+-	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
++	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ 	int pclk = mode->clock * 1000;
+-	bool valid = false;
++	int num_rates = hdmi->rates_cnt;
+ 	int i;
+ 
+-	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
+-		if (pclk == mpll_cfg[i].mpixelclock) {
+-			valid = true;
+-			break;
+-		}
++	/*
++	 * Pixel clocks we support are always < 2GHz and so fit in an
++	 * int.  We should make sure source rate does too so we don't get
++	 * overflow when we multiply by 1000.
++	 */
++	if (mode->clock > INT_MAX / 1000)
++		return MODE_BAD;
++
++	for (i = 0; i < num_rates; i++) {
++		int slop = CLK_SLOP(pclk);
++
++		if ((pclk >= hdmi->rates[i] - slop) &&
++		    (pclk <= hdmi->rates[i] + slop))
++			return MODE_OK;
+ 	}
+ 
+-	return (valid) ? MODE_OK : MODE_BAD;
++	return MODE_BAD;
+ }
+ 
+ static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
+@@ -227,7 +275,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
+ 				    const struct drm_display_mode *mode,
+ 				    struct drm_display_mode *adj_mode)
+ {
+-	return true;
++	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
++	int pclk = adj_mode->clock * 1000;
++	int best_diff = INT_MAX;
++	int best_clock = 0;
++	int slop;
++	int i;
++
++	/* Pick the best clock */
++	for (i = 0; i < hdmi->rates_cnt; i++) {
++		int diff = hdmi->rates[i] - pclk;
++
++		if (diff < 0)
++			diff = -diff;
++		if (diff < best_diff) {
++			best_diff = diff;
++			best_clock = hdmi->rates[i];
++
++			/* Bail early if we're exact */
++			if (best_diff == 0)
++				return true;
++		}
++	}
++
++	/* Double check that it's OK */
++	slop = CLK_SLOP(pclk);
++	if ((pclk >= best_clock - slop) && (pclk <= best_clock + slop)) {
++		adj_mode->clock = DIV_ROUND_UP(best_clock, 1000);
++		return true;
++	}
++
++	/* Shoudn't be here; we should have said rate wasn't valid */
++	dev_warn(hdmi->dev, "tried to set invalid rate %d\n", adj_mode->clock);
++	return false;
+ }
+ 
+ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
+@@ -280,6 +360,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
+ }
+ 
+ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
++	.mode_valid = dw_hdmi_rockchip_encoder_mode_valid,
+ 	.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
+ 	.mode_set   = dw_hdmi_rockchip_encoder_mode_set,
+ 	.enable     = dw_hdmi_rockchip_encoder_enable,
+@@ -294,7 +375,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -308,7 +388,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -387,6 +466,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ 	 */
+ 	if (IS_ERR(hdmi->hdmi)) {
+ 		ret = PTR_ERR(hdmi->hdmi);
++		devm_kfree(hdmi->dev, hdmi->rates);
+ 		drm_encoder_cleanup(encoder);
+ 		clk_disable_unprepare(hdmi->vpll_clk);
+ 	}
+@@ -399,6 +479,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
+ {
+ 	struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
+ 
++	devm_kfree(hdmi->dev, hdmi->rates);
+ 	dw_hdmi_unbind(hdmi->hdmi);
+ 	clk_disable_unprepare(hdmi->vpll_clk);
+ }
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/1100-media-Add-JPEG_RAW-format.patch

@@ -0,0 +1,63 @@
+From 1680a655127a62e74cbcfb84782e04a9c55dcf81 Mon Sep 17 00:00:00 2001
+From: Shunqian Zheng <zhengsq@rock-chips.com>
+Date: Wed, 5 Sep 2018 19:00:09 -0300
+Subject: [PATCH 3/6] media: Add JPEG_RAW format
+
+Add V4L2_PIX_FMT_JPEG_RAW format that does not contain
+JPEG header in the output frame.
+
+Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+---
+ Documentation/media/uapi/v4l/pixfmt-compressed.rst | 9 +++++++++
+ drivers/media/v4l2-core/v4l2-ioctl.c               | 1 +
+ include/uapi/linux/videodev2.h                     | 1 +
+ 3 files changed, 11 insertions(+)
+
+diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst
+index d382e7a5..4dffe400 100644
+--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst
++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst
+@@ -23,6 +23,15 @@ Compressed Formats
+       - 'JPEG'
+       - TBD. See also :ref:`VIDIOC_G_JPEGCOMP <VIDIOC_G_JPEGCOMP>`,
+ 	:ref:`VIDIOC_S_JPEGCOMP <VIDIOC_G_JPEGCOMP>`.
++    * .. _V4L2-PIX-FMT-JPEG-RAW:
++
++      - ``V4L2_PIX_FMT_JPEG_RAW``
++      - 'Raw JPEG'
++      - Raw JPEG bitstream, containing a compressed payload. This format
++        contains an image scan, i.e. without any metadata or headers.
++        The user is expected to set the needed metadata such as
++        quantization and entropy encoding tables, via ``V4L2_CID_JPEG``
++        controls, see :ref:`jpeg-control-id`.
+     * .. _V4L2-PIX-FMT-MPEG:
+ 
+       - ``V4L2_PIX_FMT_MPEG``
+diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
+index 54afc9c7..0dcd95f4 100644
+--- a/drivers/media/v4l2-core/v4l2-ioctl.c
++++ b/drivers/media/v4l2-core/v4l2-ioctl.c
+@@ -1301,6 +1301,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
+ 		/* Max description length mask:	descr = "0123456789012345678901234567890" */
+ 		case V4L2_PIX_FMT_MJPEG:	descr = "Motion-JPEG"; break;
+ 		case V4L2_PIX_FMT_JPEG:		descr = "JFIF JPEG"; break;
++		case V4L2_PIX_FMT_JPEG_RAW:	descr = "Raw JPEG"; break;
+ 		case V4L2_PIX_FMT_DV:		descr = "1394"; break;
+ 		case V4L2_PIX_FMT_MPEG:		descr = "MPEG-1/2/4"; break;
+ 		case V4L2_PIX_FMT_H264:		descr = "H.264"; break;
+diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
+index 5d1a3685..f271048c 100644
+--- a/include/uapi/linux/videodev2.h
++++ b/include/uapi/linux/videodev2.h
+@@ -627,6 +627,7 @@ struct v4l2_pix_format {
+ /* compressed formats */
+ #define V4L2_PIX_FMT_MJPEG    v4l2_fourcc('M', 'J', 'P', 'G') /* Motion-JPEG   */
+ #define V4L2_PIX_FMT_JPEG     v4l2_fourcc('J', 'P', 'E', 'G') /* JFIF JPEG     */
++#define V4L2_PIX_FMT_JPEG_RAW v4l2_fourcc('J', 'P', 'G', 'R') /* JFIF JPEG RAW without headers */
+ #define V4L2_PIX_FMT_DV       v4l2_fourcc('d', 'v', 's', 'd') /* 1394          */
+ #define V4L2_PIX_FMT_MPEG     v4l2_fourcc('M', 'P', 'E', 'G') /* MPEG-1/2/4 Multiplexed */
+ #define V4L2_PIX_FMT_H264     v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/1101-media-Add-controls-for-JPEG-quantization-tables.patch

@@ -0,0 +1,153 @@
+From 82da876c36ccc7791d5b20e7ee8b50379f7b19aa Mon Sep 17 00:00:00 2001
+From: Shunqian Zheng <zhengsq@rock-chips.com>
+Date: Wed, 5 Sep 2018 19:00:10 -0300
+Subject: [PATCH 4/6] media: Add controls for JPEG quantization tables
+
+Add V4L2_CID_JPEG_QUANTIZATION compound control to allow userspace
+configure the JPEG quantization tables.
+
+Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
+Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
+---
+ Documentation/media/uapi/v4l/extended-controls.rst | 31 ++++++++++++++++++++++
+ Documentation/media/videodev2.h.rst.exceptions     |  1 +
+ drivers/media/v4l2-core/v4l2-ctrls.c               | 10 +++++++
+ include/uapi/linux/v4l2-controls.h                 | 12 +++++++++
+ include/uapi/linux/videodev2.h                     |  1 +
+ 5 files changed, 55 insertions(+)
+
+diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst
+index 9f7312bf..1335d27d 100644
+--- a/Documentation/media/uapi/v4l/extended-controls.rst
++++ b/Documentation/media/uapi/v4l/extended-controls.rst
+@@ -3354,7 +3354,38 @@ JPEG Control IDs
+     Specify which JPEG markers are included in compressed stream. This
+     control is valid only for encoders.
+ 
++.. _jpeg-quant-tables-control:
+ 
++``V4L2_CID_JPEG_QUANTIZATION (struct)``
++    Specifies the luma and chroma quantization matrices for encoding
++    or decoding a V4L2_PIX_FMT_JPEG_RAW format buffer. The :ref:`itu-t81`
++    specification allows 8-bit quantization coefficients for
++    baseline profile images, and 8-bit or 16-bit for extended profile
++    images. Supporting or not 16-bit precision coefficients is driver-specific.
++    Coefficients must be set in JPEG zigzag scan order.
++
++
++.. c:type:: struct v4l2_ctrl_jpeg_quantization
++
++.. cssclass:: longtable
++
++.. flat-table:: struct v4l2_ctrl_jpeg_quantization
++    :header-rows:  0
++    :stub-columns: 0
++    :widths:       1 1 2
++
++    * - __u8
++      - ``precision``
++      - Specifies the coefficient precision. User shall set 0
++        for 8-bit, and 1 for 16-bit.
++
++    * - __u16
++      - ``luma_quantization_matrix[64]``
++      - Sets the luma quantization table.
++
++    * - __u16
++      - ``chroma_quantization_matrix[64]``
++      - Sets the chroma quantization table.
+ 
+ .. flat-table::
+     :header-rows:  0
+diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions
+index ca9f0edc..a0a38e92 100644
+--- a/Documentation/media/videodev2.h.rst.exceptions
++++ b/Documentation/media/videodev2.h.rst.exceptions
+@@ -129,6 +129,7 @@ replace symbol V4L2_CTRL_TYPE_STRING :c:type:`v4l2_ctrl_type`
+ replace symbol V4L2_CTRL_TYPE_U16 :c:type:`v4l2_ctrl_type`
+ replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type`
+ replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type`
++replace symbol V4L2_CTRL_TYPE_JPEG_QUANTIZATION :c:type:`v4l2_ctrl_type`
+ 
+ # V4L2 capability defines
+ replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities
+diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
+index 599c1cbf..305bd7a9 100644
+--- a/drivers/media/v4l2-core/v4l2-ctrls.c
++++ b/drivers/media/v4l2-core/v4l2-ctrls.c
+@@ -999,6 +999,7 @@ const char *v4l2_ctrl_get_name(u32 id)
+ 	case V4L2_CID_JPEG_RESTART_INTERVAL:	return "Restart Interval";
+ 	case V4L2_CID_JPEG_COMPRESSION_QUALITY:	return "Compression Quality";
+ 	case V4L2_CID_JPEG_ACTIVE_MARKER:	return "Active Markers";
++	case V4L2_CID_JPEG_QUANTIZATION:	return "JPEG Quantization Tables";
+ 
+ 	/* Image source controls */
+ 	/* Keep the order of the 'case's the same as in v4l2-controls.h! */
+@@ -1286,6 +1287,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
+ 	case V4L2_CID_DETECT_MD_REGION_GRID:
+ 		*type = V4L2_CTRL_TYPE_U8;
+ 		break;
++	case V4L2_CID_JPEG_QUANTIZATION:
++		*type = V4L2_CTRL_TYPE_JPEG_QUANTIZATION;
++		break;
+ 	case V4L2_CID_DETECT_MD_THRESHOLD_GRID:
+ 		*type = V4L2_CTRL_TYPE_U16;
+ 		break;
+@@ -1612,6 +1616,9 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx,
+ 			return -ERANGE;
+ 		return 0;
+ 
++	case V4L2_CTRL_TYPE_JPEG_QUANTIZATION:
++		return 0;
++
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -2133,6 +2140,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl,
+ 	case V4L2_CTRL_TYPE_U32:
+ 		elem_size = sizeof(u32);
+ 		break;
++	case V4L2_CTRL_TYPE_JPEG_QUANTIZATION:
++		elem_size = sizeof(struct v4l2_ctrl_jpeg_quantization);
++		break;
+ 	default:
+ 		if (type < V4L2_CTRL_COMPOUND_TYPES)
+ 			elem_size = sizeof(s32);
+diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
+index e4ee10ee..856b3325 100644
+--- a/include/uapi/linux/v4l2-controls.h
++++ b/include/uapi/linux/v4l2-controls.h
+@@ -987,6 +987,18 @@ enum v4l2_jpeg_chroma_subsampling {
+ #define	V4L2_JPEG_ACTIVE_MARKER_DQT		(1 << 17)
+ #define	V4L2_JPEG_ACTIVE_MARKER_DHT		(1 << 18)
+ 
++#define V4L2_CID_JPEG_QUANTIZATION		(V4L2_CID_JPEG_CLASS_BASE + 5)
++struct v4l2_ctrl_jpeg_quantization {
++	/* ITU-T.81 specifies two quantization coefficient precisions:
++	 * 8-bit for baseline profile,
++	 * 8-bit or 16-bit for extended profile.
++	 *
++	 * User shall set "precision" to 0 for 8-bit and 1 for 16-bit.
++	 */
++	__u8	precision;
++	__u16	luma_quantization_matrix[64];
++	__u16	chroma_quantization_matrix[64];
++};
+ 
+ /* Image source controls */
+ #define V4L2_CID_IMAGE_SOURCE_CLASS_BASE	(V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900)
+diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
+index f271048c..e998d074 100644
+--- a/include/uapi/linux/videodev2.h
++++ b/include/uapi/linux/videodev2.h
+@@ -1630,6 +1630,7 @@ enum v4l2_ctrl_type {
+ 	V4L2_CTRL_TYPE_U8	     = 0x0100,
+ 	V4L2_CTRL_TYPE_U16	     = 0x0101,
+ 	V4L2_CTRL_TYPE_U32	     = 0x0102,
++	V4L2_CTRL_TYPE_JPEG_QUANTIZATION = 0x0103,
+ };
+ 
+ /*  Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/2012-ARM-DTSI-rk3288-Add-the-RGA-node.patch

@@ -1,40 +0,0 @@
-From 3fe37d29b53e3d06c8f4314cfc113bfa679f67eb Mon Sep 17 00:00:00 2001
-From: Myy Miouyouyou <myy@miouyouyou.fr>
-Date: Thu, 19 Oct 2017 21:48:05 +0200
-Subject: [PATCH 15/28] ARM: DTSI: rk3288.dtsi: Add the RGA node
-
-Imported from @wzyy2 patches.
-
-Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
-index 10ecebb4..455446f6 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
-@@ -1159,6 +1159,20 @@
- 		};
- 	};
- 
-+	rga: rga@ff920000 {
-+		compatible = "rockchip,rk3288-rga";
-+		reg = <0x0 0xff920000 0x0 0x180>;
-+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "rga";
-+		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
-+		clock-names = "aclk", "hclk", "sclk";
-+		power-domains = <&power RK3288_PD_VIO>;
-+		resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
-+
-+		reset-names = "core", "axi", "ahb";
-+		status = "disabled";
-+	};
-+
- 	vpu_mmu: iommu@ff9a0800 {
- 		compatible = "rockchip,iommu";
- 		reg = <0x0 0xff9a0800 0x0 0x100>;
--- 
-2.11.0
-

buildroot-external/board/asus/tinker/patches/linux/2015-ARM-DTS-rk3288-tinker-Improving-the-CPU-max-volt.patch

@@ -0,0 +1,29 @@
+From d4775f623b25009039a8ef3f28332033c7766ecc Mon Sep 17 00:00:00 2001
+From: Myy Miouyouyou <myy@miouyouyou.fr>
+Date: Thu, 19 Oct 2017 22:20:33 +0200
+Subject: [PATCH 19/28] ARM: DTS: rk3288-tinker.dts: Improving the CPU max
+ voltage
+
+Taken from the various patches provided by @TonyMac32 .
+
+Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rk3288-tinker.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
+index c552fd95..4ce94698 100644
+--- a/arch/arm/boot/dts/rk3288-tinker.dts
++++ b/arch/arm/boot/dts/rk3288-tinker.dts
+@@ -243,7 +243,7 @@
+ 				regulator-always-on;
+ 				regulator-boot-on;
+ 				regulator-min-microvolt = <750000>;
+-				regulator-max-microvolt = <1350000>;
++				regulator-max-microvolt = <1450000>;
+ 				regulator-name = "vdd_arm";
+ 				regulator-ramp-delay = <6000>;
+ 				regulator-state-mem {
+-- 
+2.11.0
+

buildroot-external/board/asus/tinker/patches/linux/2017-ARM-DTS-rk3288-tinker-Defined-the-I2C-interfaces.patch

@@ -30,12 +30,12 @@ index 90c1a251..67a3ce6f 100644
 +	afc0:af-controller@0 {
 +		status = "okay";
 +		compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
-+		reg = <0x0 0x0c>;
++		reg = <0x0c>;
 +	};
 +
 +	eeprom:m24c08@50 {
 +		compatible = "at,24c08";
-+		reg = <0x0 0x50>;
++		reg = <0x50>;
 +	};
 +};
 +

buildroot-external/board/asus/tinker/patches/linux/2020-ARM-DTS-rk3288-tinker-Defining-the-SPI-interface.patch

@@ -1,49 +0,0 @@
-From 14f951ca2d354ad8fd068d0f3d8648d5c0d1e60e Mon Sep 17 00:00:00 2001
-From: Myy Miouyouyou <myy@miouyouyou.fr>
-Date: Thu, 19 Oct 2017 22:40:26 +0200
-Subject: [PATCH 23/28] ARM: DTS: rk3288-tinker.dts: Defining the SPI interface
-
-Taken from, and tested by @TonyMac32 .
-
-Well, the original one was tested by him but I had to adapt the
-registers definitions to the new 64-bits LPAE-compliant syntax.
-
-Therefore that *might* break, along with a few other patches.
-
-Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
----
- arch/arm/boot/dts/rk3288-tinker.dts | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index 6f4c0843..f4b4525c 100644
---- a/arch/arm/boot/dts/rk3288-tinker.dts
-+++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -471,6 +471,24 @@
- 
- };
- 
-+&spi2 {
-+	status = "okay";
-+	max-freq = <50000000>;
-+	spidev@0 {
-+		compatible = "rockchip,spi_tinker";
-+		reg = <0x0 0>;
-+		spi-max-frequency = <50000000>;
-+		spi-cpha = <1>;
-+	};
-+	spidev@1 {
-+		compatible = "rockchip,spi_tinker";
-+		reg = <0x0 1>;
-+		spi-max-frequency = <50000000>;
-+		spi-cpha = <1>;
-+	};
-+};
-+
-+
- &pinctrl {
- 	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
- 		drive-strength = <8>;
--- 
-2.11.0
-

buildroot-external/board/asus/tinker/patches/linux/2025-ARM-DTSI-rk3288-Renamed-the-VPU-services-clocks.patch

@@ -0,0 +1,39 @@
+From 29ef524e8890bbfd24602a61e14234259df92349 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Mon, 25 Jun 2018 17:05:37 +0200
+Subject: [PATCH 25/26] ARM: DTSI: rk3288: Renamed the VPU services clocks
+
+In order to conform to the naming scheme used in the whole DTSI.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rk3288.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
+index 796609e3..45ec4e89 100644
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -1242,7 +1242,7 @@
+ 			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ 		interrupt-names = "irq_enc", "irq_dec";
+ 		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+-		clock-names = "aclk_vcodec", "hclk_vcodec";
++		clock-names = "aclk", "iface";
+ 		power-domains = <&power RK3288_PD_VIDEO>;
+ 		rockchip,grf = <&grf>;
+ 		resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+@@ -1277,8 +1277,8 @@
+ 			<&cru SCLK_HEVC_CORE>,
+ 			<&cru SCLK_HEVC_CABAC>;
+ 		clock-names =
+-			"aclk_vcodec",
+-			"hclk_vcodec",
++			"aclk",
++			"iface",
+ 			"clk_core",
+ 			"clk_cabac";
+ 		/*
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/2026-ARM-DTSI-rk3288-Set-the-VPU-MMU-power-domains.patch

@@ -0,0 +1,56 @@
+From d3d3fe433d9038dcd1a98f4d6711c0777ed06703 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Mon, 25 Jun 2018 17:08:32 +0200
+Subject: [PATCH 26/26] ARM: DTSI: rk3288: Set the VPU MMU power domains
+
+Without that, the auto-activation of the VPU hardware IOMMU fails
+when enabling the hardware, before the "probe" phase of its device
+driver.
+
+Basically, when loading a "of_platform" device driver targeting
+the VPU devices, you'll get these errors without this patch :
+
+[12753.996950] rk_iommu ff9c0440.iommu: Error during raw reset. MMU_DTE_ADDR is not functioning
+[12754.007483] rk_iommu ff9c0440.iommu: Disable stall request timed out, status: 0xffffffff
+[12754.026652] rk_iommu ff9c0440.iommu: Disable paging request timed out, status: 0xffffffff
+[12754.045975] rk_iommu ff9c0440.iommu: Disable stall request timed out, status: 0xffffffff
+
+When using this patch, the errors disappear.
+
+This seems to be due to the IOMMU device sharing the same power domain
+than the device.
+When loading an "of_platform" driver, the kernel logic seems to try
+enabling the associated IOMMU device before letting the driver handles
+anything with the actual VPU hardware.
+It appears that setting the power domain of the VPU IOMMU nodes let the
+IOMMU driver enable the IOMMU shared power domain, and make the IOMMU
+device useable.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rk3288.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
+index 45ec4e89..46e1b8e2 100644
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -1230,6 +1230,7 @@
+ 		interrupt-names = "vpu_mmu";
+ 		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ 		clock-names = "aclk", "iface";
++		power-domains = <&power RK3288_PD_VIDEO>;
+ 		#iommu-cells = <0>;
+ 		status = "disabled";
+ 	};
+@@ -1262,6 +1263,7 @@
+ 		interrupt-names = "hevc_mmu";
+ 		clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
+ 		clock-names = "aclk", "iface";
++		power-domains = <&power RK3288_PD_HEVC>;
+ 		#iommu-cells = <0>;
+ 		status = "disabled";
+ 	};
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/2027-ARM-dtsi-The-VPU-service-as-defined-in-the-V4L2-driv.patch

@@ -0,0 +1,43 @@
+From 7f8607ba9a20f8ddb5c24559d9b875af762d4717 Mon Sep 17 00:00:00 2001
+From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
+Date: Tue, 11 Sep 2018 02:55:55 +0200
+Subject: [PATCH] ARM: dtsi: The VPU service as defined in the V4L2 driver
+
+Let's try the V4L2 road.
+They've got a lot of things ready, like an entire H264
+movie with the V4L2 data of *every frame*.
+
+That might help in this endless endeavour.
+
+Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
+---
+ arch/arm/boot/dts/rk3288.dtsi | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
+index 72c36af6..d23c7fa5 100644
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -1246,7 +1246,18 @@
+ 		clock-names = "aclk", "iface";
+ 		power-domains = <&power RK3288_PD_VIDEO>;
+ 		#iommu-cells = <0>;
+-		status = "disabled";
++	};
++
++	vpu: video-codec@ff9a0000 {
++		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
++		clock-names = "aclk", "hclk";
++		compatible = "rockchip,rk3288-vpu";
++		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
++			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "vepu", "vdpu";
++		iommus = <&vpu_mmu>;
++		power-domains = <&power RK3288_PD_VIDEO>;
++		reg = <0x0 0xff9a0000 0x0 0x800>;
+ 	};
+ 
+ 	hevc_mmu: iommu@ff9c0440 {
+-- 
+2.16.4
+

buildroot-external/board/asus/tinker/patches/linux/261_gpiomem_driver.patch

@@ -1,364 +0,0 @@
-diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
-index c28dca0..d9df49d 100644
---- a/drivers/char/Kconfig
-+++ b/drivers/char/Kconfig
-@@ -6,6 +6,7 @@
- menu "Character devices"
- 
- source "drivers/tty/Kconfig"
-+source "drivers/char/rockchip/Kconfig"
- 
- config DEVMEM
- 	bool "/dev/mem virtual device support"
-diff --git a/drivers/char/Makefile b/drivers/char/Makefile
-index 7dc3abe..5d43b1d 100644
---- a/drivers/char/Makefile
-+++ b/drivers/char/Makefile
-@@ -60,3 +60,5 @@ js-rtc-y = rtc.o
- obj-$(CONFIG_TILE_SROM)		+= tile-srom.o
- obj-$(CONFIG_XILLYBUS)		+= xillybus/
- obj-$(CONFIG_POWERNV_OP_PANEL)	+= powernv-op-panel.o
-+
-+obj-$(CONFIG_RK_CHAR_DRIVERS)	+= rockchip/
-diff --git a/drivers/char/rockchip/Kconfig b/drivers/char/rockchip/Kconfig
-new file mode 100644
-index 0000000..867d51e
---- /dev/null
-+++ b/drivers/char/rockchip/Kconfig
-@@ -0,0 +1,16 @@
-+#
-+# Broadcom char driver config
-+#
-+
-+menuconfig RK_CHAR_DRIVERS
-+	bool "Rockchip Char Drivers"
-+	help
-+	  Rockchip's char drivers
-+
-+config RK3288_DEVGPIOMEM
-+	tristate "/dev/gpiomem rootless GPIO access via mmap() on the RK3288"
-+	default y
-+	help
-+		Provides users with root-free access to the GPIO registers
-+		on the 3288. Calling mmap(/dev/gpiomem) will map the GPIO
-+		register page to the user's pointer.
-diff --git a/drivers/char/rockchip/Makefile b/drivers/char/rockchip/Makefile
-new file mode 100644
-index 0000000..e7df7f2
---- /dev/null
-+++ b/drivers/char/rockchip/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_RK3288_DEVGPIOMEM)+= rk3288-gpiomem.o
-diff --git a/drivers/char/rockchip/rk3288-gpiomem.c b/drivers/char/rockchip/rk3288-gpiomem.c
-new file mode 100644
-index 0000000..c289041
---- /dev/null
-+++ b/drivers/char/rockchip/rk3288-gpiomem.c
-@@ -0,0 +1,307 @@
-+/**
-+ * GPIO memory device driver
-+ *
-+ * Creates a chardev /dev/gpiomem which will provide user access to
-+ * the rk3288's GPIO registers when it is mmap()'d.
-+ * No longer need root for user GPIO access, but without relaxing permissions
-+ * on /dev/mem.
-+ *
-+ * Written by Luke Wren <luke@raspberrypi.org>
-+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
-+ *
-+ * Redistribution and use in source and binary forms, with or without
-+ * modification, are permitted provided that the following conditions
-+ * are met:
-+ * 1. Redistributions of source code must retain the above copyright
-+ *    notice, this list of conditions, and the following disclaimer,
-+ *    without modification.
-+ * 2. Redistributions in binary form must reproduce the above copyright
-+ *    notice, this list of conditions and the following disclaimer in the
-+ *    documentation and/or other materials provided with the distribution.
-+ * 3. The names of the above-listed copyright holders may not be used
-+ *    to endorse or promote products derived from this software without
-+ *    specific prior written permission.
-+ *
-+ * ALTERNATIVELY, this software may be distributed under the terms of the
-+ * GNU General Public License ("GPL") version 2, as published by the Free
-+ * Software Foundation.
-+ *
-+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+/*
-+ * Ported to rk3288 from Jörg Wolff, 2017
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/mm.h>
-+#include <linux/slab.h>
-+#include <linux/cdev.h>
-+#include <linux/pagemap.h>
-+#include <linux/io.h>
-+
-+#define DEVICE_NAME "rk3288-gpiomem"
-+#define DRIVER_NAME "gpiomem-rk3288"
-+#define DEVICE_MINOR 0
-+
-+struct rk3288_gpiomem_instance {
-+	unsigned long gpio_regs_phys;
-+	struct device *dev;
-+};
-+
-+static struct cdev rk3288_gpiomem_cdev;
-+static dev_t rk3288_gpiomem_devid;
-+static struct class *rk3288_gpiomem_class;
-+static struct device *rk3288_gpiomem_dev;
-+static struct rk3288_gpiomem_instance *inst;
-+
-+
-+/****************************************************************************
-+*
-+*   GPIO mem chardev file ops
-+*
-+***************************************************************************/
-+
-+static int rk3288_gpiomem_open(struct inode *inode, struct file *file)
-+{
-+	int dev = iminor(inode);
-+	int ret = 0;
-+
-+	if (dev != DEVICE_MINOR) {
-+		dev_err(inst->dev, "Unknown minor device: %d", dev);
-+		ret = -ENXIO;
-+	}
-+	return ret;
-+}
-+
-+static int rk3288_gpiomem_release(struct inode *inode, struct file *file)
-+{
-+	int dev = iminor(inode);
-+	int ret = 0;
-+
-+	if (dev != DEVICE_MINOR) {
-+		dev_err(inst->dev, "Unknown minor device %d", dev);
-+		ret = -ENXIO;
-+	}
-+	return ret;
-+}
-+
-+static const struct vm_operations_struct rk3288_gpiomem_vm_ops = {
-+#ifdef CONFIG_HAVE_IOREMAP_PROT
-+	.access = generic_access_phys
-+#endif
-+};
-+static int address_is_allowed(unsigned long pfn, unsigned long size)
-+{
-+    unsigned long address = pfn << PAGE_SHIFT;
-+
-+    dev_info(inst->dev, "address_is_allowed.pfn: 0x%08lx", address);
-+
-+    switch(address) {
-+
-+        case 0xff750000:
-+        case 0xff760000:
-+        case 0xff780000:
-+        case 0xff790000:
-+        case 0xff7a0000:
-+        case 0xff7b0000:
-+        case 0xff7c0000:
-+        case 0xff7d0000:
-+        case 0xff7e0000:
-+        case 0xff7f0000:
-+        case 0xff7f2000:
-+        case 0xff770000:
-+        case 0xff730000:
-+        case 0xff680000:
-+            dev_info(inst->dev, "address_is_allowed.return 1");
-+            return 1;
-+            break; 
-+        default :
-+            dev_info(inst->dev, "address_is_allowed.return 0");
-+	        return 0;
-+    }
-+}
-+
-+static int rk3288_gpiomem_mmap(struct file *file, struct vm_area_struct *vma)
-+{
-+
-+    size_t size;
-+
-+	size = vma->vm_end - vma->vm_start;
-+
-+
-+	if (!address_is_allowed(vma->vm_pgoff, size))
-+		return -EPERM;
-+
-+	vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff,
-+						 size,
-+						 vma->vm_page_prot);
-+
-+	vma->vm_ops =  &rk3288_gpiomem_vm_ops;
-+
-+	/* Remap-pfn-range will mark the range VM_IO */
-+	if (remap_pfn_range(vma,
-+			    vma->vm_start,
-+			    vma->vm_pgoff,
-+			    size,
-+			    vma->vm_page_prot)) {
-+		return -EAGAIN;
-+	}
-+
-+	return 0;
-+}
-+
-+static const struct file_operations
-+rk3288_gpiomem_fops = {
-+	.owner = THIS_MODULE,
-+	.open = rk3288_gpiomem_open,
-+	.release = rk3288_gpiomem_release,
-+	.mmap = rk3288_gpiomem_mmap,
-+};
-+
-+static int rk3288_gpiomem_dev_uevent(struct device *dev, struct kobj_uevent_env *env)
-+{
-+    add_uevent_var(env, "DEVMODE=%#o", 0660);
-+    return 0;
-+}
-+
-+ /****************************************************************************
-+*
-+*   Probe and remove functions
-+*
-+***************************************************************************/
-+
-+
-+static int rk3288_gpiomem_probe(struct platform_device *pdev)
-+{
-+	int err;
-+	void *ptr_err;
-+	struct device *dev = &pdev->dev;
-+	struct resource *ioresource;
-+
-+	/* Allocate buffers and instance data */
-+
-+	inst = kzalloc(sizeof(struct rk3288_gpiomem_instance), GFP_KERNEL);
-+
-+	if (!inst) {
-+		err = -ENOMEM;
-+		goto failed_inst_alloc;
-+	}
-+
-+	inst->dev = dev;
-+
-+	ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (ioresource) {
-+		inst->gpio_regs_phys = ioresource->start;
-+	} else {
-+		dev_err(inst->dev, "failed to get IO resource");
-+		err = -ENOENT;
-+		goto failed_get_resource;
-+	}
-+
-+	/* Create character device entries */
-+
-+	err = alloc_chrdev_region(&rk3288_gpiomem_devid,
-+				  DEVICE_MINOR, 1, DEVICE_NAME);
-+	if (err != 0) {
-+		dev_err(inst->dev, "unable to allocate device number");
-+		goto failed_alloc_chrdev;
-+	}
-+	cdev_init(&rk3288_gpiomem_cdev, &rk3288_gpiomem_fops);
-+	rk3288_gpiomem_cdev.owner = THIS_MODULE;
-+	err = cdev_add(&rk3288_gpiomem_cdev, rk3288_gpiomem_devid, 1);
-+	if (err != 0) {
-+		dev_err(inst->dev, "unable to register device");
-+		goto failed_cdev_add;
-+	}
-+
-+	/* Create sysfs entries */
-+
-+	rk3288_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME);
-+	ptr_err = rk3288_gpiomem_class;
-+	if (IS_ERR(ptr_err))
-+		goto failed_class_create;
-+	rk3288_gpiomem_class->dev_uevent = rk3288_gpiomem_dev_uevent;
-+	rk3288_gpiomem_dev = device_create(rk3288_gpiomem_class, NULL,
-+					rk3288_gpiomem_devid, NULL,
-+					"gpiomem");
-+	ptr_err = rk3288_gpiomem_dev;
-+	if (IS_ERR(ptr_err))
-+		goto failed_device_create;
-+
-+	dev_info(inst->dev, "Initialised: Registers at 0x%08lx",
-+		inst->gpio_regs_phys);
-+
-+	return 0;
-+
-+failed_device_create:
-+	class_destroy(rk3288_gpiomem_class);
-+failed_class_create:
-+	cdev_del(&rk3288_gpiomem_cdev);
-+	err = PTR_ERR(ptr_err);
-+failed_cdev_add:
-+	unregister_chrdev_region(rk3288_gpiomem_devid, 1);
-+failed_alloc_chrdev:
-+failed_get_resource:
-+	kfree(inst);
-+failed_inst_alloc:
-+	dev_err(inst->dev, "could not load rk3288_gpiomem");
-+	return err;
-+}
-+
-+static int rk3288_gpiomem_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = inst->dev;
-+
-+	kfree(inst);
-+	device_destroy(rk3288_gpiomem_class, rk3288_gpiomem_devid);
-+	class_destroy(rk3288_gpiomem_class);
-+	cdev_del(&rk3288_gpiomem_cdev);
-+	unregister_chrdev_region(rk3288_gpiomem_devid, 1);
-+
-+	dev_info(dev, "GPIO mem driver removed - OK");
-+	return 0;
-+}
-+
-+ /****************************************************************************
-+*
-+*   Register the driver with device tree
-+*
-+***************************************************************************/
-+
-+static const struct of_device_id rk3288_gpiomem_of_match[] = {
-+	{.compatible = "rockchip,rk3288-gpiomem",},
-+	{ /* sentinel */ },
-+};
-+
-+MODULE_DEVICE_TABLE(of, rk3288_gpiomem_of_match);
-+
-+static struct platform_driver rk3288_gpiomem_driver = {
-+	.probe = rk3288_gpiomem_probe,
-+	.remove = rk3288_gpiomem_remove,
-+	.driver = {
-+		   .name = DRIVER_NAME,
-+		   .owner = THIS_MODULE,
-+		   .of_match_table = rk3288_gpiomem_of_match,
-+		   },
-+};
-+
-+module_platform_driver(rk3288_gpiomem_driver);
-+
-+MODULE_ALIAS("platform:gpiomem-rk3288");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace");
-+MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");

buildroot-external/board/asus/tinker/patches/linux/3000_RK3288-Tinkerboard-add-1.7_1.8Ghz_OPP.patch

@@ -0,0 +1,45 @@
+diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
+index 2601316da..08ec7aa4b 100644
+--- a/arch/arm/boot/dts/rk3288-tinker.dts
++++ b/arch/arm/boot/dts/rk3288-tinker.dts
+@@ -210,8 +210,8 @@
+ 			vdd_cpu: DCDC_REG1 {
+ 				regulator-always-on;
+ 				regulator-boot-on;
+-				regulator-min-microvolt = <750000>;
+-				regulator-max-microvolt = <1450000>;
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1500000>;
+ 				regulator-name = "vdd_arm";
+ 				regulator-ramp-delay = <6000>;
+ 				regulator-state-mem {
+@@ -222,8 +222,8 @@
+ 			vdd_gpu: DCDC_REG2 {
+ 				regulator-always-on;
+ 				regulator-boot-on;
+-				regulator-min-microvolt = <850000>;
+-				regulator-max-microvolt = <1250000>;
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1500000>;
+ 				regulator-name = "vdd_gpu";
+ 				regulator-ramp-delay = <6000>;
+ 				regulator-state-mem {
+diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
+index 22bcaaa29..2fcd46098 100644
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -149,6 +149,14 @@
+ 			opp-hz = /bits/ 64 <1608000000>;
+ 			opp-microvolt = <1350000>;
+ 		};
++		opp@1704000000 {
++			opp-hz = /bits/ 64 <1704000000>;
++			opp-microvolt = <1350000>;
++		};
++		opp@1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1400000>;
++		};
+ 	};
+ 
+ 	amba {

buildroot-external/board/asus/tinker/patches/linux/3001_Tinkerboard-4.19-audio.patch

@@ -1,19 +1,19 @@
 diff --git a/sound/usb/card.c b/sound/usb/card.c
-index 23d1d23..98610ae 100644
+index 2bfe4e80a..cea93aaf5 100644
 --- a/sound/usb/card.c
 +++ b/sound/usb/card.c
-@@ -434,6 +434,14 @@ static int snd_usb_audio_create(struct usb_interface *intf,
+@@ -382,6 +382,14 @@ static void usb_audio_make_shortname(struct usb_device *dev,
  	}
- 	strim(card->shortname);
  
+ 	strim(card->shortname);
++
 +	/* Tinker Board ALC4040 CODEC	*/
 +
 +	if(USB_ID_VENDOR(chip->usb_id) == 0x0bda &&
 +		USB_ID_PRODUCT(chip->usb_id) == 0x481a) {
 +			strlcat(card->shortname, " OnBoard", sizeof(card->shortname));
-+	} 
-+
-+
- 	/* retrieve the vendor and device strings as longname */
- 	if (quirk && quirk->vendor_name && *quirk->vendor_name) {
- 		len = strlcpy(card->longname, quirk->vendor_name, sizeof(card->longname));
++	}
++	
+ }
+ 
+ static void usb_audio_make_longname(struct usb_device *dev,

buildroot-external/board/asus/tinker/patches/linux/3004-Tinkerboard-overclocking-operation.patch

@@ -1,122 +0,0 @@
-diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index 07b4af4..f71fa24
---- a/arch/arm/boot/dts/rk3288-tinker.dts
-+++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -175,10 +175,83 @@
- 		status = "okay";
- 	};
-
-+	cpu0_opp_table: opp_table {
-+		compatible = "operating-points-v2";
-+		opp-shared;
-+
-+		opp@600000000 {
-+			opp-hz = /bits/ 64 <600000000>;
-+			opp-microvolt = <900000>;
-+		};
-+		opp@816000000 {
-+			opp-hz = /bits/ 64 <816000000>;
-+			opp-microvolt = <1000000>;
-+		};
-+		opp@1008000000 {
-+			opp-hz = /bits/ 64 <1008000000>;
-+			opp-microvolt = <1050000>;
-+		};
-+		opp@1200000000 {
-+			opp-hz = /bits/ 64 <1200000000>;
-+			opp-microvolt = <1100000>;
-+		};
-+		opp@1416000000 {
-+			opp-hz = /bits/ 64 <1416000000>;
-+			opp-microvolt = <1200000>;
-+		};
-+		opp@1512000000 {
-+			opp-hz = /bits/ 64 <1512000000>;
-+			opp-microvolt = <1250000>;
-+		};
-+		opp@1608000000 {
-+			opp-hz = /bits/ 64 <1608000000>;
-+			opp-microvolt = <1300000>;
-+		};
-+		opp@1704000000 {
-+			opp-hz = /bits/ 64 <1704000000>;
-+			opp-microvolt = <1350000>;
-+		};
-+		opp@1800000000 {
-+			opp-hz = /bits/ 64 <1800000000>;
-+			opp-microvolt = <1400000>;
-+		};
-+		/* boot-only frequencies below */
-+		opp@1896000000 {
-+			opp-hz = /bits/ 64 <1896000000>;
-+			opp-microvolt = <1425000>;
-+			turbo-mode;
-+		};
-+		opp@1920000000 {
-+			opp-hz = /bits/ 64 <1920000000>;
-+			opp-microvolt = <1425000>;
-+			turbo-mode;
-+		};
-+		opp@1992000000 {
-+			opp-hz = /bits/ 64 <1992000000>;
-+			opp-microvolt = <1450000>;
-+			turbo-mode;
-+		};
-+		opp@2016000000 {
-+			opp-hz = /bits/ 64 <2016000000>;
-+			opp-microvolt = <1475000>;
-+			turbo-mode;
-+		};
-+		opp@2040000000 {
-+			opp-hz = /bits/ 64 <2040000000>;
-+			opp-microvolt = <1475000>;
-+			turbo-mode;
-+		};
-+		opp@2064000000 {
-+			opp-hz = /bits/ 64 <2064000000>;
-+			opp-microvolt = <1475000>;
-+			turbo-mode;
-+		};
-+	};
- };
-
- &cpu0 {
- 	cpu0-supply = <&vdd_cpu>;
-+	operating-points-v2 = <&cpu0_opp_table>;
- };
-
- &gmac {
-@@ -345,8 +345,8 @@
- 			vdd_cpu: DCDC_REG1 {
- 				regulator-always-on;
- 				regulator-boot-on;
--				regulator-min-microvolt = <750000>;
--				regulator-max-microvolt = <1350000>;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1500000>;
- 				regulator-name = "vdd_arm";
- 				regulator-ramp-delay = <6000>;
- 				regulator-state-mem {
-@@ -357,8 +357,8 @@
- 			vdd_gpu: DCDC_REG2 {
- 				regulator-always-on;
- 				regulator-boot-on;
--				regulator-min-microvolt = <850000>;
--				regulator-max-microvolt = <1250000>;
-+				regulator-min-microvolt = <712500>;
-+				regulator-max-microvolt = <1500000>;
- 				regulator-name = "vdd_gpu";
- 				regulator-ramp-delay = <6000>;
- 				regulator-state-mem {
-@@ -652,6 +755,11 @@
- };
-
- &usb_otg {
-+	/*
-+	 * The otg controller is the only system power source,
-+	 * so needs to always stay in device mode.
-+	 */
-+	dr_mode = "peripheral";
- 	status= "okay";
- };
-

buildroot-external/board/asus/tinker/patches/linux/4001-rockchip-Fix-dai_name-for-HDMI-codec-to-the-asoc-tree.patch

@@ -1,13 +0,0 @@
-diff --git a/sound/soc/rockchip/rk3288_hdmi_analog.c b/sound/soc/rockchip/rk3288_hdmi_analog.c
-index fa44e3901336..929b3fe289b0 100644
---- a/sound/soc/rockchip/rk3288_hdmi_analog.c
-+++ b/sound/soc/rockchip/rk3288_hdmi_analog.c
-@@ -155,7 +155,7 @@ static struct snd_soc_dai_link_component rk_codecs[] = {
- 	{ },
- 	{
- 		.name = "hdmi-audio-codec.2.auto",
--		.dai_name = "hdmi-hifi.0",
-+		.dai_name = "i2s-hifi",
- 	},
- };
- 

buildroot-external/board/asus/tinker/patches/linux/5000-add-link-for-miniarm-dtb-file.patch

@@ -1,20 +0,0 @@
-diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
-index eff87a3..58fade2 100644
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
- 	rk3288-r89.dtb \
- 	rk3288-rock2-square.dtb \
- 	rk3288-tinker.dtb \
-+	rk3288-miniarm.dtb \
- 	rk3288-veyron-brain.dtb \
- 	rk3288-veyron-jaq.dtb \
- 	rk3288-veyron-jerry.dtb \
-diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
-new file mode 120000
-index 0000000..830ab68
---- /dev/null
-+++ b/arch/arm/boot/dts/rk3288-miniarm.dts
-@@ -0,0 +1 @@
-+rk3288-tinker.dts
-\ No newline at end of file

buildroot-external/board/asus/tinker/patches/linux/ARM-DTSI-rk3288-add-usbphy-reset.patch

@@ -0,0 +1,31 @@
+diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
+index 0840ffb3..5393f2cd 100644
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -894,6 +894,8 @@
+ 				reg = <0x320>;
+ 				clocks = <&cru SCLK_OTGPHY0>;
+ 				clock-names = "phyclk";
++				resets = <&cru SRST_USBOTG_PHY>;
++				reset-names = "phy-reset";
+ 				#clock-cells = <0>;
+ 			};
+ 
+@@ -902,6 +904,8 @@
+ 				reg = <0x334>;
+ 				clocks = <&cru SCLK_OTGPHY1>;
+ 				clock-names = "phyclk";
++				resets = <&cru SRST_USBHOST0_PHY>;
++				reset-names = "phy-reset";
+ 				#clock-cells = <0>;
+ 			};
+ 
+@@ -910,6 +914,8 @@
+ 				reg = <0x348>;
+ 				clocks = <&cru SCLK_OTGPHY2>;
+ 				clock-names = "phyclk";
++				resets = <&cru SRST_USBHOST1_PHY>;
++				reset-names = "phy-reset";
+ 				#clock-cells = <0>;
+ 			};
+ 		};

buildroot-external/board/asus/tinker/patches/linux/assert-phy-reset-when-waking-up-in-rk3288-platform.patch

@@ -0,0 +1,68 @@
+diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
+index cc9c93af..3ff41d87 100644
+--- a/drivers/usb/dwc2/core.h
++++ b/drivers/usb/dwc2/core.h
+@@ -1021,6 +1021,7 @@ struct dwc2_hsotg {
+ 	u16 frame_number;
+ 
+ 	struct phy *phy;
++	struct work_struct phy_rst_work;
+ 	struct usb_phy *uphy;
+ 	struct dwc2_hsotg_plat *plat;
+ 	struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
+diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
+index 19ae2595..f1270bf1 100644
+--- a/drivers/usb/dwc2/core_intr.c
++++ b/drivers/usb/dwc2/core_intr.c
+@@ -396,6 +396,7 @@ static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
+ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
+ {
+ 	int ret;
++	struct device_node *np = hsotg->dev->of_node;
+ 
+ 	/* Clear interrupt */
+ 	dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
+@@ -435,6 +436,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
+ 			/* Restart the Phy Clock */
+ 			pcgcctl &= ~PCGCTL_STOPPCLK;
+ 			dwc2_writel(hsotg, pcgcctl, PCGCTL);
++
++			/*
++			 * It is a quirk in Rockchip RK3288, causing by
++			 * a hardware bug. This will propagate out and
++			 * eventually we'll re-enumerate the device.
++			 * Not great but the best we can do.
++			*/
++			if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
++				schedule_work(&hsotg->phy_rst_work);
++
+ 			mod_timer(&hsotg->wkp_timer,
+ 				  jiffies + msecs_to_jiffies(71));
+ 		} else {
+diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
+index 57764289..748763bd 100644
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -208,6 +208,14 @@ int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
+ 	return ret;
+ }
+ 
++/* Only used to reset usb phy at interrupter runtime */
++static void dwc2_reset_phy_work(struct work_struct *data)
++{
++	struct dwc2_hsotg *hsotg = container_of(data, struct dwc2_hsotg,
++			phy_rst_work);
++	phy_reset(hsotg->phy);
++}
++
+ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
+ {
+ 	int i, ret;
+@@ -252,6 +260,7 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
+ 			return ret;
+ 		}
+ 	}
++	INIT_WORK(&hsotg->phy_rst_work, dwc2_reset_phy_work);
+ 
+ 	if (!hsotg->phy) {
+ 		hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);

buildroot-external/board/asus/tinker/patches/linux/board-tinkerboard-support-older-eMMC-installs.patch

@@ -0,0 +1,665 @@
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 2d0b2f4c4..d5c9022e7 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -859,6 +859,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3288-firefly-beta.dtb \
+ 	rk3288-firefly.dtb \
+ 	rk3288-firefly-reload.dtb \
++	rk3288-miniarm.dtb \
+ 	rk3288-miqi.dtb \
+ 	rk3288-phycore-rdk.dtb \
+ 	rk3288-popmetal.dtb \
+diff --git a/arch/arm/boot/dts/rk3288-miniarm.dts b/arch/arm/boot/dts/rk3288-miniarm.dts
+new file mode 100644
+index 000000000..d0961c35d
+--- /dev/null
++++ b/arch/arm/boot/dts/rk3288-miniarm.dts
+@@ -0,0 +1,647 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include "rk3288.dtsi"
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/clock/rockchip,rk808.h>
++
++/ {
++	model = "Rockchip RK3288 Tinker Board";
++	compatible = "asus,rk3288-tinker", "rockchip,rk3288";
++
++	chosen {
++		stdout-path = "serial2:115200n8";
++	};
++
++	memory {
++		reg = <0x0 0x0 0x0 0x80000000>;
++		device_type = "memory";
++	};
++
++	ext_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <125000000>;
++		clock-output-names = "ext_gmac";
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		autorepeat;
++
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwrbtn>;
++
++		button@0 {
++			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
++			linux,code = <KEY_POWER>;
++			label = "GPIO Key Power";
++			linux,input-type = <1>;
++			wakeup-source;
++			debounce-interval = <100>;
++		};
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++
++		act-led {
++			gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger="mmc0";
++		};
++
++		heartbeat-led {
++			gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger="heartbeat";
++		};
++
++		pwr-led {
++			gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "default-on";
++		};
++	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "rockchip,tinker-codec";
++		simple-audio-card,mclk-fs = <512>;
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s>;
++		};
++	};
++
++	/* This is essential to get SDIO devices working.
++	   The Wifi depends on SDIO ! */
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk808 RK808_CLKOUT1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
++
++		/*
++		 * On the module itself this is one of these (depending
++		 * on the actual card populated):
++		 * - SDIO_RESET_L_WL_REG_ON
++		 * - PDN (power down when low)
++		 */
++		reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>;
++	};
++
++	vcc_sys: vsys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc_sd: sdmmc-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sdmmc_pwr>;
++		regulator-name = "vcc_sd";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		vin-supply = <&vcc_io>;
++	};
++
++	wireless-wlan {
++		compatible = "wlan-platdata";
++		rockchip,grf = <&grf>;
++		wifi_chip_type = "8723bs";
++		sdio_vref = <1800>;
++		WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++/*
++	wireless-bluetooth {
++		compatible = "bluetooth-platdata";
++		uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default","rts_gpio";
++		pinctrl-0 = <&uart0_rts>;
++		pinctrl-1 = <&uart0_gpios>;
++		BT,reset_gpio    = <&gpio4 29 GPIO_ACTIVE_HIGH>;
++		BT,wake_gpio     = <&gpio4 26 GPIO_ACTIVE_HIGH>;
++		BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
++		status = "okay";
++	};
++*/
++
++};
++
++&cpu0 {
++	cpu0-supply = <&vdd_cpu>;
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_MAC>;
++	assigned-clock-parents = <&ext_gmac>;
++	clock_in_out = "input";
++	phy-mode = "rgmii";
++	phy-supply = <&vcc33_lan>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	snps,reset-gpio = <&gpio4 7 0>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 1000000>;
++	tx_delay = <0x30>;
++	rx_delay = <0x10>;
++	status = "ok";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&hdmi {
++	ddc-i2c-bus = <&i2c5>;
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	status = "okay";
++
++	rk808: pmic@1b {
++		compatible = "rockchip,rk808";
++		reg = <0x1b>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk808-clkout2";
++		dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
++				<&gpio0 12 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc6-supply = <&vcc_sys>;
++		vcc7-supply = <&vcc_sys>;
++		vcc8-supply = <&vcc_io>;
++		vcc9-supply = <&vcc_io>;
++		vcc10-supply = <&vcc_io>;
++		vcc11-supply = <&vcc_sys>;
++		vcc12-supply = <&vcc_io>;
++		vddio-supply = <&vcc_io>;
++
++		regulators {
++			vdd_cpu: DCDC_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1500000>;
++				regulator-name = "vdd_arm";
++				regulator-ramp-delay = <6000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1500000>;
++				regulator-name = "vdd_gpu";
++				regulator-ramp-delay = <6000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc_ddr";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_io: DCDC_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc_io";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc18_ldo1: LDO_REG1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18_ldo1";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc33_mipi: LDO_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33_mipi";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_10: LDO_REG3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-name = "vdd_10";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vcc18_codec: LDO_REG4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18_codec";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vccio_sd";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vdd10_lcd: LDO_REG6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-name = "vdd10_lcd";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vcc_18: LDO_REG7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc_18";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc18_lcd: LDO_REG8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18_lcd";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc33_sd: SWITCH_REG1 {
++				regulator-boot-on;
++				regulator-name = "vcc33_sd";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc33_lan: SWITCH_REG2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vcc33_lan";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++};
++
++&i2c2 {
++	status = "okay";
++
++	afc0:af-controller@0 {
++		status = "okay";
++		compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
++		reg = <0x0c>;
++	};
++
++	eeprom:m24c08@50 {
++		compatible = "at,24c08";
++		reg = <0x50>;
++	};
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++};
++
++&i2c5 {
++	status = "okay";
++};
++
++&i2s {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++&io_domains {
++	status = "okay";
++	rockchip,grf = <&grf>;
++	wifi-supply = <&vcc_18>;
++	sdcard-supply = <&vccio_sd>;
++};
++
++&sdio0 {
++	status = "okay";
++	clock-frequency = <50000000>;
++	clock-freq-min-max = <200000 50000000>;
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	disable-wp;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	supports-sdio;
++
++};
++
++&pinctrl {
++	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
++		drive-strength = <8>;
++	};
++
++	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
++		bias-pull-up;
++		drive-strength = <8>;
++	};
++
++	backlight {
++		bl_en: bl-en {
++			rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	buttons {
++		pwrbtn: pwrbtn {
++			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	eth_phy {
++		eth_phy_pwr: eth-phy-pwr {
++			rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic-int {
++			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
++					&pcfg_pull_up>;
++		};
++
++		dvs_1: dvs-1 {
++			rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
++					&pcfg_pull_down>;
++		};
++
++		dvs_2: dvs-2 {
++			rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
++					&pcfg_pull_down>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifienable-h {
++			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		chip_enable_h: chip-enable-h {
++			rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdmmc {
++		sdmmc_bus4: sdmmc-bus4 {
++			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
++					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
++					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
++					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
++		};
++
++		sdmmc_clk: sdmmc-clk {
++			rockchip,pins = <6 20 RK_FUNC_1 \
++					&pcfg_pull_none_drv_8ma>;
++		};
++
++		sdmmc_cmd: sdmmc-cmd {
++			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
++		};
++
++		sdmmc_pwr: sdmmc-pwr {
++			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		host_vbus_drv: host-vbus-drv {
++			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pwr_3g: pwr-3g {
++			rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	wireless-bluetooth {
++		uart0_gpios: uart0-gpios {
++			rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcc18_ldo1>;
++	status ="okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	card-detect-delay = <200>;
++	disable-wp;			/* wp not hooked up */
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	sd-uhs-sdr104;
++	status = "okay";
++	supports-sd;
++	vmmc-supply = <&vcc33_sd>;
++	vqmmc-supply = <&vccio_sd>;
++};
++
++&emmc {
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	disable-wp;
++	non-removable;
++	num-slots = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
++	max-frequency = <150000000>;
++	mmc-hs200-1_8v;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
++	status = "okay";
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>,  <&uart0_rts>;
++};
++
++&uart1 {
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&uart3 {
++	status = "okay";
++};
++
++&uart4 {
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host1 {
++	status = "okay";
++};
++
++&usb_otg {
++	status= "okay";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
++
++&vpu_mmu {
++	status = "okay";
++};
++
++&vpu_service {
++	status = "okay";
++};
++
++&hevc_mmu {
++	status = "okay";
++};
++
++&hevc_service {
++	status = "okay";
++};
++
++&wdt {
++	status = "okay";
++};

buildroot-external/board/asus/tinker/patches/linux/brcmfmac-add-ap6330-firmware.patch

@@ -0,0 +1,23 @@
+diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+index a907d7b06..ec71996c7 100644
+--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
++++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+@@ -619,13 +619,17 @@ BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
+ BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
+ BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
+ 
++/* AMPAK */
++BRCMF_FW_DEF(AP6330, "brcmfmac-ap6330-sdio");
++
+ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
+ 	BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
+-	BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
++	BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFEF, 4330),
++	BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0x10, AP6330),
+ 	BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
+ 	BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),

buildroot-external/board/asus/tinker/patches/linux/general-adjust-tinker-dts-hdmi-sound.patch

@@ -1,17 +1,13 @@
 diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
-index 925b277..33b198e 100644
+index 958c0f3bf..59b8d8eac 100644
 --- a/arch/arm/boot/dts/rk3288-tinker.dts
 +++ b/arch/arm/boot/dts/rk3288-tinker.dts
-@@ -100,6 +100,12 @@
- 		};
- 	};
- 
-+	rk3288-gpiomem {
-+		compatible = "rockchip,rk3288-gpiomem";
-+		reg = <0x0 0xff750000 0x0 0x1000>;
-+		status = "okay";
-+	};
-+
+@@ -70,7 +70,7 @@
  	sound {
  		compatible = "simple-audio-card";
  		simple-audio-card,format = "i2s";
+-		simple-audio-card,name = "rockchip,tinker-codec";
++		simple-audio-card,name = "DW-I2S-HDMI";
+ 		simple-audio-card,mclk-fs = <512>;
+ 
+ 		simple-audio-card,codec {

buildroot-external/board/asus/tinker/patches/linux/general-increasing_DMA_block_memory_allocation_to_2048.patch

@@ -0,0 +1,27 @@
+diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
+index 3216e09..21bce28
+--- a/arch/arm64/mm/dma-mapping.c
++++ b/arch/arm64/mm/dma-mapping.c
+@@ -44,7 +44,7 @@ static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot,
+
+ static struct gen_pool *atomic_pool;
+
+-#define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_256K
++#define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_2M
+ static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
+
+ static int __init early_coherent_pool(char *p)
+
+diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
+index ada8eb2..8df220f
+--- a/arch/arm/mm/dma-mapping.c
++++ b/arch/arm/mm/dma-mapping.c
+@@ -381,7 +381,7 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
+ 			VM_ARM_DMA_CONSISTENT | VM_USERMAP);
+ }
+
+-#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_256K
++#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_2M
+ static struct gen_pool *atomic_pool __ro_after_init;
+
+ static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;

buildroot-external/board/asus/tinker/patches/linux/increasing_DMA_block_memory_allocation_to_2048.patch

@@ -1,13 +0,0 @@
-diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
-index bd83c53..af7cfe3
---- a/arch/arm/mm/dma-mapping.c
-+++ b/arch/arm/mm/dma-mapping.c
-@@ -374,7 +374,7 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
- 			VM_ARM_DMA_CONSISTENT | VM_USERMAP);
- }
-
--#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_256K
-+#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_2M
- static struct gen_pool *atomic_pool;
-
- static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;

buildroot-external/board/asus/tinker/patches/linux/memolry-leak-fix-r8723bs.patch

@@ -1,26 +0,0 @@
-diff --git a/drivers/staging/rtl8723bs/hal/sdio_ops.c
-b/drivers/staging/rtl8723bs/hal/sdio_ops.c
-index 6285b72faa9a..ad65cd74c3c8 100644
---- a/drivers/staging/rtl8723bs/hal/sdio_ops.c
-+++ b/drivers/staging/rtl8723bs/hal/sdio_ops.c
-@@ -1008,6 +1008,7 @@ static struct recv_buf *sd_recv_rxfifo(struct
- adapter *padapter, u32 size)
- 		}
-
- 		if (precvbuf->pskb == NULL) {
-+			rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
- 			DBG_871X("%s: alloc_skb fail! read =%d\n", __func__, readsize);
- 			return NULL;
- 		}
-@@ -1017,6 +1018,7 @@ static struct recv_buf *sd_recv_rxfifo(struct
- adapter *padapter, u32 size)
- 	preadbuf = precvbuf->pskb->data;
- 	ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID,
- readsize, preadbuf);
- 	if (ret == _FAIL) {
-+		rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
- 		RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: read port FAIL!\n",
- __func__));
- 		return NULL;
- 	}
-

buildroot-external/board/asus/tinker/patches/linux/staging-rtl8723bs-hide-nolinked-power-save-info-when-not-debugging.patch

@@ -1,22 +0,0 @@
-diff --git a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
-index 820a061506cc..80cf5a8b1557 100644
---- a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
-+++ b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c
-@@ -34,7 +34,7 @@ void _ips_enter(struct adapter *padapter)
- 
- 	if (rf_off == pwrpriv->change_rfpwrstate) {
- 		pwrpriv->bpower_saving = true;
--		DBG_871X_LEVEL(_drv_always_, "nolinked power save enter\n");
-+		DBG_871X("nolinked power save enter\n");
- 
- 		if (pwrpriv->ips_mode == IPS_LEVEL_2)
- 			pwrpriv->bkeepfwalive = true;
-@@ -73,7 +73,7 @@ int _ips_leave(struct adapter *padapter)
- 		if (result == _SUCCESS) {
- 			pwrpriv->rf_pwrstate = rf_on;
- 		}
--		DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n");
-+		DBG_871X("nolinked power save leave\n");
- 
- 		DBG_871X("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c));
- 		pwrpriv->bips_processing = false;

buildroot-external/board/asus/tinker/patches/linux/wifi-0002-realtek-wifi-881xAU-adding-kernel-4.14.patch

@@ -1,26 +0,0 @@
-diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
-index 918f449..561b71c 100644
---- a/drivers/net/wireless/Kconfig
-+++ b/drivers/net/wireless/Kconfig
-@@ -39,6 +39,8 @@ source "drivers/net/wireless/cisco/Kconfig"
- source "drivers/net/wireless/intel/Kconfig"
- source "drivers/net/wireless/intersil/Kconfig"
- source "drivers/net/wireless/marvell/Kconfig"
-+source "drivers/net/wireless/rtl8812au/Kconfig"
-+source "drivers/net/wireless/rtl8814au/Kconfig"
- source "drivers/net/wireless/mediatek/Kconfig"
- source "drivers/net/wireless/ralink/Kconfig"
- source "drivers/net/wireless/realtek/Kconfig"
-diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
-index 59df552..614ddf4 100644
---- a/drivers/net/wireless/Makefile
-+++ b/drivers/net/wireless/Makefile
-@@ -12,6 +12,8 @@ obj-$(CONFIG_WLAN_VENDOR_CISCO) += cisco/
- obj-$(CONFIG_WLAN_VENDOR_INTEL) += intel/
- obj-$(CONFIG_WLAN_VENDOR_INTERSIL) += intersil/
- obj-$(CONFIG_WLAN_VENDOR_MARVELL) += marvell/
-+obj-$(CONFIG_RTL8812AU) += rtl8812au/
-+obj-$(CONFIG_RTL8814AU) += rtl8814au/
- obj-$(CONFIG_WLAN_VENDOR_MEDIATEK) += mediatek/
- obj-$(CONFIG_WLAN_VENDOR_RALINK) += ralink/
- obj-$(CONFIG_WLAN_VENDOR_REALTEK) += realtek/

buildroot-external/board/asus/tinker/patches/linux/wifi-0003-realtek-wifi-881xAU-enable-8814au.patch

@@ -1,46 +0,0 @@
-diff --git a/drivers/net/wireless/rtl8812au/Kconfig b/drivers/net/wireless/rtl8812au/Kconfig
-index 16d3567..f87653d 100644
---- a/drivers/net/wireless/rtl8812au/Kconfig
-+++ b/drivers/net/wireless/rtl8812au/Kconfig
-@@ -4,8 +4,3 @@ config RTL8812AU
- 	---help---
- 	  Help message of RTL8812AU
- 
--config RTL8814AU
--	tristate "Realtek 8814A USB WiFi"
--	depends on USB
--	---help---
--	  Help message of RTL8814AU
-diff --git a/drivers/net/wireless/rtl8814au/Kconfig b/drivers/net/wireless/rtl8814au/Kconfig
-index 16d3567..730c4e0 100644
---- a/drivers/net/wireless/rtl8814au/Kconfig
-+++ b/drivers/net/wireless/rtl8814au/Kconfig
-@@ -1,9 +1,3 @@
--config RTL8812AU
--	tristate "Realtek 8812A USB WiFi"
--	depends on USB
--	---help---
--	  Help message of RTL8812AU
--
- config RTL8814AU
- 	tristate "Realtek 8814A USB WiFi"
- 	depends on USB
-diff --git a/drivers/net/wireless/rtl8814au/Makefile b/drivers/net/wireless/rtl8814au/Makefile
-index ef959e7..f71f524 100644
---- a/drivers/net/wireless/rtl8814au/Makefile
-+++ b/drivers/net/wireless/rtl8814au/Makefile
-@@ -32,11 +32,11 @@ CONFIG_AUTOCFG_CP = n
- ########################## WIFI IC ############################
- CONFIG_MULTIDRV = n
- CONFIG_RTL8188E = n
--CONFIG_RTL8812A = y
--CONFIG_RTL8821A = y
-+CONFIG_RTL8812A = n
-+CONFIG_RTL8821A = n
- CONFIG_RTL8192E = n
- CONFIG_RTL8723B = n
--CONFIG_RTL8814A = n
-+CONFIG_RTL8814A = y
- CONFIG_RTL8723C = n
- CONFIG_RTL8188F = n
- CONFIG_RTL8822B = n

buildroot-external/board/asus/tinker/patches/linux/wifi-2002-02-rtl8188eu.patch

@@ -301875,7 +301875,7 @@ new file mode 100644
 index 0000000000000..324b45bd223fd
 --- /dev/null
 +++ b/drivers/net/wireless/rtl8188eu/include/wifi.h
-@@ -0,0 +1,1103 @@
+@@ -0,0 +1,1105 @@
 +/******************************************************************************
 + *
 + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
@@ -302608,7 +302608,9 @@ index 0000000000000..324b45bd223fd
 + * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
 + */
 +#define IEEE80211_MIN_AMPDU_BUF 0x8
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,19,0))
 +#define IEEE80211_MAX_AMPDU_BUF 0x40
++#endif
 +
 +/* Spatial Multiplexing Power Save Modes */
 +#define WLAN_HT_CAP_SM_PS_STATIC	0
@@ -311898,7 +311900,7 @@ new file mode 100644
 index 0000000000000..fadf117a54b6a
 --- /dev/null
 +++ b/drivers/net/wireless/rtl8188eu/os_dep/os_intfs.c
-@@ -0,0 +1,1273 @@
+@@ -0,0 +1,1276 @@
 +/******************************************************************************
 + *
 + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
@@ -312553,7 +312555,10 @@ index 0000000000000..fadf117a54b6a
 +}
 +
 +static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0))
++			    ,struct net_device *sb_dev
++                            ,select_queue_fallback_t fallback
++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0))
 +			    ,void *unused
 +                            ,select_queue_fallback_t fallback
 +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(3, 13, 0))

buildroot-external/board/asus/tinker/patches/linux/xt-q8l-v10-add-device-tree.patch

@@ -0,0 +1,972 @@
+--- /dev/null
++++ b/arch/arm/boot/dts/rk3288-xt-q8l-v10.dts	2018-12-06 21:46:51.493688015 +0000
+@@ -0,0 +1,969 @@
++/*
++ * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
++ * 					   2018 Paolo Sabatino <paolo.sabatino@gm**l.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "rk3288.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++	model = "XT-Q8L-V10-RK3288";
++	compatible = "generic,xt-q8l-v10-rk3288", "rockchip,rk3288";
++
++	memory {
++		reg = <0x0 0x0 0x0 0x80000000>;
++		device_type = "memory";
++	};
++	
++	cpu0_opp_table: opp_table {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp@600000000 {
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt = <900000>;
++		};
++		opp@816000000 {
++			opp-hz = /bits/ 64 <816000000>;
++			opp-microvolt = <1000000>;
++		};
++		opp@1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt = <1050000>;
++		};
++		opp@1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1100000>;
++		};
++		opp@1416000000 {
++			opp-hz = /bits/ 64 <1416000000>;
++			opp-microvolt = <1200000>;
++		};
++		opp@1512000000 {
++			opp-hz = /bits/ 64 <1512000000>;
++			opp-microvolt = <1250000>;
++		};
++		opp@1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1300000>;
++		};
++		/*
++		opp@1704000000 {
++			opp-hz = /bits/ 64 <1704000000>;
++			opp-microvolt = <1350000>;
++		};
++		opp@1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1400000>;
++		};
++		*/
++	};
++	
++	/*
++	 * Peripheral from original q8 device tree, currently no references
++	 * for drivers in linux kernel.
++	rockchip-hsadc@ff080000 {
++		compatible = "rockchip-hsadc";
++		reg = <0xff080000 0x4000>;
++		interrupts = <0x0 0x1f 0x4>;
++		#address-cells = <0x1>;
++		#size-cells = <0x0>;
++		pinctrl-names = "default";
++		pinctrl-0 = <0x9a>;
++		clocks = <0x79 0x7 0x8 0x39>;
++		clock-names = "hclk_hsadc", "clk_hsadc_out", "clk_hsadc_ext";
++		dmas = <0x9b 0x0>;
++		dma-names = "data";
++		status = "disabled";
++	};
++	*/
++
++	ext_gmac: external-gmac-clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <125000000>;
++		clock-output-names = "ext_gmac";
++	};
++	
++	/*
++	 * Handle the IR receiver using the gpio-ir-receiver kernel module.
++	 * This works flawlessy, the original xt-q8l-v10 remote uses a NEC
++	 * protocol and the keymap rc-xt-q8l-v10 has to be compiled in the
++	 * kernel for the remote to work as an input device
++	 */
++	ir: ir-receiver {
++		compatible = "gpio-ir-receiver";
++		gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&ir_int>;
++		linux,rc-map-name = "rc-xt-q8l-v10";
++		wakeup-source;
++	};	
++
++	keys: gpio-keys {
++		compatible = "gpio-keys";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwr_key>;
++
++		button@0 {
++			gpio-key,wakeup = <1>;
++			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
++			label = "GPIO Power";
++			linux,code = <KEY_POWER>;
++			wakeup-source;
++			debounce-interval = <100>;
++		};
++		
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		power {
++			/*
++				Power led is active high, but we set it here active low
++				so while there is mass storage access it turns red and
++				when it is idle is blue
++			*/
++			gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; 
++			label = "power";
++			linux,default-trigger = "mmc0";
++			pinctrl-names = "default";
++			pinctrl-0 = <&power_led>;
++		};
++
++	};
++
++	vcc_sys: vsys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc_sd: sdmmc-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sdmmc_pwr>;
++		regulator-name = "vcc_sd";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		vin-supply = <&vcc_io>;
++	};
++
++	vcc_flash: flash-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_flash";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_io>;
++	};
++
++	vcc_host_5v: usb-host-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&host_vbus_drv>;
++		regulator-name = "vcc_host_5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++        regulator-always-on;
++        enable-active-high;
++//        startup-delay-us = <1000>;
++		vin-supply = <&vcc_sys>;
++	};
++
++
++	vcc_otg_5v: usb-otg-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&otg_vbus_drv>;
++		regulator-name = "vcc_otg_5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++//        startup-delay-us = <1000>;
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	/*
++	 * Required power sequence to properly enable the wireless/bluetooth
++	 * module connected to sdio0
++	 */
++	sdio0_pwrseq: sdio0_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h>, <&bt_enable_h>;
++		reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 29 GPIO_ACTIVE_LOW>;
++		post-power-on-delay-ms = <100>;
++	};
++	
++	/*
++	 * Sound taken from tinkerboard device tree, adapted to q8.
++	 */
++	soundcard-hdmi {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "DW-I2S-HDMI";
++		simple-audio-card,mclk-fs = <512>;
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s>;
++		};
++	};
++	
++	soundcard-spdif {
++        compatible = "simple-audio-card";
++        simple-audio-card,name = "SPDIF";
++        simple-audio-card,dai-link@1 {
++			
++            cpu { 
++				sound-dai = <&spdif>; 
++			};
++			
++            codec { 
++				sound-dai = <&spdif_out>; 
++			};
++			
++        };
++    };
++
++    spdif_out: spdif-out {
++        compatible = "linux,spdif-dit";
++        #sound-dai-cells = <0>;
++    };
++
++};
++
++
++&io_domains {
++	status = "okay";
++
++	audio-supply = <&vcca_33>;
++	bb-supply = <&vcc_io>;
++	dvp-supply = <&vcc_18>;
++	flash0-supply = <&vcc_flash>;
++	flash1-supply = <&vcc_lan>;
++	gpio30-supply = <&vcc_io>;
++	gpio1830-supply = <&vcc_io>;
++	lcdc-supply = <&vcc_io>;
++	sdcard-supply = <&vccio_sd>;
++	wifi-supply = <&vcc_18>;
++};
++
++&cpu0 {
++	cpu0-supply = <&vdd_cpu>;
++	operating-points-v2 = <&cpu0_opp_table>;
++	/delete-node/operating-points;
++};
++
++&cpu1 {
++	operating-points-v2 = <&cpu0_opp_table>;
++	/delete-node/operating-points;
++};
++
++&cpu2 {
++	operating-points-v2 = <&cpu0_opp_table>;
++	/delete-node/operating-points;
++};
++
++&cpu3 {
++	operating-points-v2 = <&cpu0_opp_table>;
++	/delete-node/operating-points;
++};
++
++&gmac {
++	assigned-clocks = <&cru SCLK_MAC>;
++	assigned-clock-parents = <&ext_gmac>;
++	clock_in_out = "input";
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
++	phy-supply = <&vcc_lan>;
++	phy-mode = "rgmii";
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 10000 1000000>;
++	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
++	tx_delay = <0x30>;
++	rx_delay = <0x10>;
++	status = "ok";
++};
++
++&hdmi {
++	ddc-i2c-bus = <&i2c5>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	status = "okay";
++
++	vdd_cpu: syr827@40 {
++		compatible = "silergy,syr827";
++		fcs,suspend-voltage-selector = <1>;
++		reg = <0x40>;
++		regulator-name = "vdd_cpu";
++		regulator-min-microvolt = <850000>;
++		regulator-max-microvolt = <1350000>;
++		regulator-ramp-delay = <8000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vdd_gpu: syr828@41 {
++		compatible = "silergy,syr828";
++		fcs,suspend-voltage-selector = <1>;
++		reg = <0x41>;
++		regulator-name = "vdd_gpu";
++		regulator-min-microvolt = <850000>;
++		regulator-max-microvolt = <1350000>;
++		regulator-ramp-delay = <8000>;
++		regulator-always-on;
++		vin-supply = <&vcc_sys>;
++	};
++
++	hym8563: hym8563@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		clock-output-names = "xin32k";
++		interrupt-parent = <&gpio0>;
++		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&rtc_int>;
++	};
++
++	act8846: act8846@5a {
++		compatible = "active-semi,act8846";
++		reg = <0x5a>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_vsel>;
++		system-power-controller;
++
++		vp1-supply = <&vcc_sys>;
++		vp2-supply = <&vcc_sys>;
++		vp3-supply = <&vcc_sys>;
++		vp4-supply = <&vcc_sys>;
++		inl1-supply = <&vcc_sys>;
++		inl2-supply = <&vcc_sys>;
++		inl3-supply = <&vcc_20>;
++		wakeup-source;
++
++		regulators {
++			
++			/*
++			 * Regulator controlling DDR memory - always on
++			 */
++			vcc_ddr: REG1 {
++				regulator-name = "vcc_ddr";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * Regulator controlling various IO functions of the rk3288.
++			 * Always on
++			 */
++			vcc_io: REG2 {
++				regulator-name = "vcc_io";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * Regulator controlling various board logic.
++			 * Always on.
++			 * rk3288 electrical datasheet says it should have variable
++			 * voltage depending upon dvfs
++			 */
++			vdd_log: REG3 {
++				regulator-name = "vdd_log";
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * No reference for this on electrical datasheet. Maybe this
++			 * is vcc_18? Maybe this is vcc18_flash on electrical datasheet.
++			 * So far we disable it.
++			 */
++			vcc_20: REG4 {
++				regulator-name = "vcc_20";
++				regulator-min-microvolt = <2000000>;
++				regulator-max-microvolt = <2000000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * This regulator controls SDIO. Electrical datasheet says
++			 * this regulator can be operated between 1.8 and 3.3 volts
++			 */
++			vccio_sd: REG5 {
++				regulator-name = "vccio_sd";
++				regulator-min-microvolt = <1800000>; 
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * Controlling HDMI and LCD controller on rk3288. 1.0 volts
++			 * by reference
++			 */
++			vdd10_lcd: REG6 {
++				regulator-name = "vdd10_lcd";
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * From the rk3288 electrical datasheet, this regulator powers
++			 * the rk1000 chip, which is absent in our device, but it
++			 * is also supplying bluetooth, so we enable it.
++			 */
++			vcca_18: REG7 {
++				regulator-name = "vcca_18";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * This regulator controls, among other things, the SPDIF
++			 * interface, so we enable it
++			 */
++			vcca_33: REG8 {
++				regulator-name = "vcca_33";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on; // Turn this on to get SPDIF!
++			};
++
++			/*
++			 * LAN regulator
++			 */
++			vcc_lan: REG9 {
++				regulator-name = "vcc_lan";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			/*
++			 * Regulator controlling PMU, USB PHY and rk3288 PLLs.
++			 * 1.0 volts by reference
++			 */
++			vdd_10: REG10 {
++				regulator-name = "vdd_10";
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * Regulator controlling Wifi over SDIO, SARADC and USB PHY.
++			 * Better turn this on
++			 */
++			vccio_wl: vcc_18: REG11 {
++				regulator-name = "vcc_18";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++			};
++
++			/*
++			 * Not clear: apparently this controls HDMI and LCD controller
++			 * on rk3368 devices.
++			 * 1.8 volts by reference
++			 */
++			vcc18_lcd: REG12 {
++				regulator-name = "vcc18_lcd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++};
++
++&i2c2 {
++	status = "okay";
++};
++
++&i2c4 {
++	
++	/*
++	 * Here should go the RK1000 audio codec parts, but seems that
++	 * there is no driver in linux kernel at the moment, so we can't
++	 * describe it.
++	 * Also, most important, there is no RK1000 on our board :)
++	 * Datasheet is available here:
++	 * http://dl.radxa.com/rock/docs/hw/ds/RK1000-S%20DATASHEET%20V14.pdf
++	 */
++	status = "okay";
++	
++};
++
++&i2c5 {
++	status = "okay";
++};
++
++&pinctrl {
++
++	/*
++		These two lines here, these must be commented out! Otherwise for some reason the kernel
++		does not see the boot device anymore and will stay stuck in initramfs!
++		On the contrary, these are required by u-boot to keep the power holding so the device does not
++		automatically turns off after a small timeout
++	*/
++	/*pinctrl-names = "default";*/
++	/*pinctrl-0 = <&pwr_hold>;*/
++
++	pcfg_output_high: pcfg-output-high {
++		output-high;
++	};
++
++	pcfg_output_low: pcfg-output-low {
++		output-low;
++	};
++
++	pcfg_wl: pcfg-wl {
++		bias-pull-up;
++		drive-strength = <8>;
++	};
++	
++	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
++		bias-pull-up;
++		drive-strength = <8>;
++	};
++	
++	pcfg_pull_none_8ma: pcfg-pull-none-8ma {
++		bias-disable;
++		drive-strength = <8>;
++	};
++
++	pcfg_wl_clk: pcfg-wl-clk {
++		bias-disable;
++		drive-strength = <12>;
++	};
++
++	pcfg_wl_int: pcfg-wl-int {
++		bias-pull-up;
++	};
++	
++	act8846 {
++		
++		/*
++		 * Original q8 device tree says:
++		 *  - gpio0 11 HIGH -> power hold
++		 *  - gpio7 1 LOW -> possibly pmic-vsel, we don't care 
++		 */ 
++		pmic_vsel: pmic-vsel {
++			rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
++		};
++		
++		pwr_hold: pwr-hold {
++			rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	gmac {
++		phy_int: phy-int {
++			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		phy_pmeb: phy-pmeb {
++			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		phy_rst: phy-rst {
++			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
++		};
++	};
++
++	hym8563 {
++		rtc_int: rtc-int {
++			rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	keys {
++		pwr_key: pwr-key {
++			rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	leds {
++		power_led: power-led {
++			rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	ir {
++		ir_int: ir-int {
++			rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	sdmmc {
++		
++		/*
++		 * Copied from firefly board definition to give more drive to
++		 * the sdmmc pins. The Q8 seems to be quite able to drive
++		 * ultra high speed uSD cards, so we give a bit more energy
++		 * to the gpio pins
++		 */
++		sdmmc_bus4: sdmmc-bus4 {
++			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
++					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
++					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
++					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
++		};
++
++		sdmmc_clk: sdmmc-clk {
++			rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_8ma>;
++		};
++
++		sdmmc_cmd: sdmmc-cmd {
++			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
++		};
++
++		sdmmc_pwr: sdmmc-pwr {
++			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++	};
++
++	usb_host1 {
++		host_vbus_drv: host-vbus-drv {
++			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++	};
++
++	usb_otg {
++		otg_vbus_drv: otg-vbus-drv {
++			rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio0 {
++		wifi_enable_h: wifienable-h {
++			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_output_high>;
++		};
++
++		bt_enable_h: bt-enable-h {
++			rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_output_high>;
++		};
++
++	};
++	
++	
++	wireless-bluetooth {
++		uart0_gpios: uart0-gpios {
++			rockchip,pins = <4 19 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++};
++
++&saradc {
++	vref-supply = <&vcc_18>;
++	status = "okay";
++};
++
++&emmc {
++	
++	/*
++	 * eMMC seems to be 52Mhz device on q8 devices, so set it here
++	 * vmmc-supply and vqmmc-supply are removed because they hang
++	 * u-boot >= v2018.03
++	 * From the original q8l firmware and eMMC datasheet it also should
++	 * support DDR highspeed mode, but using mmc-ddr-3_3v or mmc-ddr-1_8v
++	 * properties are not working
++	 */
++	clock-frequency = <50000000>;
++	 
++	broken-cd;
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	disable-wp;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
++
++	status = "okay";
++};
++
++&sdmmc {
++	supports-sd;
++
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	card-detect-delay = <200>;
++	disable-wp;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
++	vmmc-supply = <&vcc_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	sd-uhs-sdr104;
++	sd-uhs-ddr50;
++	status = "okay";
++};
++
++&sdio0 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	
++	bus-width = <4>;
++	mmc-pwrseq = <&sdio0_pwrseq>;
++	
++	vmmc-supply = <&vcc_io>;
++    vqmmc-supply = <&vcc_18>; // This must be the same as in io_domains, 
++		// otherwise the mmc1 device won't be detected properly
++		
++//	clock-frequency = <50000000>;
++//	max-frequency = <50000000>;
++
++	pinctrl-names = "default";
++    pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
++	
++	cap-sdio-irq;
++	no-mmc;
++	no-sd;
++	cap-sd-highspeed; // required, otherwise does not work!
++	supports-sdio; 
++	non-removable;
++	
++	keep-power-in-suspend;
++	disable-wp;
++ 
++	
++	status = "okay";
++	
++	brcmf: bcrmf@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++		interrupt-parent = <&gpio4>;
++		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-names = "host-wake";
++		status = "okay";
++	}; 
++	
++	//sd-uhs-sdr104; // required to be disabled, otherwise the device get
++		// detected, but there is no communication
++
++};
++
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <0>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++/*
++ * These dmas described here for uarts are present in original q8 board
++ * dts, so I replicate them here because documentation says that serial
++ * ports can have dmas.
++ * note: 
++ *  - uart0 is the serial port connected to the bluetooth module
++ *  - uart2 is the onboard serial port 
++ * 
++ * As ok kernel 4.19 DMA for serial ports is disabled because it makes
++ * the ports unusable
++ * 
++ */
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
++	//dmas = <&dmac_peri 1 &dmac_peri 2>;
++	//dma-names = "tx", "rx";
++	status = "okay";
++};
++
++&uart1 {
++	//dmas = <&dmac_peri 3 &dmac_peri 4>;
++	//dma-names = "tx", "rx";
++	status = "okay";
++};
++
++&uart2 {
++	//dmas = <&dmac_bus_s 4 &dmac_bus_s 5>;
++	//dma-names = "tx", "rx";
++	status = "okay";
++};
++
++&uart3 {
++	//dmas = <&dmac_peri 7 &dmac_peri 8>;
++	//dma-names = "tx", "rx";
++	status = "okay";
++};
++
++&uart4 {
++	//dmas = <&dmac_peri 9 &dmac_peri 10>;
++	//dma-names = "tx", "rx";
++	status = "disabled";
++};
++
++/*
++ * Here usbphy* should have their proper reset lines described in rk3288.dtsi
++ * Describing resets for usb phy is important because otherwise the USB
++ * port gets stuck in case it goes into autosuspend: plugging any device
++ * when the port is autosuspended will actually kill the port itself and
++ * require a power cycle.
++ * This is required for the usbphy1 phy, nonetheless it is a good idea to
++ * specify the proper resources for all the phys though.
++ * The reference patch which works in conjuction with the reset lines:
++ * https://patchwork.kernel.org/patch/9469811/
++ * 
++ */
++&usbphy {
++	status = "okay";
++};
++ 
++&usbphy0 {
++    vbus-supply = <&vcc_otg_5v>;
++};
++
++&usbphy2 {
++    vbus-supply = <&vcc_host_5v>;
++};
++
++&usb_host0_ehci {
++    dr_mode = "host";
++    reg = <0x0 0xff500000 0x0 0x20000>;
++    status = "disable";
++};
++
++&usb_host1 {
++	status = "okay";
++};
++
++&usb_otg {
++	status = "okay";
++};
++
++/*
++ * Enable VPU services and complete the relative IOMMU configurations
++ */
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++};
++
++&vopl_mmu {
++	status = "okay";
++};
++
++&vpu_mmu {
++	status = "okay";
++};
++
++&vpu_service {
++	status = "okay";
++};
++
++&hevc_mmu {
++	status = "okay";
++};
++
++&hevc_service {
++	status = "okay";
++};
++
++&wdt {
++	status = "okay";
++};
++
++// i2s bus is present on q8 device, enable it
++&i2s {
++	#sound-dai-cells = <0>;
++	status = "okay";
++};
++
++// spdif is present on q8 device, enable it
++&spdif {
++	status = "okay";
++};

buildroot-external/board/asus/tinker/patches/linux/xt-q8l-v10-add-dts-makefile.patch

@@ -0,0 +1,12 @@
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 37a3de760..6bcfceede 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -832,6 +832,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ 	rk3188-radxarock.dtb \
+ 	rk3228-evb.dtb \
+ 	rk3229-evb.dtb \
++	rk3288-xt-q8l-v10.dtb \
+ 	rk3288-evb-act8846.dtb \
+ 	rk3288-evb-rk808.dtb \
+ 	rk3288-fennec.dtb \

buildroot-external/board/asus/tinker/patches/linux/xt-q8l-v10-remote-keymap.patch

@@ -0,0 +1,103 @@
+diff --git a/include/media/rc-map.h b/include/media/rc-map.h
+index bfa3017..c2a21bb 100644
+--- a/include/media/rc-map.h
++++ b/include/media/rc-map.h
+@@ -277,6 +277,7 @@ struct rc_map *rc_map_get(const char *name);
+ #define RC_MAP_WINFAST                   "rc-winfast"
+ #define RC_MAP_WINFAST_USBII_DELUXE      "rc-winfast-usbii-deluxe"
+ #define RC_MAP_SU3000                    "rc-su3000"
++#define RC_MAP_XT_Q8L_V10                "rc-xt-q8l-v10"
+ #define RC_MAP_ZX_IRDEC                  "rc-zx-irdec"
+ 
+ /*
+diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
+index d6b913a..ee00ce5 100644
+--- a/drivers/media/rc/keymaps/Makefile
++++ b/drivers/media/rc/keymaps/Makefile
+@@ -116,4 +116,5 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
+ 			rc-winfast.o \
+ 			rc-winfast-usbii-deluxe.o \
+ 			rc-su3000.o \
++           rc-xt-q8l-v10.o \
+ 			rc-zx-irdec.o
+diff --git a/drivers/media/rc/keymaps/rc-xt-q8l-v10.c b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
+index e69de29..19c7d9e 100644
+--- /dev/null
++++ b/drivers/media/rc/keymaps/rc-xt-q8l-v10.c
+@@ -0,0 +1,76 @@
++// SPDX-License-Identifier: GPL-2.0+
++// rc-xt-q8l-v10.c - Keytable for xt-q8l-v10 tv box remote controller
++//
++// keymap imported from ir-keymaps.c
++//
++// Copyright (c) 2018 Paolo Sabatino
++
++#include <media/rc-map.h>
++#include <linux/module.h>
++
++/*
++
++*/
++
++static struct rc_map_table xt_q8l_v10[] = {
++	
++	{ 0xcc1d11, KEY_ENTER },
++	{ 0xcc1d00, KEY_POWER },
++	{ 0xcc1d15, KEY_PLAYPAUSE },
++	{ 0xcc1d16, KEY_STOP },
++	{ 0xcc1d06, KEY_PREVIOUSSONG },
++	{ 0xcc1d0a, KEY_NEXTSONG },
++	{ 0xcc1d41, KEY_1 },
++	{ 0xcc1d45, KEY_2 },
++	{ 0xcc1d4d, KEY_3 },
++	{ 0xcc1d42, KEY_4 },
++	{ 0xcc1d46, KEY_5 },
++	{ 0xcc1d4e, KEY_6 },
++	{ 0xcc1d43, KEY_7 },
++	{ 0xcc1d47, KEY_8 },
++	{ 0xcc1d4f, KEY_9 },
++	{ 0xcc1d49, KEY_0 },
++	{ 0xcc1d4a, KEY_BACKSPACE },
++	{ 0xcc1d48, KEY_F6 },
++	{ 0xcc1d03, KEY_HOME },
++	{ 0xcc1d0f, KEY_BACK },
++	{ 0xcc1d40, KEY_MENU },
++	{ 0xcc1d4c, KEY_TEXT },
++	{ 0xcc1d10, KEY_LEFT },
++	{ 0xcc1d12, KEY_RIGHT },
++	{ 0xcc1d44, KEY_DOWN },
++	{ 0xcc1d07, KEY_UP },
++	{ 0xcc1d02, KEY_VOLUMEDOWN },
++	{ 0xcc1d0c, KEY_MUTE },
++	{ 0xcc1d0e, KEY_VOLUMEUP },
++	{ 0xcc1d01, KEY_F1 },
++	{ 0xcc1d05, KEY_F2 },
++	{ 0xcc1d09, KEY_F3 },
++	{ 0xcc1d0d, KEY_F4 },
++	
++};
++
++static struct rc_map_list xt_q8l_v10_map = {
++	.map = {
++		.scan     = xt_q8l_v10,
++		.size     = ARRAY_SIZE(xt_q8l_v10),
++		.rc_proto = RC_PROTO_NEC,	/* Legacy IR type */
++		.name     = RC_MAP_XT_Q8L_V10,
++	}
++};
++
++static int __init init_rc_map_xt_q8l_v10(void)
++{
++	return rc_map_register(&xt_q8l_v10_map);
++}
++
++static void __exit exit_rc_map_xt_q8l_v10(void)
++{
++	rc_map_unregister(&xt_q8l_v10_map);
++}
++
++module_init(init_rc_map_xt_q8l_v10)
++module_exit(exit_rc_map_xt_q8l_v10)
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Paolo Sabatino");

buildroot-external/board/asus/tinker/patches/uboot/101-u-boot-0002-rockchip-tinker-enable-rockchip-video-driver.patch.disabled

@@ -0,0 +1,25 @@
+From cd0236ef771fd72e2975ca294ba2f1872d7dbc0b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 22 Oct 2017 12:48:24 +0200
+Subject: [PATCH 2/2] rockchip: tinker: enable rockchip video driver
+
+---
+ configs/tinker-rk3288_defconfig | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
+index 1315be3ee8..3a81328b48 100644
+--- a/configs/tinker-rk3288_defconfig
++++ b/configs/tinker-rk3288_defconfig
+@@ -78,6 +78,11 @@ CONFIG_USB_GADGET_DWC2_OTG=y
+ CONFIG_USB_HOST_ETHER=y
+ CONFIG_USB_ETHER_ASIX=y
+ CONFIG_USB_ETHER_SMSC95XX=y
++CONFIG_DM_VIDEO=y
++CONFIG_DISPLAY=y
++CONFIG_VIDEO_ROCKCHIP=y
++CONFIG_DISPLAY_ROCKCHIP_HDMI=y
++CONFIG_CONSOLE_SCROLL_LINES=10
+ CONFIG_USE_TINY_PRINTF=y
+ CONFIG_CMD_DHRYSTONE=y
+ CONFIG_ERRNO_STR=y

buildroot-external/board/hardkernel/odroid-xu4/kernel.config

@@ -680,13 +680,8 @@ CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_GOV_ATTR_SET=y
 CONFIG_CPU_FREQ_GOV_COMMON=y
 CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=m
 CONFIG_CPU_FREQ_GOV_USERSPACE=m
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
@@ -1588,8 +1583,8 @@ CONFIG_STANDALONE=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_FW_LOADER=y
 CONFIG_FIRMWARE_IN_KERNEL=y
-#CONFIG_EXTRA_FIRMWARE="edid/480x320.bin edid/1920x1080_24hz.bin edid/1920x1080_23_976hz.bin edid/848x480.bin edid/1152x864_75hz.bin edid/1280x768.bin edid/1920x800.bin edid/1400x1050.bin edid/1792x1344.bin edid/1024x768.bin edid/1280x800.bin edid/1920x1080.bin edid/720x480.bin edid/800x600.bin edid/800x480.bin edid/480x800.bin edid/1280x1024.bin edid/1280x720.bin edid/1440x900.bin edid/1680x1050.bin edid/1360x768.bin edid/1366x768.bin edid/1600x1200.bin edid/1600x900.bin edid/1920x1200_30hz.bin edid/1920x1200_60hz.bin edid/1920x1080_50hz.bin edid/640x480.bin edid/720x576.bin edid/1024x600.bin"
-#CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+CONFIG_EXTRA_FIRMWARE="s5p-mfc-v8.fw"
+CONFIG_EXTRA_FIRMWARE_DIR="/build/buildroot/output/target/usr/lib/firmware/"
 # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
 CONFIG_WANT_DEV_COREDUMP=y
 CONFIG_ALLOW_DEV_COREDUMP=y

buildroot-external/board/hardkernel/odroid-xu4/meta

@@ -4,4 +4,4 @@ CHASSIS=embedded
 BOOTLOADER=uboot
 KERNEL_FILE=zImage
 BOOT_SYS=mbr
-BOOT_ENV_SIZE=0x2000
+BOOT_ENV_SIZE=0x4000

buildroot-external/board/hardkernel/odroid-xu4/uboot-boot.ush

@@ -3,15 +3,20 @@
 
 part start mmc ${devnum} 9 mmc_env
 mmc dev ${devnum}
+
+# Note that import is performed twice for backwards compatability.
 setenv loadbootstate " \
     echo 'loading env...'; \
-    mmc read ${ramdisk_addr_r} ${mmc_env} 0x10; \
-    env import -c ${ramdisk_addr_r} 0x2000;"
+    mw.b ${ramdisk_addr_r} 0 0x4000; \
+    mmc read ${ramdisk_addr_r} ${mmc_env} 0x20; \
+    env import -c ${ramdisk_addr_r} 0x2000 || \
+    env import -c ${ramdisk_addr_r} 0x4000;"
 
 setenv storebootstate " \
     echo 'storing env...'; \
-    env export -c -s 0x2000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT; \
-    mmc write ${ramdisk_addr_r} ${mmc_env} 0x10;"
+    mw.b ${ramdisk_addr_r} 0 0x4000; \
+    env export -c -s 0x4000 ${ramdisk_addr_r} BOOT_ORDER BOOT_A_LEFT BOOT_B_LEFT; \
+    mmc write ${ramdisk_addr_r} ${mmc_env} 0x20;"
 
 run loadbootstate
 test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"

buildroot-external/board/hardkernel/patches/README.md

@@ -0,0 +1,2 @@
+# Kernel
+https://github.com/akuster/meta-odroid

buildroot-external/board/hardkernel/patches/linux/0001-ARM64-defconfig-enable-CEC-support.patch

@@ -0,0 +1,47 @@
+From 6763c7964e9cb28e21497eee0032be053461bba5 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Mon, 13 Nov 2017 12:09:40 +0100
+Subject: [PATCH 01/53] ARM64: defconfig: enable CEC support
+
+Turn on CONFIG_CEC_SUPPORT and CONFIG_CEC_PLATFORM_DRIVERS
+Turn on CONFIG_VIDEO_MESON_AO_CEC as module
+Turn on CONFIG_DRM_DW_HDMI_CEC as module
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ arch/arm64/configs/defconfig | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index db8d364f8476..ab1cb51319e7 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -413,6 +413,7 @@ CONFIG_MEDIA_SUPPORT=m
+ CONFIG_MEDIA_CAMERA_SUPPORT=y
+ CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+ CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_CEC_SUPPORT=y
+ CONFIG_MEDIA_CONTROLLER=y
+ CONFIG_VIDEO_V4L2_SUBDEV_API=y
+ # CONFIG_DVB_NET is not set
+@@ -424,6 +425,8 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
+ CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+ CONFIG_VIDEO_RENESAS_FCP=m
+ CONFIG_VIDEO_RENESAS_VSP1=m
++CONFIG_CEC_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MESON_AO_CEC=m
+ CONFIG_DRM=m
+ CONFIG_DRM_NOUVEAU=m
+ CONFIG_DRM_EXYNOS=m
+@@ -444,6 +447,7 @@ CONFIG_DRM_RCAR_LVDS=m
+ CONFIG_DRM_TEGRA=m
+ CONFIG_DRM_PANEL_SIMPLE=m
+ CONFIG_DRM_I2C_ADV7511=m
++CONFIG_DRM_DW_HDMI_CEC=m
+ CONFIG_DRM_VC4=m
+ CONFIG_DRM_HISI_HIBMC=m
+ CONFIG_DRM_HISI_KIRIN=m
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0001-exynos5422-odroidhc1.dts-fix-booting-from-mmc.patch

@@ -0,0 +1,72 @@
+From 7041ca0d550d3a9caed54857365cf504eaeea756 Mon Sep 17 00:00:00 2001
+From: Armin Kuster <akuster@mvista.com>
+Date: Fri, 23 Mar 2018 09:02:44 -0700
+Subject: [PATCH] exynos5422-odroidhc1.dts: fix booting from mmc
+
+Signed-off-by: Armin Kuster <akuster@mvista.com>
+---
+ arch/arm/boot/dts/exynos5422-odroidhc1.dts | 37 ++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
+index fb8e8ae..c7adecf 100644
+--- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
++++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
+@@ -11,6 +11,7 @@
+ */
+ 
+ /dts-v1/;
++#include <dt-bindings/input/input.h>
+ #include "exynos5422-odroid-core.dtsi"
+ 
+ / {
+@@ -30,6 +31,14 @@
+ 		};
+ 	};
+ 
++        emmc_pwrseq: pwrseq {
++                pinctrl-0 = <&emmc_nrst_pin>;
++                pinctrl-names = "default";
++                compatible = "mmc-pwrseq-emmc";
++                reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
++        };
++
++
+ 	thermal-zones {
+ 		cpu0_thermal: cpu0-thermal {
+ 			thermal-sensors = <&tmu_cpu0 0>;
+@@ -211,3 +220,31 @@
+ &usbdrd_dwc3_1 {
+ 	dr_mode = "host";
+ };
++
++&mmc_0 {
++        status = "okay";
++        mmc-pwrseq = <&emmc_pwrseq>;
++        card-detect-delay = <200>;
++        samsung,dw-mshc-ciu-div = <3>;
++        samsung,dw-mshc-sdr-timing = <0 4>;
++        samsung,dw-mshc-ddr-timing = <0 2>;
++        samsung,dw-mshc-hs400-timing = <0 2>;
++        samsung,read-strobe-delay = <90>;
++        pinctrl-names = "default";
++        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
++        bus-width = <8>;
++        cap-mmc-highspeed;
++        mmc-hs200-1_8v;
++        mmc-hs400-1_8v;
++        vmmc-supply = <&ldo18_reg>;
++        vqmmc-supply = <&ldo3_reg>;
++};
++
++&pinctrl_1 {
++        emmc_nrst_pin: emmc-nrst {
++                samsung,pins = "gpd1-0";
++                samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
++                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
++                samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
++        };
++};
+-- 
+2.7.4
+

buildroot-external/board/hardkernel/patches/linux/0002-ASoC-meson-add-meson-audio-core-driver.patch

@@ -0,0 +1,290 @@
+From 6b2734923e6bf1d4bd98f918400e2c7a692a8db0 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 30 Mar 2017 11:49:55 +0200
+Subject: [PATCH 02/53] ASoC: meson: add meson audio core driver
+
+This patch adds support for the audio core driver for the Amlogic Meson SoC
+family. The purpose of this driver is to properly reset the audio block and
+provide register access for the different devices scattered in this address
+space. This includes output and input DMAs, pcm, i2s and spdif dai, card
+level routing, internal codec for the gxl variant
+
+For more information, please refer to the section 5 of the public datasheet
+of the S905 (gxbb). This datasheet is available here: [0].
+
+[0]: http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ sound/soc/meson/Kconfig      |  10 ++
+ sound/soc/meson/Makefile     |   4 +
+ sound/soc/meson/audio-core.c | 190 +++++++++++++++++++++++++++++++++++
+ sound/soc/meson/audio-core.h |  28 ++++++
+ 4 files changed, 232 insertions(+)
+ create mode 100644 sound/soc/meson/audio-core.c
+ create mode 100644 sound/soc/meson/audio-core.h
+
+diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
+index 8af8bc358a90..ed432d488b74 100644
+--- a/sound/soc/meson/Kconfig
++++ b/sound/soc/meson/Kconfig
+@@ -63,3 +63,13 @@ config SND_MESON_AXG_SPDIFOUT
+ 	  in the Amlogic AXG SoC family
+ 
+ endmenu
++
++menuconfig SND_SOC_MESON
++	tristate "ASoC support for Amlogic Meson SoCs"
++	depends on ARCH_MESON
++	select MFD_CORE
++	select REGMAP_MMIO
++	help
++	  Say Y or M if you want to add support for codecs attached to
++	  the Amlogic Meson SoCs Audio interfaces. You will also need to
++	  select the audio interfaces to support below.
+diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
+index c5e003b093db..768d7c414649 100644
+--- a/sound/soc/meson/Makefile
++++ b/sound/soc/meson/Makefile
+@@ -19,3 +19,7 @@ obj-$(CONFIG_SND_MESON_AXG_TDMIN) += snd-soc-meson-axg-tdmin.o
+ obj-$(CONFIG_SND_MESON_AXG_TDMOUT) += snd-soc-meson-axg-tdmout.o
+ obj-$(CONFIG_SND_MESON_AXG_SOUND_CARD) += snd-soc-meson-axg-sound-card.o
+ obj-$(CONFIG_SND_MESON_AXG_SPDIFOUT) += snd-soc-meson-axg-spdifout.o
++
++snd-soc-meson-audio-core-objs	 := audio-core.o
++
++obj-$(CONFIG_SND_SOC_MESON) += snd-soc-meson-audio-core.o
+\ No newline at end of file
+diff --git a/sound/soc/meson/audio-core.c b/sound/soc/meson/audio-core.c
+new file mode 100644
+index 000000000000..99993ec4a5cc
+--- /dev/null
++++ b/sound/soc/meson/audio-core.c
+@@ -0,0 +1,190 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/mfd/core.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++
++#include "audio-core.h"
++
++#define DRV_NAME "meson-audio-core"
++
++static const char * const acore_clock_names[] = { "aiu_top",
++						  "aiu_glue",
++						  "audin" };
++
++static int meson_acore_init_clocks(struct device *dev)
++{
++	struct clk *clock;
++	int i, ret;
++
++	for (i = 0; i < ARRAY_SIZE(acore_clock_names); i++) {
++		clock = devm_clk_get(dev, acore_clock_names[i]);
++		if (IS_ERR(clock)) {
++			if (PTR_ERR(clock) != -EPROBE_DEFER)
++				dev_err(dev, "Failed to get %s clock\n",
++					acore_clock_names[i]);
++			return PTR_ERR(clock);
++		}
++
++		ret = clk_prepare_enable(clock);
++		if (ret) {
++			dev_err(dev, "Failed to enable %s clock\n",
++				acore_clock_names[i]);
++			return ret;
++		}
++
++		ret = devm_add_action_or_reset(dev,
++				(void(*)(void *))clk_disable_unprepare,
++				clock);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static const char * const acore_reset_names[] = { "aiu",
++						  "audin" };
++
++static int meson_acore_init_resets(struct device *dev)
++{
++	struct reset_control *reset;
++	int i, ret;
++
++	for (i = 0; i < ARRAY_SIZE(acore_reset_names); i++) {
++		reset = devm_reset_control_get_exclusive(dev,
++							 acore_reset_names[i]);
++		if (IS_ERR(reset)) {
++			if (PTR_ERR(reset) != -EPROBE_DEFER)
++				dev_err(dev, "Failed to get %s reset\n",
++					acore_reset_names[i]);
++			return PTR_ERR(reset);
++		}
++
++		ret = reset_control_reset(reset);
++		if (ret) {
++			dev_err(dev, "Failed to pulse %s reset\n",
++				acore_reset_names[i]);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static const struct regmap_config meson_acore_regmap_config = {
++	.reg_bits       = 32,
++	.val_bits       = 32,
++	.reg_stride     = 4,
++};
++
++static const struct mfd_cell meson_acore_devs[] = {
++	{
++		.name = "meson-i2s-dai",
++		.of_compatible = "amlogic,meson-i2s-dai",
++	},
++	{
++		.name = "meson-spdif-dai",
++		.of_compatible = "amlogic,meson-spdif-dai",
++	},
++	{
++		.name = "meson-aiu-i2s-dma",
++		.of_compatible = "amlogic,meson-aiu-i2s-dma",
++	},
++	{
++		.name = "meson-aiu-spdif-dma",
++		.of_compatible = "amlogic,meson-aiu-spdif-dma",
++	},
++};
++
++static int meson_acore_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct meson_audio_core_data *data;
++	struct resource *res;
++	void __iomem *regs;
++	int ret;
++
++	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
++	if (!data)
++		return -ENOMEM;
++	platform_set_drvdata(pdev, data);
++
++	ret = meson_acore_init_clocks(dev);
++	if (ret)
++		return ret;
++
++	ret = meson_acore_init_resets(dev);
++	if (ret)
++		return ret;
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aiu");
++	regs = devm_ioremap_resource(dev, res);
++	if (IS_ERR(regs))
++		return PTR_ERR(regs);
++
++	data->aiu = devm_regmap_init_mmio(dev, regs,
++					  &meson_acore_regmap_config);
++	if (IS_ERR(data->aiu)) {
++		dev_err(dev, "Couldn't create the AIU regmap\n");
++		return PTR_ERR(data->aiu);
++	}
++
++	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audin");
++	regs = devm_ioremap_resource(dev, res);
++	if (IS_ERR(regs))
++		return PTR_ERR(regs);
++
++	data->audin = devm_regmap_init_mmio(dev, regs,
++					    &meson_acore_regmap_config);
++	if (IS_ERR(data->audin)) {
++		dev_err(dev, "Couldn't create the AUDIN regmap\n");
++		return PTR_ERR(data->audin);
++	}
++
++	return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, meson_acore_devs,
++				    ARRAY_SIZE(meson_acore_devs), NULL, 0,
++				    NULL);
++}
++
++static const struct of_device_id meson_acore_of_match[] = {
++	{ .compatible = "amlogic,meson-audio-core", },
++	{ .compatible = "amlogic,meson-gxbb-audio-core", },
++	{ .compatible = "amlogic,meson-gxl-audio-core", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, meson_acore_of_match);
++
++static struct platform_driver meson_acore_pdrv = {
++	.probe = meson_acore_probe,
++	.driver = {
++		.name = DRV_NAME,
++		.of_match_table = meson_acore_of_match,
++	},
++};
++module_platform_driver(meson_acore_pdrv);
++
++MODULE_DESCRIPTION("Meson Audio Core Driver");
++MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
++MODULE_LICENSE("GPL v2");
+diff --git a/sound/soc/meson/audio-core.h b/sound/soc/meson/audio-core.h
+new file mode 100644
+index 000000000000..6e7a24cdc4a9
+--- /dev/null
++++ b/sound/soc/meson/audio-core.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _MESON_AUDIO_CORE_H_
++#define _MESON_AUDIO_CORE_H_
++
++struct meson_audio_core_data {
++	struct regmap *aiu;
++	struct regmap *audin;
++};
++
++#endif /* _MESON_AUDIO_CORE_H_ */
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0003-ASoC-meson-add-register-definitions.patch

@@ -0,0 +1,360 @@
+From 0b2aabc632854e317544bb293cbc0c63e120ddfa Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 30 Mar 2017 12:00:10 +0200
+Subject: [PATCH 03/53] ASoC: meson: add register definitions
+
+Add the register definition for the AIU and AUDIN blocks
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ sound/soc/meson/aiu-regs.h   | 182 +++++++++++++++++++++++++++++++++++
+ sound/soc/meson/audin-regs.h | 148 ++++++++++++++++++++++++++++
+ 2 files changed, 330 insertions(+)
+ create mode 100644 sound/soc/meson/aiu-regs.h
+ create mode 100644 sound/soc/meson/audin-regs.h
+
+diff --git a/sound/soc/meson/aiu-regs.h b/sound/soc/meson/aiu-regs.h
+new file mode 100644
+index 000000000000..67391e64fe1c
+--- /dev/null
++++ b/sound/soc/meson/aiu-regs.h
+@@ -0,0 +1,182 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AIU_REGS_H_
++#define _AIU_REGS_H_
++
++#define AIU_958_BPF			0x000
++#define AIU_958_BRST			0x004
++#define AIU_958_LENGTH			0x008
++#define AIU_958_PADDSIZE		0x00C
++#define AIU_958_MISC			0x010
++#define AIU_958_FORCE_LEFT		0x014	/* Unknown */
++#define AIU_958_DISCARD_NUM		0x018
++#define AIU_958_DCU_FF_CTRL		0x01C
++#define AIU_958_CHSTAT_L0		0x020
++#define AIU_958_CHSTAT_L1		0x024
++#define AIU_958_CTRL			0x028
++#define AIU_958_RPT			0x02C
++#define AIU_I2S_MUTE_SWAP		0x030
++#define AIU_I2S_SOURCE_DESC		0x034
++#define AIU_I2S_MED_CTRL		0x038
++#define AIU_I2S_MED_THRESH		0x03C
++#define AIU_I2S_DAC_CFG			0x040
++#define AIU_I2S_SYNC			0x044	/* Unknown */
++#define AIU_I2S_MISC			0x048
++#define AIU_I2S_OUT_CFG			0x04C
++#define AIU_I2S_FF_CTRL			0x050	/* Unknown */
++#define AIU_RST_SOFT			0x054
++#define AIU_CLK_CTRL			0x058
++#define AIU_MIX_ADCCFG			0x05C
++#define AIU_MIX_CTRL			0x060
++#define AIU_CLK_CTRL_MORE		0x064
++#define AIU_958_POP			0x068
++#define AIU_MIX_GAIN			0x06C
++#define AIU_958_SYNWORD1		0x070
++#define AIU_958_SYNWORD2		0x074
++#define AIU_958_SYNWORD3		0x078
++#define AIU_958_SYNWORD1_MASK		0x07C
++#define AIU_958_SYNWORD2_MASK		0x080
++#define AIU_958_SYNWORD3_MASK		0x084
++#define AIU_958_FFRDOUT_THD		0x088
++#define AIU_958_LENGTH_PER_PAUSE	0x08C
++#define AIU_958_PAUSE_NUM		0x090
++#define AIU_958_PAUSE_PAYLOAD		0x094
++#define AIU_958_AUTO_PAUSE		0x098
++#define AIU_958_PAUSE_PD_LENGTH		0x09C
++#define AIU_CODEC_DAC_LRCLK_CTRL	0x0A0
++#define AIU_CODEC_ADC_LRCLK_CTRL	0x0A4
++#define AIU_HDMI_CLK_DATA_CTRL		0x0A8
++#define AIU_CODEC_CLK_DATA_CTRL		0x0AC
++#define AIU_ACODEC_CTRL			0x0B0
++#define AIU_958_CHSTAT_R0		0x0C0
++#define AIU_958_CHSTAT_R1		0x0C4
++#define AIU_958_VALID_CTRL		0x0C8
++#define AIU_AUDIO_AMP_REG0		0x0F0	/* Unknown */
++#define AIU_AUDIO_AMP_REG1		0x0F4	/* Unknown */
++#define AIU_AUDIO_AMP_REG2		0x0F8	/* Unknown */
++#define AIU_AUDIO_AMP_REG3		0x0FC	/* Unknown */
++#define AIU_AIFIFO2_CTRL		0x100
++#define AIU_AIFIFO2_STATUS		0x104
++#define AIU_AIFIFO2_GBIT		0x108
++#define AIU_AIFIFO2_CLB			0x10C
++#define AIU_CRC_CTRL			0x110
++#define AIU_CRC_STATUS			0x114
++#define AIU_CRC_SHIFT_REG		0x118
++#define AIU_CRC_IREG			0x11C
++#define AIU_CRC_CAL_REG1		0x120
++#define AIU_CRC_CAL_REG0		0x124
++#define AIU_CRC_POLY_COEF1		0x128
++#define AIU_CRC_POLY_COEF0		0x12C
++#define AIU_CRC_BIT_SIZE1		0x130
++#define AIU_CRC_BIT_SIZE0		0x134
++#define AIU_CRC_BIT_CNT1		0x138
++#define AIU_CRC_BIT_CNT0		0x13C
++#define AIU_AMCLK_GATE_HI		0x140
++#define AIU_AMCLK_GATE_LO		0x144
++#define AIU_AMCLK_MSR			0x148
++#define AIU_AUDAC_CTRL0			0x14C	/* Unknown */
++#define AIU_DELTA_SIGMA0		0x154	/* Unknown */
++#define AIU_DELTA_SIGMA1		0x158	/* Unknown */
++#define AIU_DELTA_SIGMA2		0x15C	/* Unknown */
++#define AIU_DELTA_SIGMA3		0x160	/* Unknown */
++#define AIU_DELTA_SIGMA4		0x164	/* Unknown */
++#define AIU_DELTA_SIGMA5		0x168	/* Unknown */
++#define AIU_DELTA_SIGMA6		0x16C	/* Unknown */
++#define AIU_DELTA_SIGMA7		0x170	/* Unknown */
++#define AIU_DELTA_SIGMA_LCNTS		0x174	/* Unknown */
++#define AIU_DELTA_SIGMA_RCNTS		0x178	/* Unknown */
++#define AIU_MEM_I2S_START_PTR		0x180
++#define AIU_MEM_I2S_RD_PTR		0x184
++#define AIU_MEM_I2S_END_PTR		0x188
++#define AIU_MEM_I2S_MASKS		0x18C
++#define AIU_MEM_I2S_CONTROL		0x190
++#define AIU_MEM_IEC958_START_PTR	0x194
++#define AIU_MEM_IEC958_RD_PTR		0x198
++#define AIU_MEM_IEC958_END_PTR		0x19C
++#define AIU_MEM_IEC958_MASKS		0x1A0
++#define AIU_MEM_IEC958_CONTROL		0x1A4
++#define AIU_MEM_AIFIFO2_START_PTR	0x1A8
++#define AIU_MEM_AIFIFO2_CURR_PTR	0x1AC
++#define AIU_MEM_AIFIFO2_END_PTR		0x1B0
++#define AIU_MEM_AIFIFO2_BYTES_AVAIL	0x1B4
++#define AIU_MEM_AIFIFO2_CONTROL		0x1B8
++#define AIU_MEM_AIFIFO2_MAN_WP		0x1BC
++#define AIU_MEM_AIFIFO2_MAN_RP		0x1C0
++#define AIU_MEM_AIFIFO2_LEVEL		0x1C4
++#define AIU_MEM_AIFIFO2_BUF_CNTL	0x1C8
++#define AIU_MEM_I2S_MAN_WP		0x1CC
++#define AIU_MEM_I2S_MAN_RP		0x1D0
++#define AIU_MEM_I2S_LEVEL		0x1D4
++#define AIU_MEM_I2S_BUF_CNTL		0x1D8
++#define AIU_MEM_I2S_BUF_WRAP_COUNT	0x1DC
++#define AIU_MEM_I2S_MEM_CTL		0x1E0
++#define AIU_MEM_IEC958_MEM_CTL		0x1E4
++#define AIU_MEM_IEC958_WRAP_COUNT	0x1E8
++#define AIU_MEM_IEC958_IRQ_LEVEL	0x1EC
++#define AIU_MEM_IEC958_MAN_WP		0x1F0
++#define AIU_MEM_IEC958_MAN_RP		0x1F4
++#define AIU_MEM_IEC958_LEVEL		0x1F8
++#define AIU_MEM_IEC958_BUF_CNTL		0x1FC
++#define AIU_AIFIFO_CTRL			0x200
++#define AIU_AIFIFO_STATUS		0x204
++#define AIU_AIFIFO_GBIT			0x208
++#define AIU_AIFIFO_CLB			0x20C
++#define AIU_MEM_AIFIFO_START_PTR	0x210
++#define AIU_MEM_AIFIFO_CURR_PTR		0x214
++#define AIU_MEM_AIFIFO_END_PTR		0x218
++#define AIU_MEM_AIFIFO_BYTES_AVAIL	0x21C
++#define AIU_MEM_AIFIFO_CONTROL		0x220
++#define AIU_MEM_AIFIFO_MAN_WP		0x224
++#define AIU_MEM_AIFIFO_MAN_RP		0x228
++#define AIU_MEM_AIFIFO_LEVEL		0x22C
++#define AIU_MEM_AIFIFO_BUF_CNTL		0x230
++#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT	0x234
++#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT	0x238
++#define AIU_MEM_AIFIFO_MEM_CTL		0x23C
++#define AIFIFO_TIME_STAMP_CNTL		0x240
++#define AIFIFO_TIME_STAMP_SYNC_0	0x244
++#define AIFIFO_TIME_STAMP_SYNC_1	0x248
++#define AIFIFO_TIME_STAMP_0		0x24C
++#define AIFIFO_TIME_STAMP_1		0x250
++#define AIFIFO_TIME_STAMP_2		0x254
++#define AIFIFO_TIME_STAMP_3		0x258
++#define AIFIFO_TIME_STAMP_LENGTH	0x25C
++#define AIFIFO2_TIME_STAMP_CNTL		0x260
++#define AIFIFO2_TIME_STAMP_SYNC_0	0x264
++#define AIFIFO2_TIME_STAMP_SYNC_1	0x268
++#define AIFIFO2_TIME_STAMP_0		0x26C
++#define AIFIFO2_TIME_STAMP_1		0x270
++#define AIFIFO2_TIME_STAMP_2		0x274
++#define AIFIFO2_TIME_STAMP_3		0x278
++#define AIFIFO2_TIME_STAMP_LENGTH	0x27C
++#define IEC958_TIME_STAMP_CNTL		0x280
++#define IEC958_TIME_STAMP_SYNC_0	0x284
++#define IEC958_TIME_STAMP_SYNC_1	0x288
++#define IEC958_TIME_STAMP_0		0x28C
++#define IEC958_TIME_STAMP_1		0x290
++#define IEC958_TIME_STAMP_2		0x294
++#define IEC958_TIME_STAMP_3		0x298
++#define IEC958_TIME_STAMP_LENGTH	0x29C
++#define AIU_MEM_AIFIFO2_MEM_CTL		0x2A0
++#define AIU_I2S_CBUS_DDR_CNTL		0x2A4
++#define AIU_I2S_CBUS_DDR_WDATA		0x2A8
++#define AIU_I2S_CBUS_DDR_ADDR		0x2AC
++
++#endif /* _AIU_REGS_H_ */
+diff --git a/sound/soc/meson/audin-regs.h b/sound/soc/meson/audin-regs.h
+new file mode 100644
+index 000000000000..f224610e80e7
+--- /dev/null
++++ b/sound/soc/meson/audin-regs.h
+@@ -0,0 +1,148 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _AUDIN_REGS_H_
++#define _AUDIN_REGS_H_
++
++/*
++ * Note :
++ * Datasheet issue page 196
++ * AUDIN_MUTE_VAL 0x35 => impossible: Already assigned to AUDIN_FIFO1_PTR
++ * AUDIN_FIFO1_PTR is more likely to be correct here since surrounding registers
++ * also deal with AUDIN_FIFO1
++ *
++ * Clarification needed from Amlogic
++ */
++
++#define AUDIN_SPDIF_MODE		0x000
++#define AUDIN_SPDIF_FS_CLK_RLTN		0x004
++#define AUDIN_SPDIF_CHNL_STS_A		0x008
++#define AUDIN_SPDIF_CHNL_STS_B		0x00C
++#define AUDIN_SPDIF_MISC		0x010
++#define AUDIN_SPDIF_NPCM_PCPD		0x014
++#define AUDIN_SPDIF_END			0x03C	/* Unknown */
++#define AUDIN_I2SIN_CTRL		0x040
++#define AUDIN_SOURCE_SEL		0x044
++#define AUDIN_DECODE_FORMAT		0x048
++#define AUDIN_DECODE_CONTROL_STATUS	0x04C
++#define AUDIN_DECODE_CHANNEL_STATUS_A_0	0x050
++#define AUDIN_DECODE_CHANNEL_STATUS_A_1	0x054
++#define AUDIN_DECODE_CHANNEL_STATUS_A_2	0x058
++#define AUDIN_DECODE_CHANNEL_STATUS_A_3	0x05C
++#define AUDIN_DECODE_CHANNEL_STATUS_A_4	0x060
++#define AUDIN_DECODE_CHANNEL_STATUS_A_5	0x064
++#define AUDIN_FIFO0_START		0x080
++#define AUDIN_FIFO0_END			0x084
++#define AUDIN_FIFO0_PTR			0x088
++#define AUDIN_FIFO0_INTR		0x08C
++#define AUDIN_FIFO0_RDPTR		0x090
++#define AUDIN_FIFO0_CTRL		0x094
++#define AUDIN_FIFO0_CTRL1		0x098
++#define AUDIN_FIFO0_LVL0		0x09C
++#define AUDIN_FIFO0_LVL1		0x0A0
++#define AUDIN_FIFO0_LVL2		0x0A4
++#define AUDIN_FIFO0_REQID		0x0C0
++#define AUDIN_FIFO0_WRAP		0x0C4
++#define AUDIN_FIFO1_START		0x0CC
++#define AUDIN_FIFO1_END			0x0D0
++#define AUDIN_FIFO1_PTR			0x0D4
++#define AUDIN_FIFO1_INTR		0x0D8
++#define AUDIN_FIFO1_RDPTR		0x0DC
++#define AUDIN_FIFO1_CTRL		0x0E0
++#define AUDIN_FIFO1_CTRL1		0x0E4
++#define AUDIN_FIFO1_LVL0		0x100
++#define AUDIN_FIFO1_LVL1		0x104
++#define AUDIN_FIFO1_LVL2		0x108
++#define AUDIN_FIFO1_REQID		0x10C
++#define AUDIN_FIFO1_WRAP		0x110
++#define AUDIN_FIFO2_START		0x114
++#define AUDIN_FIFO2_END			0x118
++#define AUDIN_FIFO2_PTR			0x11C
++#define AUDIN_FIFO2_INTR		0x120
++#define AUDIN_FIFO2_RDPTR		0x124
++#define AUDIN_FIFO2_CTRL		0x128
++#define AUDIN_FIFO2_CTRL1		0x12C
++#define AUDIN_FIFO2_LVL0		0x130
++#define AUDIN_FIFO2_LVL1		0x134
++#define AUDIN_FIFO2_LVL2		0x138
++#define AUDIN_FIFO2_REQID		0x13C
++#define AUDIN_FIFO2_WRAP		0x140
++#define AUDIN_INT_CTRL			0x144
++#define AUDIN_FIFO_INT			0x148
++#define PCMIN_CTRL0			0x180
++#define PCMIN_CTRL1			0x184
++#define PCMIN1_CTRL0			0x188
++#define PCMIN1_CTRL1			0x18C
++#define PCMOUT_CTRL0			0x1C0
++#define PCMOUT_CTRL1			0x1C4
++#define PCMOUT_CTRL2			0x1C8
++#define PCMOUT_CTRL3			0x1CC
++#define PCMOUT1_CTRL0			0x1D0
++#define PCMOUT1_CTRL1			0x1D4
++#define PCMOUT1_CTRL2			0x1D8
++#define PCMOUT1_CTRL3			0x1DC
++#define AUDOUT_CTRL			0x200
++#define AUDOUT_CTRL1			0x204
++#define AUDOUT_BUF0_STA			0x208
++#define AUDOUT_BUF0_EDA			0x20C
++#define AUDOUT_BUF0_WPTR		0x210
++#define AUDOUT_BUF1_STA			0x214
++#define AUDOUT_BUF1_EDA			0x218
++#define AUDOUT_BUF1_WPTR		0x21C
++#define AUDOUT_FIFO_RPTR		0x220
++#define AUDOUT_INTR_PTR			0x224
++#define AUDOUT_FIFO_STS			0x228
++#define AUDOUT1_CTRL			0x240
++#define AUDOUT1_CTRL1			0x244
++#define AUDOUT1_BUF0_STA		0x248
++#define AUDOUT1_BUF0_EDA		0x24C
++#define AUDOUT1_BUF0_WPTR		0x250
++#define AUDOUT1_BUF1_STA		0x254
++#define AUDOUT1_BUF1_EDA		0x258
++#define AUDOUT1_BUF1_WPTR		0x25C
++#define AUDOUT1_FIFO_RPTR		0x260
++#define AUDOUT1_INTR_PTR		0x264
++#define AUDOUT1_FIFO_STS		0x268
++#define AUDIN_HDMI_MEAS_CTRL		0x280
++#define AUDIN_HDMI_MEAS_CYCLES_M1	0x284
++#define AUDIN_HDMI_MEAS_INTR_MASKN	0x288
++#define AUDIN_HDMI_MEAS_INTR_STAT	0x28C
++#define AUDIN_HDMI_REF_CYCLES_STAT_0	0x290
++#define AUDIN_HDMI_REF_CYCLES_STAT_1	0x294
++#define AUDIN_HDMIRX_AFIFO_STAT		0x298
++#define AUDIN_FIFO0_PIO_STS		0x2C0
++#define AUDIN_FIFO0_PIO_RDL		0x2C4
++#define AUDIN_FIFO0_PIO_RDH		0x2C8
++#define AUDIN_FIFO1_PIO_STS		0x2CC
++#define AUDIN_FIFO1_PIO_RDL		0x2D0
++#define AUDIN_FIFO1_PIO_RDH		0x2D4
++#define AUDIN_FIFO2_PIO_STS		0x2D8
++#define AUDIN_FIFO2_PIO_RDL		0x2DC
++#define AUDIN_FIFO2_PIO_RDH		0x2E0
++#define AUDOUT_FIFO_PIO_STS		0x2E4
++#define AUDOUT_FIFO_PIO_WRL		0x2E8
++#define AUDOUT_FIFO_PIO_WRH		0x2EC
++#define AUDOUT1_FIFO_PIO_STS		0x2F0	/* Unknown */
++#define AUDOUT1_FIFO_PIO_WRL		0x2F4	/* Unknown */
++#define AUDOUT1_FIFO_PIO_WRH		0x2F8	/* Unknown */
++#define AUD_RESAMPLE_CTRL0		0x2FC
++#define AUD_RESAMPLE_CTRL1		0x300
++#define AUD_RESAMPLE_STATUS		0x304
++
++#endif /* _AUDIN_REGS_H_ */
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0004-ASoC-meson-add-aiu-i2s-dma-support.patch

@@ -0,0 +1,424 @@
+From 61d387ffa57865531ead1a33d63b1d53a99e808b Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 30 Mar 2017 12:14:40 +0200
+Subject: [PATCH 04/53] ASoC: meson: add aiu i2s dma support
+
+Add support for the i2s output dma which is part of the AIU block
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ sound/soc/meson/Kconfig       |   7 +
+ sound/soc/meson/Makefile      |   4 +-
+ sound/soc/meson/aiu-i2s-dma.c | 370 ++++++++++++++++++++++++++++++++++
+ 3 files changed, 380 insertions(+), 1 deletion(-)
+ create mode 100644 sound/soc/meson/aiu-i2s-dma.c
+
+diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
+index ed432d488b74..6e030b5c7804 100644
+--- a/sound/soc/meson/Kconfig
++++ b/sound/soc/meson/Kconfig
+@@ -73,3 +73,10 @@ menuconfig SND_SOC_MESON
+ 	  Say Y or M if you want to add support for codecs attached to
+ 	  the Amlogic Meson SoCs Audio interfaces. You will also need to
+ 	  select the audio interfaces to support below.
++
++config SND_SOC_MESON_I2S
++	tristate "Meson i2s interface"
++	depends on SND_SOC_MESON
++	help
++	  Say Y or M if you want to add support for i2s dma driver for Amlogic
++	  Meson SoCs.
+diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
+index 768d7c414649..57960077aab2 100644
+--- a/sound/soc/meson/Makefile
++++ b/sound/soc/meson/Makefile
+@@ -21,5 +21,7 @@ obj-$(CONFIG_SND_MESON_AXG_SOUND_CARD) += snd-soc-meson-axg-sound-card.o
+ obj-$(CONFIG_SND_MESON_AXG_SPDIFOUT) += snd-soc-meson-axg-spdifout.o
+ 
+ snd-soc-meson-audio-core-objs	 := audio-core.o
++snd-soc-meson-aiu-i2s-dma-objs	 := aiu-i2s-dma.o
+ 
+-obj-$(CONFIG_SND_SOC_MESON) += snd-soc-meson-audio-core.o
+\ No newline at end of file
++obj-$(CONFIG_SND_SOC_MESON) += snd-soc-meson-audio-core.o
++obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-aiu-i2s-dma.o
+\ No newline at end of file
+diff --git a/sound/soc/meson/aiu-i2s-dma.c b/sound/soc/meson/aiu-i2s-dma.c
+new file mode 100644
+index 000000000000..2684bd0db19e
+--- /dev/null
++++ b/sound/soc/meson/aiu-i2s-dma.c
+@@ -0,0 +1,370 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#include "aiu-regs.h"
++#include "audio-core.h"
++
++#define DRV_NAME "meson-aiu-i2s-dma"
++
++struct aiu_i2s_dma {
++	struct meson_audio_core_data *core;
++	struct clk *fast;
++	int irq;
++};
++
++#define AIU_MEM_I2S_BUF_CNTL_INIT		BIT(0)
++#define AIU_MEM_I2S_CONTROL_INIT		BIT(0)
++#define AIU_MEM_I2S_CONTROL_FILL_EN		BIT(1)
++#define AIU_MEM_I2S_CONTROL_EMPTY_EN		BIT(2)
++#define AIU_MEM_I2S_CONTROL_MODE_16BIT		BIT(6)
++#define AIU_MEM_I2S_CONTROL_BUSY		BIT(7)
++#define AIU_MEM_I2S_CONTROL_DATA_READY		BIT(8)
++#define AIU_MEM_I2S_CONTROL_LEVEL_CNTL		BIT(9)
++#define AIU_MEM_I2S_MASKS_IRQ_BLOCK_MASK	GENMASK(31, 16)
++#define AIU_MEM_I2S_MASKS_IRQ_BLOCK(n)		((n) << 16)
++#define AIU_MEM_I2S_MASKS_CH_MEM_MASK		GENMASK(15, 8)
++#define AIU_MEM_I2S_MASKS_CH_MEM(ch)		((ch) << 8)
++#define AIU_MEM_I2S_MASKS_CH_RD_MASK		GENMASK(7, 0)
++#define AIU_MEM_I2S_MASKS_CH_RD(ch)		((ch) << 0)
++#define AIU_RST_SOFT_I2S_FAST_DOMAIN		BIT(0)
++#define AIU_RST_SOFT_I2S_SLOW_DOMAIN		BIT(1)
++
++/*
++ * The DMA works by i2s "blocks" (or DMA burst). The burst size and the memory
++ * layout expected depends on the mode of operation.
++ *
++ * - Normal mode: The channels are expected to be packed in 32 bytes groups
++ *  interleaved the buffer. AIU_MEM_I2S_MASKS_CH_MEM is a bitfield representing
++ *  the channels present in memory. AIU_MEM_I2S_MASKS_CH_MEM represents the
++ *  channels read by the DMA. This is very flexible but the unsual memory layout
++ *  makes it less easy to deal with. The burst size is 32 bytes times the number
++ *  of channels read.
++ *
++ * - Split mode:
++ * Classical channel interleaved frame organisation. In this mode,
++ * AIU_MEM_I2S_MASKS_CH_MEM and AIU_MEM_I2S_MASKS_CH_MEM must be set to 0xff and
++ * the burst size is fixed to 256 bytes. The input can be either 2 or 8
++ * channels.
++ *
++ * The following driver implements the split mode.
++ */
++
++#define AIU_I2S_DMA_BURST 256
++
++static struct snd_pcm_hardware aiu_i2s_dma_hw = {
++	.info = (SNDRV_PCM_INFO_INTERLEAVED |
++		 SNDRV_PCM_INFO_MMAP |
++		 SNDRV_PCM_INFO_MMAP_VALID |
++		 SNDRV_PCM_INFO_PAUSE),
++
++	.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++		    SNDRV_PCM_FMTBIT_S24_LE |
++		    SNDRV_PCM_FMTBIT_S32_LE),
++
++	/*
++	 * TODO: The DMA can change the endianness, the msb position
++	 * and deal with unsigned - support this later on
++	 */
++
++	.rate_min = 8000,
++	.rate_max = 192000,
++	.channels_min = 2,
++	.channels_max = 8,
++	.period_bytes_min = AIU_I2S_DMA_BURST,
++	.period_bytes_max = AIU_I2S_DMA_BURST * 65535,
++	.periods_min = 2,
++	.periods_max = UINT_MAX,
++	.buffer_bytes_max = 1 * 1024 * 1024,
++	.fifo_size = 0,
++};
++
++static struct aiu_i2s_dma *aiu_i2s_dma_priv(struct snd_pcm_substream *s)
++{
++	struct snd_soc_pcm_runtime *rtd = s->private_data;
++	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
++
++	return snd_soc_component_get_drvdata(component);
++}
++
++static snd_pcm_uframes_t
++aiu_i2s_dma_pointer(struct snd_pcm_substream *substream)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
++	unsigned int addr;
++	int ret;
++
++	ret = regmap_read(priv->core->aiu, AIU_MEM_I2S_RD_PTR,
++			  &addr);
++	if (ret)
++		return 0;
++
++	return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
++}
++
++static void __dma_enable(struct aiu_i2s_dma *priv, bool enable)
++{
++	unsigned int en_mask = (AIU_MEM_I2S_CONTROL_FILL_EN |
++				AIU_MEM_I2S_CONTROL_EMPTY_EN);
++
++	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL, en_mask,
++			   enable ? en_mask : 0);
++
++}
++
++static int aiu_i2s_dma_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		__dma_enable(priv, true);
++		break;
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++	case SNDRV_PCM_TRIGGER_STOP:
++		__dma_enable(priv, false);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static void __dma_init_mem(struct aiu_i2s_dma *priv)
++{
++	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL,
++			   AIU_MEM_I2S_CONTROL_INIT,
++			   AIU_MEM_I2S_CONTROL_INIT);
++	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_BUF_CNTL,
++			   AIU_MEM_I2S_BUF_CNTL_INIT,
++			   AIU_MEM_I2S_BUF_CNTL_INIT);
++
++	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL,
++			   AIU_MEM_I2S_CONTROL_INIT,
++			   0);
++	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_BUF_CNTL,
++			   AIU_MEM_I2S_BUF_CNTL_INIT,
++			   0);
++}
++
++static int aiu_i2s_dma_prepare(struct snd_pcm_substream *substream)
++{
++	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
++
++	__dma_init_mem(priv);
++
++	return 0;
++}
++
++static int aiu_i2s_dma_hw_params(struct snd_pcm_substream *substream,
++				 struct snd_pcm_hw_params *params)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
++	int ret;
++	u32 burst_num, mem_ctl;
++	dma_addr_t end_ptr;
++
++	ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
++	if (ret < 0)
++		return ret;
++
++	/* Setup memory layout */
++	if (params_physical_width(params) == 16)
++		mem_ctl = AIU_MEM_I2S_CONTROL_MODE_16BIT;
++	else
++		mem_ctl = 0;
++
++	regmap_update_bits(priv->core->aiu, AIU_MEM_I2S_CONTROL,
++			   AIU_MEM_I2S_CONTROL_MODE_16BIT,
++			   mem_ctl);
++
++	/* Initialize memory pointers */
++	regmap_write(priv->core->aiu, AIU_MEM_I2S_START_PTR, runtime->dma_addr);
++	regmap_write(priv->core->aiu, AIU_MEM_I2S_RD_PTR, runtime->dma_addr);
++
++	/* The end pointer is the address of the last valid block */
++	end_ptr = runtime->dma_addr + runtime->dma_bytes - AIU_I2S_DMA_BURST;
++	regmap_write(priv->core->aiu, AIU_MEM_I2S_END_PTR, end_ptr);
++
++	/* Memory masks */
++	burst_num = params_period_bytes(params) / AIU_I2S_DMA_BURST;
++	regmap_write(priv->core->aiu, AIU_MEM_I2S_MASKS,
++		     AIU_MEM_I2S_MASKS_CH_RD(0xff) |
++		     AIU_MEM_I2S_MASKS_CH_MEM(0xff) |
++		     AIU_MEM_I2S_MASKS_IRQ_BLOCK(burst_num));
++
++	return 0;
++}
++
++static int aiu_i2s_dma_hw_free(struct snd_pcm_substream *substream)
++{
++	return snd_pcm_lib_free_pages(substream);
++}
++
++
++static irqreturn_t aiu_i2s_dma_irq_block(int irq, void *dev_id)
++{
++	struct snd_pcm_substream *playback = dev_id;
++
++	snd_pcm_period_elapsed(playback);
++
++	return IRQ_HANDLED;
++}
++
++static int aiu_i2s_dma_open(struct snd_pcm_substream *substream)
++{
++	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
++	int ret;
++
++	snd_soc_set_runtime_hwparams(substream, &aiu_i2s_dma_hw);
++
++	/*
++	 * Make sure the buffer and period size are multiple of the DMA burst
++	 * size
++	 */
++	ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
++					 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
++					 AIU_I2S_DMA_BURST);
++	if (ret)
++		return ret;
++
++	ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
++					 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
++					 AIU_I2S_DMA_BURST);
++	if (ret)
++		return ret;
++
++	/* Request the I2S DDR irq */
++	ret = request_irq(priv->irq, aiu_i2s_dma_irq_block, 0,
++			  DRV_NAME, substream);
++	if (ret)
++		return ret;
++
++	/* Power up the i2s fast domain - can't write the registers w/o it */
++	ret = clk_prepare_enable(priv->fast);
++	if (ret)
++		return ret;
++
++	/* Make sure the dma is initially disabled */
++	__dma_enable(priv, false);
++
++	return 0;
++}
++
++static int aiu_i2s_dma_close(struct snd_pcm_substream *substream)
++{
++	struct aiu_i2s_dma *priv = aiu_i2s_dma_priv(substream);
++
++	clk_disable_unprepare(priv->fast);
++	free_irq(priv->irq, substream);
++
++	return 0;
++}
++
++static const struct snd_pcm_ops aiu_i2s_dma_ops = {
++	.open =		aiu_i2s_dma_open,
++	.close =        aiu_i2s_dma_close,
++	.ioctl =	snd_pcm_lib_ioctl,
++	.hw_params =	aiu_i2s_dma_hw_params,
++	.hw_free =      aiu_i2s_dma_hw_free,
++	.prepare =      aiu_i2s_dma_prepare,
++	.pointer =	aiu_i2s_dma_pointer,
++	.trigger =	aiu_i2s_dma_trigger,
++};
++
++static int aiu_i2s_dma_new(struct snd_soc_pcm_runtime *rtd)
++{
++	struct snd_card *card = rtd->card->snd_card;
++	size_t size = aiu_i2s_dma_hw.buffer_bytes_max;
++
++	return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
++						     SNDRV_DMA_TYPE_DEV,
++						     card->dev, size, size);
++}
++
++static const struct snd_soc_component_driver aiu_i2s_platform = {
++	.ops = &aiu_i2s_dma_ops,
++	.pcm_new = aiu_i2s_dma_new,
++	.name = DRV_NAME,
++};
++
++static int aiu_i2s_dma_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct aiu_i2s_dma *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, priv);
++	priv->core = dev_get_drvdata(dev->parent);
++
++	priv->fast = devm_clk_get(dev, "fast");
++	if (IS_ERR(priv->fast)) {
++		if (PTR_ERR(priv->fast) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get i2s fast domain clock\n");
++		return PTR_ERR(priv->fast);
++	}
++
++	priv->irq = platform_get_irq(pdev, 0);
++	if (priv->irq <= 0) {
++		dev_err(dev, "Can't get i2s ddr irq\n");
++		return priv->irq;
++	}
++
++	return devm_snd_soc_register_component(dev, &aiu_i2s_platform,
++					       NULL, 0);
++}
++
++static const struct of_device_id aiu_i2s_dma_of_match[] = {
++	{ .compatible = "amlogic,meson-aiu-i2s-dma", },
++	{ .compatible = "amlogic,meson-gxbb-aiu-i2s-dma", },
++	{ .compatible = "amlogic,meson-gxl-aiu-i2s-dma", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, aiu_i2s_dma_of_match);
++
++static struct platform_driver aiu_i2s_dma_pdrv = {
++	.probe = aiu_i2s_dma_probe,
++	.driver = {
++		.name = DRV_NAME,
++		.of_match_table = aiu_i2s_dma_of_match,
++	},
++};
++module_platform_driver(aiu_i2s_dma_pdrv);
++
++MODULE_DESCRIPTION("Meson AIU i2s DMA ASoC Driver");
++MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0005-ASoC-meson-add-initial-i2s-dai-support.patch

@@ -0,0 +1,518 @@
+From 91eb80de0a4425e8856484d6480b2e347ccfa83d Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 30 Mar 2017 12:17:27 +0200
+Subject: [PATCH 05/53] ASoC: meson: add initial i2s dai support
+
+Add support for the i2s dai found on Amlogic Meson SoC family.
+With this initial implementation, only playback is supported.
+Capture will be part of furture work.
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ sound/soc/meson/Kconfig   |   2 +-
+ sound/soc/meson/Makefile  |   4 +-
+ sound/soc/meson/i2s-dai.c | 465 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 469 insertions(+), 2 deletions(-)
+ create mode 100644 sound/soc/meson/i2s-dai.c
+
+diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
+index 6e030b5c7804..5904e9e50569 100644
+--- a/sound/soc/meson/Kconfig
++++ b/sound/soc/meson/Kconfig
+@@ -78,5 +78,5 @@ config SND_SOC_MESON_I2S
+ 	tristate "Meson i2s interface"
+ 	depends on SND_SOC_MESON
+ 	help
+-	  Say Y or M if you want to add support for i2s dma driver for Amlogic
++	  Say Y or M if you want to add support for i2s driver for Amlogic
+ 	  Meson SoCs.
+diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
+index 57960077aab2..b8641f9f7fc1 100644
+--- a/sound/soc/meson/Makefile
++++ b/sound/soc/meson/Makefile
+@@ -22,6 +22,8 @@ obj-$(CONFIG_SND_MESON_AXG_SPDIFOUT) += snd-soc-meson-axg-spdifout.o
+ 
+ snd-soc-meson-audio-core-objs	 := audio-core.o
+ snd-soc-meson-aiu-i2s-dma-objs	 := aiu-i2s-dma.o
++snd-soc-meson-i2s-dai-objs	 := i2s-dai.o
+ 
+ obj-$(CONFIG_SND_SOC_MESON) += snd-soc-meson-audio-core.o
+-obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-aiu-i2s-dma.o
+\ No newline at end of file
++obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-aiu-i2s-dma.o
++obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-i2s-dai.o
+\ No newline at end of file
+diff --git a/sound/soc/meson/i2s-dai.c b/sound/soc/meson/i2s-dai.c
+new file mode 100644
+index 000000000000..1008af8d3972
+--- /dev/null
++++ b/sound/soc/meson/i2s-dai.c
+@@ -0,0 +1,465 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++
++#include "aiu-regs.h"
++#include "audio-core.h"
++
++#define DRV_NAME "meson-i2s-dai"
++
++struct meson_i2s_dai {
++	struct meson_audio_core_data *core;
++	struct clk *mclk;
++	struct clk *bclks;
++	struct clk *iface;
++	struct clk *fast;
++	bool bclks_idle;
++};
++
++#define AIU_CLK_CTRL_I2S_DIV_EN			BIT(0)
++#define AIU_CLK_CTRL_I2S_DIV_MASK		GENMASK(3, 2)
++#define AIU_CLK_CTRL_AOCLK_POLARITY_MASK	BIT(6)
++#define AIU_CLK_CTRL_AOCLK_POLARITY_NORMAL	(0 << 6)
++#define AIU_CLK_CTRL_AOCLK_POLARITY_INVERTED	(1 << 6)
++#define AIU_CLK_CTRL_ALRCLK_POLARITY_MASK	BIT(7)
++#define AIU_CLK_CTRL_ALRCLK_POLARITY_NORMAL	(0 << 7)
++#define AIU_CLK_CTRL_ALRCLK_POLARITY_INVERTED	(1 << 7)
++#define AIU_CLK_CTRL_ALRCLK_SKEW_MASK		GENMASK(9, 8)
++#define AIU_CLK_CTRL_ALRCLK_LEFT_J		(0 << 8)
++#define AIU_CLK_CTRL_ALRCLK_I2S			(1 << 8)
++#define AIU_CLK_CTRL_ALRCLK_RIGHT_J		(2 << 8)
++#define AIU_CLK_CTRL_MORE_I2S_DIV_MASK		GENMASK(5, 0)
++#define AIU_CLK_CTRL_MORE_I2S_DIV(div)		(((div) - 1) << 0)
++#define AIU_CODEC_DAC_LRCLK_CTRL_DIV_MASK	GENMASK(11, 0)
++#define AIU_CODEC_DAC_LRCLK_CTRL_DIV(div)	(((div) - 1) << 0)
++#define AIU_I2S_DAC_CFG_PAYLOAD_SIZE_MASK	GENMASK(1, 0)
++#define AIU_I2S_DAC_CFG_AOCLK_32		(0 << 0)
++#define AIU_I2S_DAC_CFG_AOCLK_48		(2 << 0)
++#define AIU_I2S_DAC_CFG_AOCLK_64		(3 << 0)
++#define AIU_I2S_MISC_HOLD_EN			BIT(2)
++#define AIU_I2S_SOURCE_DESC_MODE_8CH		BIT(0)
++#define AIU_I2S_SOURCE_DESC_MODE_24BIT		BIT(5)
++#define AIU_I2S_SOURCE_DESC_MODE_32BIT		BIT(9)
++#define AIU_I2S_SOURCE_DESC_MODE_SPLIT		BIT(11)
++
++static void __hold(struct meson_i2s_dai *priv, bool enable)
++{
++	regmap_update_bits(priv->core->aiu, AIU_I2S_MISC,
++			   AIU_I2S_MISC_HOLD_EN,
++			   enable ? AIU_I2S_MISC_HOLD_EN : 0);
++}
++
++static void __divider_enable(struct meson_i2s_dai *priv, bool enable)
++{
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
++			   AIU_CLK_CTRL_I2S_DIV_EN,
++			   enable ? AIU_CLK_CTRL_I2S_DIV_EN : 0);
++}
++
++static void __playback_start(struct meson_i2s_dai *priv)
++{
++	__divider_enable(priv, true);
++	__hold(priv, false);
++}
++
++static void __playback_stop(struct meson_i2s_dai *priv, bool clk_force)
++{
++	__hold(priv, true);
++	/* Disable the bit clks if necessary */
++	if (clk_force || !priv->bclks_idle)
++		__divider_enable(priv, false);
++}
++
++static int meson_i2s_dai_trigger(struct snd_pcm_substream *substream, int cmd,
++				 struct snd_soc_dai *dai)
++{
++	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
++	bool clk_force_stop = false;
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		__playback_start(priv);
++		return 0;
++
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++		clk_force_stop = true;
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		__playback_stop(priv, clk_force_stop);
++		return 0;
++
++	default:
++		return -EINVAL;
++	}
++}
++
++static int __bclks_set_rate(struct meson_i2s_dai *priv, unsigned int srate,
++			    unsigned int width)
++{
++	unsigned int fs;
++
++	/* Get the oversampling factor */
++	fs = DIV_ROUND_CLOSEST(clk_get_rate(priv->mclk), srate);
++
++	/*
++	 * This DAI is usually connected to the dw-hdmi which does not support
++	 * bclk being 32 * lrclk or 48 * lrclk
++	 * Restrict to blck = 64 * lrclk
++	 */
++	if (fs % 64)
++		return -EINVAL;
++
++	/* Set the divider between lrclk and bclk */
++	regmap_update_bits(priv->core->aiu, AIU_I2S_DAC_CFG,
++			   AIU_I2S_DAC_CFG_PAYLOAD_SIZE_MASK,
++			   AIU_I2S_DAC_CFG_AOCLK_64);
++
++	regmap_update_bits(priv->core->aiu, AIU_CODEC_DAC_LRCLK_CTRL,
++			   AIU_CODEC_DAC_LRCLK_CTRL_DIV_MASK,
++			   AIU_CODEC_DAC_LRCLK_CTRL_DIV(64));
++
++	/* Use CLK_MORE for the i2s divider */
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
++			   AIU_CLK_CTRL_I2S_DIV_MASK,
++			   0);
++
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL_MORE,
++			   AIU_CLK_CTRL_MORE_I2S_DIV_MASK,
++			   AIU_CLK_CTRL_MORE_I2S_DIV(fs / 64));
++
++	return 0;
++}
++
++static int __setup_desc(struct meson_i2s_dai *priv, unsigned int width,
++			unsigned int channels)
++{
++	u32 desc = 0;
++
++	switch (width) {
++	case 24:
++		/*
++		 * For some reason, 24 bits wide audio don't play well
++		 * if the 32 bits mode is not set
++		 */
++		desc |= (AIU_I2S_SOURCE_DESC_MODE_24BIT |
++			 AIU_I2S_SOURCE_DESC_MODE_32BIT);
++		break;
++	case 16:
++		break;
++
++	default:
++		return -EINVAL;
++	}
++
++	switch (channels) {
++	case 2: /* Nothing to do */
++		break;
++	case 8:
++		/* TODO: Still requires testing ... */
++		desc |= AIU_I2S_SOURCE_DESC_MODE_8CH;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->core->aiu, AIU_I2S_SOURCE_DESC,
++			   AIU_I2S_SOURCE_DESC_MODE_8CH |
++			   AIU_I2S_SOURCE_DESC_MODE_24BIT |
++			   AIU_I2S_SOURCE_DESC_MODE_32BIT,
++			   desc);
++
++	return 0;
++}
++
++static int meson_i2s_dai_hw_params(struct snd_pcm_substream *substream,
++				   struct snd_pcm_hw_params *params,
++				   struct snd_soc_dai *dai)
++{
++	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
++	unsigned int width = params_width(params);
++	unsigned int channels = params_channels(params);
++	unsigned int rate = params_rate(params);
++	int ret;
++
++	ret = __setup_desc(priv, width, channels);
++	if (ret) {
++		dev_err(dai->dev, "Unable set to set i2s description\n");
++		return ret;
++	}
++
++	ret = __bclks_set_rate(priv, rate, width);
++	if (ret) {
++		dev_err(dai->dev, "Unable set to the i2s clock rates\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int meson_i2s_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
++	u32 val;
++
++	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
++		return -EINVAL;
++
++	/* DAI output mode */
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		val = AIU_CLK_CTRL_ALRCLK_I2S;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		val = AIU_CLK_CTRL_ALRCLK_LEFT_J;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		val = AIU_CLK_CTRL_ALRCLK_RIGHT_J;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
++			   AIU_CLK_CTRL_ALRCLK_SKEW_MASK,
++			   val);
++
++	/* DAI clock polarity */
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_IB_IF:
++		/* Invert both clocks */
++		val = AIU_CLK_CTRL_ALRCLK_POLARITY_INVERTED |
++			AIU_CLK_CTRL_AOCLK_POLARITY_INVERTED;
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		/* Invert bit clock */
++		val = AIU_CLK_CTRL_ALRCLK_POLARITY_NORMAL |
++			AIU_CLK_CTRL_AOCLK_POLARITY_INVERTED;
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		/* Invert frame clock */
++		val = AIU_CLK_CTRL_ALRCLK_POLARITY_INVERTED |
++			AIU_CLK_CTRL_AOCLK_POLARITY_NORMAL;
++		break;
++	case SND_SOC_DAIFMT_NB_NF:
++		/* Normal clocks */
++		val = AIU_CLK_CTRL_ALRCLK_POLARITY_NORMAL |
++			AIU_CLK_CTRL_AOCLK_POLARITY_NORMAL;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
++			   AIU_CLK_CTRL_ALRCLK_POLARITY_MASK |
++			   AIU_CLK_CTRL_AOCLK_POLARITY_MASK,
++			   val);
++
++	switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
++	case SND_SOC_DAIFMT_CONT:
++		priv->bclks_idle = true;
++		break;
++	case SND_SOC_DAIFMT_GATED:
++		priv->bclks_idle = false;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int meson_i2s_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++				    unsigned int freq, int dir)
++{
++	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
++	int ret;
++
++	if (WARN_ON(clk_id != 0))
++		return -EINVAL;
++
++	if (dir == SND_SOC_CLOCK_IN)
++		return 0;
++
++	ret = clk_set_rate(priv->mclk, freq);
++	if (ret) {
++		dev_err(dai->dev, "Failed to set sysclk to %uHz", freq);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int meson_i2s_dai_startup(struct snd_pcm_substream *substream,
++				 struct snd_soc_dai *dai)
++{
++	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
++	int ret;
++
++	/* Power up the i2s fast domain - can't write the registers w/o it */
++	ret = clk_prepare_enable(priv->fast);
++	if (ret)
++		goto out_clk_fast;
++
++	/* Make sure nothing gets out of the DAI yet */
++	__hold(priv, true);
++
++	/* I2S encoder needs the mixer interface gate */
++	ret = clk_prepare_enable(priv->iface);
++	if (ret)
++		goto out_clk_iface;
++
++	/* Enable the i2s master clock */
++	ret = clk_prepare_enable(priv->mclk);
++	if (ret)
++		goto out_mclk;
++
++	/* Enable the bit clock gate */
++	ret = clk_prepare_enable(priv->bclks);
++	if (ret)
++		goto out_bclks;
++
++	/* Make sure the interface expect a memory layout we can work with */
++	regmap_update_bits(priv->core->aiu, AIU_I2S_SOURCE_DESC,
++			   AIU_I2S_SOURCE_DESC_MODE_SPLIT,
++			   AIU_I2S_SOURCE_DESC_MODE_SPLIT);
++
++	return 0;
++
++out_bclks:
++	clk_disable_unprepare(priv->mclk);
++out_mclk:
++	clk_disable_unprepare(priv->iface);
++out_clk_iface:
++	clk_disable_unprepare(priv->fast);
++out_clk_fast:
++	return ret;
++}
++
++static void meson_i2s_dai_shutdown(struct snd_pcm_substream *substream,
++				   struct snd_soc_dai *dai)
++{
++	struct meson_i2s_dai *priv = snd_soc_dai_get_drvdata(dai);
++
++	clk_disable_unprepare(priv->bclks);
++	clk_disable_unprepare(priv->mclk);
++	clk_disable_unprepare(priv->iface);
++	clk_disable_unprepare(priv->fast);
++}
++
++static const struct snd_soc_dai_ops meson_i2s_dai_ops = {
++	.startup    = meson_i2s_dai_startup,
++	.shutdown   = meson_i2s_dai_shutdown,
++	.trigger    = meson_i2s_dai_trigger,
++	.hw_params  = meson_i2s_dai_hw_params,
++	.set_fmt    = meson_i2s_dai_set_fmt,
++	.set_sysclk = meson_i2s_dai_set_sysclk,
++};
++
++static struct snd_soc_dai_driver meson_i2s_dai = {
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 2,
++		.channels_max = 8,
++		.rates = SNDRV_PCM_RATE_8000_192000,
++		.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++			    SNDRV_PCM_FMTBIT_S24_LE)
++	},
++	.ops = &meson_i2s_dai_ops,
++};
++
++static const struct snd_soc_component_driver meson_i2s_dai_component = {
++	.name	= DRV_NAME,
++};
++
++static int meson_i2s_dai_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct meson_i2s_dai *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, priv);
++	priv->core = dev_get_drvdata(dev->parent);
++
++	priv->fast = devm_clk_get(dev, "fast");
++	if (IS_ERR(priv->fast)) {
++		if (PTR_ERR(priv->fast) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get the i2s fast domain clock\n");
++		return PTR_ERR(priv->fast);
++	}
++
++	priv->iface = devm_clk_get(dev, "iface");
++	if (IS_ERR(priv->iface)) {
++		if (PTR_ERR(priv->iface) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get i2s dai clock gate\n");
++		return PTR_ERR(priv->iface);
++	}
++
++	priv->bclks = devm_clk_get(dev, "bclks");
++	if (IS_ERR(priv->bclks)) {
++		if (PTR_ERR(priv->bclks) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get bit clocks gate\n");
++		return PTR_ERR(priv->bclks);
++	}
++
++	priv->mclk = devm_clk_get(dev, "mclk");
++	if (IS_ERR(priv->mclk)) {
++		if (PTR_ERR(priv->mclk) != -EPROBE_DEFER)
++			dev_err(dev, "failed to get the i2s master clock\n");
++		return PTR_ERR(priv->mclk);
++	}
++
++	return devm_snd_soc_register_component(dev, &meson_i2s_dai_component,
++					       &meson_i2s_dai, 1);
++}
++
++static const struct of_device_id meson_i2s_dai_of_match[] = {
++	{ .compatible = "amlogic,meson-i2s-dai", },
++	{ .compatible = "amlogic,meson-gxbb-i2s-dai", },
++	{ .compatible = "amlogic,meson-gxl-i2s-dai", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, meson_i2s_dai_of_match);
++
++static struct platform_driver meson_i2s_dai_pdrv = {
++	.probe = meson_i2s_dai_probe,
++	.driver = {
++		.name = DRV_NAME,
++		.of_match_table = meson_i2s_dai_of_match,
++	},
++};
++module_platform_driver(meson_i2s_dai_pdrv);
++
++MODULE_DESCRIPTION("Meson i2s DAI ASoC Driver");
++MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0006-ASoC-meson-add-aiu-spdif-dma-support.patch

@@ -0,0 +1,445 @@
+From 99e6d5ba97d0615428f88850ee8366a9dc24168e Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 30 Mar 2017 13:43:52 +0200
+Subject: [PATCH 06/53] ASoC: meson: add aiu spdif dma support
+
+Add support for the spdif output dma which is part of the AIU block
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ sound/soc/meson/Kconfig         |   7 +
+ sound/soc/meson/Makefile        |   4 +-
+ sound/soc/meson/aiu-spdif-dma.c | 388 ++++++++++++++++++++++++++++++++
+ 3 files changed, 398 insertions(+), 1 deletion(-)
+ create mode 100644 sound/soc/meson/aiu-spdif-dma.c
+
+diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
+index 5904e9e50569..712303ff8970 100644
+--- a/sound/soc/meson/Kconfig
++++ b/sound/soc/meson/Kconfig
+@@ -80,3 +80,10 @@ config SND_SOC_MESON_I2S
+ 	help
+ 	  Say Y or M if you want to add support for i2s driver for Amlogic
+ 	  Meson SoCs.
++
++config SND_SOC_MESON_SPDIF
++	tristate "Meson spdif interface"
++	depends on SND_SOC_MESON
++	help
++	  Say Y or M if you want to add support for spdif dma driver for Amlogic
++	  Meson SoCs.
+diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
+index b8641f9f7fc1..dc5164a7e164 100644
+--- a/sound/soc/meson/Makefile
++++ b/sound/soc/meson/Makefile
+@@ -22,8 +22,10 @@ obj-$(CONFIG_SND_MESON_AXG_SPDIFOUT) += snd-soc-meson-axg-spdifout.o
+ 
+ snd-soc-meson-audio-core-objs	 := audio-core.o
+ snd-soc-meson-aiu-i2s-dma-objs	 := aiu-i2s-dma.o
++snd-soc-meson-aiu-spdif-dma-objs := aiu-spdif-dma.o
+ snd-soc-meson-i2s-dai-objs	 := i2s-dai.o
+ 
+ obj-$(CONFIG_SND_SOC_MESON) += snd-soc-meson-audio-core.o
+ obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-aiu-i2s-dma.o
+-obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-i2s-dai.o
+\ No newline at end of file
++obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-i2s-dai.o
++obj-$(CONFIG_SND_SOC_MESON_SPDIF) += snd-soc-meson-aiu-spdif-dma.o
+\ No newline at end of file
+diff --git a/sound/soc/meson/aiu-spdif-dma.c b/sound/soc/meson/aiu-spdif-dma.c
+new file mode 100644
+index 000000000000..81c3b856fbf9
+--- /dev/null
++++ b/sound/soc/meson/aiu-spdif-dma.c
+@@ -0,0 +1,388 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#include "aiu-regs.h"
++#include "audio-core.h"
++
++#define DRV_NAME "meson-aiu-spdif-dma"
++
++struct aiu_spdif_dma {
++	struct meson_audio_core_data *core;
++	struct clk *fast;
++	int irq;
++};
++
++#define AIU_958_DCU_FF_CTRL_EN			BIT(0)
++#define AIU_958_DCU_FF_CTRL_AUTO_DISABLE	BIT(1)
++#define AIU_958_DCU_FF_CTRL_IRQ_MODE_MASK	GENMASK(3, 2)
++#define AIU_958_DCU_FF_CTRL_IRQ_OUT_THD		BIT(2)
++#define AIU_958_DCU_FF_CTRL_IRQ_FRAME_READ 	BIT(3)
++#define AIU_958_DCU_FF_CTRL_SYNC_HEAD_EN	BIT(4)
++#define AIU_958_DCU_FF_CTRL_BYTE_SEEK		BIT(5)
++#define AIU_958_DCU_FF_CTRL_CONTINUE		BIT(6)
++#define AIU_MEM_IEC958_BUF_CNTL_INIT		BIT(0)
++#define AIU_MEM_IEC958_CONTROL_INIT		BIT(0)
++#define AIU_MEM_IEC958_CONTROL_FILL_EN		BIT(1)
++#define AIU_MEM_IEC958_CONTROL_EMPTY_EN		BIT(2)
++#define AIU_MEM_IEC958_CONTROL_ENDIAN_MASK	GENMASK(5, 3)
++#define AIU_MEM_IEC958_CONTROL_RD_DDR		BIT(6)
++#define AIU_MEM_IEC958_CONTROL_MODE_16BIT	BIT(7)
++#define AIU_MEM_IEC958_MASKS_CH_MEM_MASK	GENMASK(15, 8)
++#define AIU_MEM_IEC958_MASKS_CH_MEM(ch)		((ch) << 8)
++#define AIU_MEM_IEC958_MASKS_CH_RD_MASK		GENMASK(7, 0)
++#define AIU_MEM_IEC958_MASKS_CH_RD(ch)		((ch) << 0)
++
++#define AIU_SPDIF_DMA_BURST 8
++#define AIU_SPDIF_BPF_MAX USHRT_MAX
++
++static struct snd_pcm_hardware aiu_spdif_dma_hw = {
++	.info = (SNDRV_PCM_INFO_INTERLEAVED |
++		 SNDRV_PCM_INFO_MMAP |
++		 SNDRV_PCM_INFO_MMAP_VALID |
++		 SNDRV_PCM_INFO_PAUSE),
++
++	.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++		    SNDRV_PCM_FMTBIT_S24_LE |
++		    SNDRV_PCM_FMTBIT_S32_LE),
++
++	.rates = (SNDRV_PCM_RATE_32000 |
++		  SNDRV_PCM_RATE_44100 |
++		  SNDRV_PCM_RATE_48000 |
++		  SNDRV_PCM_RATE_96000 |
++		  SNDRV_PCM_RATE_192000),
++	/*
++	 * TODO: The DMA can change the endianness, the msb position
++	 * and deal with unsigned - support this later on
++	 */
++
++	.channels_min = 2,
++	.channels_max = 2,
++	.period_bytes_min = AIU_SPDIF_DMA_BURST,
++	.period_bytes_max = AIU_SPDIF_BPF_MAX,
++	.periods_min = 2,
++	.periods_max = UINT_MAX,
++	.buffer_bytes_max = 1 * 1024 * 1024,
++	.fifo_size = 0,
++};
++
++static struct aiu_spdif_dma *aiu_spdif_dma_priv(struct snd_pcm_substream *s)
++{
++	struct snd_soc_pcm_runtime *rtd = s->private_data;
++	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
++
++	return snd_soc_component_get_drvdata(component);
++}
++
++static snd_pcm_uframes_t
++aiu_spdif_dma_pointer(struct snd_pcm_substream *substream)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct aiu_spdif_dma *priv = aiu_spdif_dma_priv(substream);
++	unsigned int addr;
++	int ret;
++
++	ret = regmap_read(priv->core->aiu, AIU_MEM_IEC958_RD_PTR,
++			  &addr);
++	if (ret)
++		return 0;
++
++	return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);
++}
++
++static void __dma_enable(struct aiu_spdif_dma *priv, bool enable)
++{
++	unsigned int en_mask = (AIU_MEM_IEC958_CONTROL_FILL_EN |
++				AIU_MEM_IEC958_CONTROL_EMPTY_EN);
++
++	regmap_update_bits(priv->core->aiu, AIU_MEM_IEC958_CONTROL, en_mask,
++			   enable ? en_mask : 0);
++}
++
++static void __dcu_fifo_enable(struct aiu_spdif_dma *priv, bool enable)
++{
++	regmap_update_bits(priv->core->aiu, AIU_958_DCU_FF_CTRL,
++			   AIU_958_DCU_FF_CTRL_EN,
++			   enable ? AIU_958_DCU_FF_CTRL_EN : 0);
++}
++
++static int aiu_spdif_dma_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++	struct aiu_spdif_dma *priv = aiu_spdif_dma_priv(substream);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		__dcu_fifo_enable(priv, true);
++		__dma_enable(priv, true);
++		break;
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++	case SNDRV_PCM_TRIGGER_STOP:
++		__dma_enable(priv, false);
++		__dcu_fifo_enable(priv, false);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static void __dma_init_mem(struct aiu_spdif_dma *priv)
++{
++	regmap_update_bits(priv->core->aiu, AIU_MEM_IEC958_CONTROL,
++			   AIU_MEM_IEC958_CONTROL_INIT,
++			   AIU_MEM_IEC958_CONTROL_INIT);
++	regmap_update_bits(priv->core->aiu, AIU_MEM_IEC958_BUF_CNTL,
++			   AIU_MEM_IEC958_BUF_CNTL_INIT,
++			   AIU_MEM_IEC958_BUF_CNTL_INIT);
++
++	regmap_update_bits(priv->core->aiu, AIU_MEM_IEC958_CONTROL,
++			   AIU_MEM_IEC958_CONTROL_INIT,
++			   0);
++	regmap_update_bits(priv->core->aiu, AIU_MEM_IEC958_BUF_CNTL,
++			   AIU_MEM_IEC958_BUF_CNTL_INIT,
++			   0);
++}
++
++static int aiu_spdif_dma_prepare(struct snd_pcm_substream *substream)
++{
++	struct aiu_spdif_dma *priv = aiu_spdif_dma_priv(substream);
++
++	__dma_init_mem(priv);
++
++	return 0;
++}
++
++static int __setup_memory_layout(struct aiu_spdif_dma *priv,
++				 unsigned int width)
++{
++	u32 mem_ctl = AIU_MEM_IEC958_CONTROL_RD_DDR;
++
++	if (width == 16)
++		mem_ctl |= AIU_MEM_IEC958_CONTROL_MODE_16BIT;
++
++	regmap_update_bits(priv->core->aiu, AIU_MEM_IEC958_CONTROL,
++			   AIU_MEM_IEC958_CONTROL_ENDIAN_MASK |
++			   AIU_MEM_IEC958_CONTROL_MODE_16BIT |
++			   AIU_MEM_IEC958_CONTROL_RD_DDR,
++			   mem_ctl);
++
++	return 0;
++}
++
++static int aiu_spdif_dma_hw_params(struct snd_pcm_substream *substream,
++				   struct snd_pcm_hw_params *params)
++{
++	struct snd_pcm_runtime *runtime = substream->runtime;
++	struct aiu_spdif_dma *priv = aiu_spdif_dma_priv(substream);
++	int ret;
++	dma_addr_t end_ptr;
++
++	ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
++	if (ret < 0)
++		return ret;
++
++	ret = __setup_memory_layout(priv, params_physical_width(params));
++	if (ret)
++		return ret;
++
++	/* Initialize memory pointers */
++	regmap_write(priv->core->aiu,
++		     AIU_MEM_IEC958_START_PTR, runtime->dma_addr);
++	regmap_write(priv->core->aiu,
++		     AIU_MEM_IEC958_RD_PTR, runtime->dma_addr);
++
++	/* The end pointer is the address of the last valid block */
++	end_ptr = runtime->dma_addr + runtime->dma_bytes - AIU_SPDIF_DMA_BURST;
++	regmap_write(priv->core->aiu, AIU_MEM_IEC958_END_PTR, end_ptr);
++
++	/* Memory masks */
++	regmap_write(priv->core->aiu, AIU_MEM_IEC958_MASKS,
++		     AIU_MEM_IEC958_MASKS_CH_RD(0xff) |
++		     AIU_MEM_IEC958_MASKS_CH_MEM(0xff));
++
++	/* Setup the number bytes read by the FIFO between each IRQ */
++	regmap_write(priv->core->aiu, AIU_958_BPF, params_period_bytes(params));
++
++	/*
++	 * AUTO_DISABLE and SYNC_HEAD are enabled by default but
++	 * this should be disabled in PCM (uncompressed) mode
++	 */
++	regmap_update_bits(priv->core->aiu, AIU_958_DCU_FF_CTRL,
++			   AIU_958_DCU_FF_CTRL_AUTO_DISABLE |
++			   AIU_958_DCU_FF_CTRL_IRQ_MODE_MASK |
++			   AIU_958_DCU_FF_CTRL_SYNC_HEAD_EN,
++			   AIU_958_DCU_FF_CTRL_IRQ_FRAME_READ);
++
++	return 0;
++}
++
++static int aiu_spdif_dma_hw_free(struct snd_pcm_substream *substream)
++{
++	return snd_pcm_lib_free_pages(substream);
++}
++
++static irqreturn_t aiu_spdif_dma_irq(int irq, void *dev_id)
++{
++	struct snd_pcm_substream *playback = dev_id;
++
++	snd_pcm_period_elapsed(playback);
++
++	return IRQ_HANDLED;
++}
++
++static int aiu_spdif_dma_open(struct snd_pcm_substream *substream)
++{
++	struct aiu_spdif_dma *priv = aiu_spdif_dma_priv(substream);
++	int ret;
++
++	snd_soc_set_runtime_hwparams(substream, &aiu_spdif_dma_hw);
++
++	/*
++	 * Make sure the buffer and period size are multiple of the DMA burst
++	 * size
++	 */
++	ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
++					 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
++					 AIU_SPDIF_DMA_BURST);
++	if (ret)
++		return ret;
++
++	ret = snd_pcm_hw_constraint_step(substream->runtime, 0,
++					 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
++					 AIU_SPDIF_DMA_BURST);
++	if (ret)
++		return ret;
++
++	/* Request the SPDIF DDR irq */
++	ret = request_irq(priv->irq, aiu_spdif_dma_irq, 0,
++			  DRV_NAME, substream);
++	if (ret)
++		return ret;
++
++	/* Power up the spdif fast domain - can't write the register w/o it */
++	ret = clk_prepare_enable(priv->fast);
++	if (ret)
++		return ret;
++
++	/* Make sure the dma is initially halted */
++	__dma_enable(priv, false);
++	__dcu_fifo_enable(priv, false);
++
++	return 0;
++}
++
++static int aiu_spdif_dma_close(struct snd_pcm_substream *substream)
++{
++	struct aiu_spdif_dma *priv = aiu_spdif_dma_priv(substream);
++
++	clk_disable_unprepare(priv->fast);
++	free_irq(priv->irq, substream);
++
++	return 0;
++}
++
++static const struct snd_pcm_ops aiu_spdif_dma_ops = {
++	.open =		aiu_spdif_dma_open,
++	.close =        aiu_spdif_dma_close,
++	.ioctl =	snd_pcm_lib_ioctl,
++	.hw_params =	aiu_spdif_dma_hw_params,
++	.hw_free =      aiu_spdif_dma_hw_free,
++	.prepare =      aiu_spdif_dma_prepare,
++	.pointer =	aiu_spdif_dma_pointer,
++	.trigger =	aiu_spdif_dma_trigger,
++};
++
++static int aiu_spdif_dma_new(struct snd_soc_pcm_runtime *rtd)
++{
++	struct snd_card *card = rtd->card->snd_card;
++	size_t size = aiu_spdif_dma_hw.buffer_bytes_max;
++
++	return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
++						     SNDRV_DMA_TYPE_DEV,
++						     card->dev, size, size);
++}
++
++static const struct snd_soc_component_driver aiu_spdif_platform = {
++	.ops		= &aiu_spdif_dma_ops,
++	.pcm_new	= aiu_spdif_dma_new,
++	.name 		= DRV_NAME,
++};
++
++static int aiu_spdif_dma_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct aiu_spdif_dma *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, priv);
++	priv->core = dev_get_drvdata(dev->parent);
++
++	priv->fast = devm_clk_get(dev, "fast");
++	if (IS_ERR(priv->fast)) {
++		if (PTR_ERR(priv->fast) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get spdif fast domain clock\n");
++		return PTR_ERR(priv->fast);
++	}
++
++	priv->irq = platform_get_irq(pdev, 0);
++	if (priv->irq <= 0) {
++		dev_err(dev, "Can't get spdif ddr irq\n");
++		return priv->irq;
++	}
++
++	return devm_snd_soc_register_component(dev, &aiu_spdif_platform,
++					       NULL, 0);
++}
++
++static const struct of_device_id aiu_spdif_dma_of_match[] = {
++	{ .compatible = "amlogic,meson-aiu-spdif-dma", },
++	{ .compatible = "amlogic,meson-gxbb-aiu-spdif-dma", },
++	{ .compatible = "amlogic,meson-gxl-aiu-spdif-dma", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, aiu_spdif_dma_of_match);
++
++static struct platform_driver aiu_spdif_dma_pdrv = {
++	.probe = aiu_spdif_dma_probe,
++	.driver = {
++		.name = DRV_NAME,
++		.of_match_table = aiu_spdif_dma_of_match,
++	},
++};
++module_platform_driver(aiu_spdif_dma_pdrv);
++
++MODULE_DESCRIPTION("Meson AIU spdif DMA ASoC Driver");
++MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
++MODULE_LICENSE("GPL");
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0007-ASoC-meson-add-initial-spdif-dai-support.patch

@@ -0,0 +1,432 @@
+From ecabfe253aab181bdc241cc7e16e857a3574e528 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 30 Mar 2017 13:46:03 +0200
+Subject: [PATCH 07/53] ASoC: meson: add initial spdif dai support
+
+Add support for the spdif dai found on Amlogic Meson SoC family.
+With this initial implementation, only uncompressed pcm playback
+from the spdif dma is supported. Future work will add compressed
+support, pcm playback from i2s dma and capture.
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ sound/soc/meson/Kconfig     |   3 +-
+ sound/soc/meson/Makefile    |   4 +-
+ sound/soc/meson/spdif-dai.c | 374 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 379 insertions(+), 2 deletions(-)
+ create mode 100644 sound/soc/meson/spdif-dai.c
+
+diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
+index 712303ff8970..bc3d6f22ed88 100644
+--- a/sound/soc/meson/Kconfig
++++ b/sound/soc/meson/Kconfig
+@@ -84,6 +84,7 @@ config SND_SOC_MESON_I2S
+ config SND_SOC_MESON_SPDIF
+ 	tristate "Meson spdif interface"
+ 	depends on SND_SOC_MESON
++	select SND_PCM_IEC958
+ 	help
+-	  Say Y or M if you want to add support for spdif dma driver for Amlogic
++	  Say Y or M if you want to add support for spdif driver for Amlogic
+ 	  Meson SoCs.
+diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
+index dc5164a7e164..44f79d8b91b7 100644
+--- a/sound/soc/meson/Makefile
++++ b/sound/soc/meson/Makefile
+@@ -24,8 +24,10 @@ snd-soc-meson-audio-core-objs	 := audio-core.o
+ snd-soc-meson-aiu-i2s-dma-objs	 := aiu-i2s-dma.o
+ snd-soc-meson-aiu-spdif-dma-objs := aiu-spdif-dma.o
+ snd-soc-meson-i2s-dai-objs	 := i2s-dai.o
++snd-soc-meson-spdif-dai-objs	 := spdif-dai.o
+ 
+ obj-$(CONFIG_SND_SOC_MESON) += snd-soc-meson-audio-core.o
+ obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-aiu-i2s-dma.o
+ obj-$(CONFIG_SND_SOC_MESON_I2S)	+= snd-soc-meson-i2s-dai.o
+-obj-$(CONFIG_SND_SOC_MESON_SPDIF) += snd-soc-meson-aiu-spdif-dma.o
+\ No newline at end of file
++obj-$(CONFIG_SND_SOC_MESON_SPDIF) += snd-soc-meson-aiu-spdif-dma.o
++obj-$(CONFIG_SND_SOC_MESON_SPDIF) += snd-soc-meson-spdif-dai.o
+\ No newline at end of file
+diff --git a/sound/soc/meson/spdif-dai.c b/sound/soc/meson/spdif-dai.c
+new file mode 100644
+index 000000000000..e7630007c84b
+--- /dev/null
++++ b/sound/soc/meson/spdif-dai.c
+@@ -0,0 +1,374 @@
++/*
++ * Copyright (C) 2017 BayLibre, SAS
++ * Author: Jerome Brunet <jbrunet@baylibre.com>
++ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++#include <sound/pcm_iec958.h>
++
++#include "aiu-regs.h"
++#include "audio-core.h"
++
++#define DRV_NAME "meson-spdif-dai"
++
++struct meson_spdif_dai {
++	struct meson_audio_core_data *core;
++	struct clk *iface;
++	struct clk *fast;
++	struct clk *mclk_i958;
++	struct clk *mclk;
++};
++
++#define AIU_CLK_CTRL_958_DIV_EN			BIT(1)
++#define AIU_CLK_CTRL_958_DIV_MASK		GENMASK(5, 4)
++#define AIU_CLK_CTRL_958_DIV_MORE		BIT(12)
++#define AIU_MEM_IEC958_CONTROL_MODE_LINEAR	BIT(8)
++#define AIU_958_CTRL_HOLD_EN			BIT(0)
++#define AIU_958_MISC_NON_PCM			BIT(0)
++#define AIU_958_MISC_MODE_16BITS		BIT(1)
++#define AIU_958_MISC_16BITS_ALIGN_MASK		GENMASK(6, 5)
++#define AIU_958_MISC_16BITS_ALIGN(val)		((val) << 5)
++#define AIU_958_MISC_MODE_32BITS		BIT(7)
++#define AIU_958_MISC_32BITS_SHIFT_MASK		GENMASK(10, 8)
++#define AIU_958_MISC_32BITS_SHIFT(val)		((val) << 8)
++#define AIU_958_MISC_U_FROM_STREAM		BIT(12)
++#define AIU_958_MISC_FORCE_LR			BIT(13)
++
++#define AIU_CS_WORD_LEN 4
++
++static void __hold(struct meson_spdif_dai *priv, bool enable)
++{
++	regmap_update_bits(priv->core->aiu, AIU_958_CTRL,
++			   AIU_958_CTRL_HOLD_EN,
++			   enable ? AIU_958_CTRL_HOLD_EN : 0);
++}
++
++static void __divider_enable(struct meson_spdif_dai *priv, bool enable)
++{
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
++			   AIU_CLK_CTRL_958_DIV_EN,
++			   enable ? AIU_CLK_CTRL_958_DIV_EN : 0);
++}
++
++static void __playback_start(struct meson_spdif_dai *priv)
++{
++	__divider_enable(priv, true);
++	__hold(priv, false);
++}
++
++static void __playback_stop(struct meson_spdif_dai *priv)
++{
++	__hold(priv, true);
++	__divider_enable(priv, false);
++}
++
++static int meson_spdif_dai_trigger(struct snd_pcm_substream *substream, int cmd,
++				   struct snd_soc_dai *dai)
++{
++	struct meson_spdif_dai *priv = snd_soc_dai_get_drvdata(dai);
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++	case SNDRV_PCM_TRIGGER_RESUME:
++	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++		__playback_start(priv);
++		return 0;
++
++	case SNDRV_PCM_TRIGGER_STOP:
++	case SNDRV_PCM_TRIGGER_SUSPEND:
++	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++		__playback_stop(priv);
++		return 0;
++
++	default:
++		return -EINVAL;
++	}
++}
++
++static int __setup_spdif_clk(struct meson_spdif_dai *priv, unsigned int rate)
++{
++	unsigned int mrate;
++
++	/* Leave the internal divisor alone */
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL,
++			   AIU_CLK_CTRL_958_DIV_MASK |
++			   AIU_CLK_CTRL_958_DIV_MORE,
++			   0);
++
++	/* 2 * 32bits per subframe * 2 channels = 128 */
++	mrate = rate * 128;
++	return clk_set_rate(priv->mclk, mrate);
++}
++
++static int __setup_cs_word(struct meson_spdif_dai *priv,
++			   struct snd_pcm_hw_params *params)
++{
++	u8 cs[AIU_CS_WORD_LEN];
++	u32 val;
++	int ret;
++
++	ret = snd_pcm_create_iec958_consumer_hw_params(params, cs,
++						       AIU_CS_WORD_LEN);
++	if (ret < 0)
++		return -EINVAL;
++
++	/* Write the 1st half word */
++	val = cs[1] | cs[0] << 8;
++	regmap_write(priv->core->aiu, AIU_958_CHSTAT_L0, val);
++	regmap_write(priv->core->aiu, AIU_958_CHSTAT_R0, val);
++
++	/* Write the 2nd half word */
++	val = cs[3] | cs[2] << 8;
++	regmap_write(priv->core->aiu, AIU_958_CHSTAT_L1, val);
++	regmap_write(priv->core->aiu, AIU_958_CHSTAT_R1, val);
++
++	return 0;
++}
++
++static int __setup_pcm_fmt(struct meson_spdif_dai *priv,
++			   unsigned int width)
++{
++	u32 val = 0;
++
++	switch (width) {
++	case 16:
++		val |= AIU_958_MISC_MODE_16BITS;
++		val |= AIU_958_MISC_16BITS_ALIGN(2);
++		break;
++	case 32:
++	case 24:
++		/*
++		 * Looks like this should only be set for 32bits mode, but the
++		 * vendor kernel sets it like this for 24bits as well, let's
++		 * try and see
++		 */
++		val |= AIU_958_MISC_MODE_32BITS;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	/* No idea what this actually does, copying the vendor kernel for now */
++	val |= AIU_958_MISC_FORCE_LR;
++	val |= AIU_958_MISC_U_FROM_STREAM;
++
++	regmap_update_bits(priv->core->aiu, AIU_958_MISC,
++			   AIU_958_MISC_NON_PCM |
++			   AIU_958_MISC_MODE_16BITS |
++			   AIU_958_MISC_16BITS_ALIGN_MASK |
++			   AIU_958_MISC_MODE_32BITS |
++			   AIU_958_MISC_FORCE_LR,
++			   val);
++
++	return 0;
++}
++
++static int meson_spdif_dai_hw_params(struct snd_pcm_substream *substream,
++				     struct snd_pcm_hw_params *params,
++				     struct snd_soc_dai *dai)
++{
++	struct meson_spdif_dai *priv = snd_soc_dai_get_drvdata(dai);
++	int ret;
++
++	ret = __setup_spdif_clk(priv, params_rate(params));
++	if (ret) {
++		dev_err(dai->dev, "Unable to set the spdif clock\n");
++		return ret;
++	}
++
++	ret = __setup_cs_word(priv, params);
++	if (ret) {
++		dev_err(dai->dev, "Unable to set the channel status word\n");
++		return ret;
++	}
++
++	ret = __setup_pcm_fmt(priv, params_width(params));
++	if (ret) {
++		dev_err(dai->dev, "Unable to set the pcm format\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int meson_spdif_dai_startup(struct snd_pcm_substream *substream,
++				   struct snd_soc_dai *dai)
++{
++	struct meson_spdif_dai *priv = snd_soc_dai_get_drvdata(dai);
++	int ret;
++
++	/* Power up the spdif fast domain - can't write the registers w/o it */
++	ret = clk_prepare_enable(priv->fast);
++	if (ret)
++		goto out_clk_fast;
++
++	/* Make sure nothing gets out of the DAI yet*/
++	__hold(priv, true);
++
++	ret = clk_set_parent(priv->mclk, priv->mclk_i958);
++	if (ret)
++		return ret;
++
++	/* Enable the clock gate */
++	ret = clk_prepare_enable(priv->iface);
++	if (ret)
++		goto out_clk_iface;
++
++	/* Enable the spdif clock */
++	ret = clk_prepare_enable(priv->mclk);
++	if (ret)
++		goto out_mclk;
++
++	/*
++	 * Make sure the interface expect a memory layout we can work with
++	 * MEM prefixed register usually belong to the DMA, but when the spdif
++	 * DAI takes data from the i2s buffer, we need to make sure it works in
++	 * split mode and not the  "normal mode" (channel samples packed in
++	 * 32 bytes groups)
++	 */
++	regmap_update_bits(priv->core->aiu, AIU_MEM_IEC958_CONTROL,
++			   AIU_MEM_IEC958_CONTROL_MODE_LINEAR,
++			   AIU_MEM_IEC958_CONTROL_MODE_LINEAR);
++
++	return 0;
++
++out_mclk:
++	clk_disable_unprepare(priv->iface);
++out_clk_iface:
++	clk_disable_unprepare(priv->fast);
++out_clk_fast:
++	return ret;
++}
++
++static void meson_spdif_dai_shutdown(struct snd_pcm_substream *substream,
++				   struct snd_soc_dai *dai)
++{
++	struct meson_spdif_dai *priv = snd_soc_dai_get_drvdata(dai);
++
++	clk_disable_unprepare(priv->iface);
++	clk_disable_unprepare(priv->mclk);
++	clk_disable_unprepare(priv->fast);
++}
++
++static const struct snd_soc_dai_ops meson_spdif_dai_ops = {
++	.startup    = meson_spdif_dai_startup,
++	.shutdown   = meson_spdif_dai_shutdown,
++	.trigger    = meson_spdif_dai_trigger,
++	.hw_params  = meson_spdif_dai_hw_params,
++};
++
++static struct snd_soc_dai_driver meson_spdif_dai = {
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rates = (SNDRV_PCM_RATE_32000 |
++			  SNDRV_PCM_RATE_44100 |
++			  SNDRV_PCM_RATE_48000 |
++			  SNDRV_PCM_RATE_96000 |
++			  SNDRV_PCM_RATE_192000),
++		.formats = (SNDRV_PCM_FMTBIT_S16_LE |
++			    SNDRV_PCM_FMTBIT_S24_LE)
++	},
++	.ops = &meson_spdif_dai_ops,
++};
++
++static const struct snd_soc_component_driver meson_spdif_dai_component = {
++	.name	= DRV_NAME,
++};
++
++static int meson_spdif_dai_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct meson_spdif_dai *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, priv);
++	priv->core = dev_get_drvdata(dev->parent);
++
++	priv->fast = devm_clk_get(dev, "fast");
++	if (IS_ERR(priv->fast)) {
++		if (PTR_ERR(priv->fast) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get spdif fast domain clockt\n");
++		return PTR_ERR(priv->fast);
++	}
++
++	priv->iface = devm_clk_get(dev, "iface");
++	if (IS_ERR(priv->iface)) {
++		if (PTR_ERR(priv->iface) != -EPROBE_DEFER)
++			dev_err(dev,
++				"Can't get the dai clock gate\n");
++		return PTR_ERR(priv->iface);
++	}
++
++	priv->mclk_i958 = devm_clk_get(dev, "mclk_i958");
++	if (IS_ERR(priv->mclk_i958)) {
++		if (PTR_ERR(priv->mclk_i958) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get the spdif master clock\n");
++		return PTR_ERR(priv->mclk_i958);
++	}
++
++	/*
++	 * TODO: the spdif dai can also get its data from the i2s fifo.
++	 * For this use-case, the DAI driver will need to get the i2s master
++	 * clock in order to reparent the spdif clock from cts_mclk_i958 to
++	 * cts_amclk
++	 */
++
++	priv->mclk = devm_clk_get(dev, "mclk");
++	if (IS_ERR(priv->mclk)) {
++		if (PTR_ERR(priv->mclk) != -EPROBE_DEFER)
++			dev_err(dev, "Can't get the spdif input mux clock\n");
++		return PTR_ERR(priv->mclk);
++	}
++
++	return devm_snd_soc_register_component(dev, &meson_spdif_dai_component,
++					       &meson_spdif_dai, 1);
++}
++
++static const struct of_device_id meson_spdif_dai_of_match[] = {
++	{ .compatible = "amlogic,meson-spdif-dai", },
++	{ .compatible = "amlogic,meson-gxbb-spdif-dai", },
++	{ .compatible = "amlogic,meson-gxl-spdif-dai", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, meson_spdif_dai_of_match);
++
++static struct platform_driver meson_spdif_dai_pdrv = {
++	.probe = meson_spdif_dai_probe,
++	.driver = {
++		.name = DRV_NAME,
++		.of_match_table = meson_spdif_dai_of_match,
++	},
++};
++module_platform_driver(meson_spdif_dai_pdrv);
++
++MODULE_DESCRIPTION("Meson spdif DAI ASoC Driver");
++MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0008-ARM64-defconfig-enable-audio-support-for-meson-SoCs-.patch

@@ -0,0 +1,31 @@
+From eabd19b9bb8a62764dfd5290205cf7431e0329d6 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Fri, 31 Mar 2017 15:55:03 +0200
+Subject: [PATCH 08/53] ARM64: defconfig: enable audio support for meson SoCs
+ as module
+
+Add audio support for meson SoCs. This includes the audio core
+driver and the i2s and spdif output interfaces
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ arch/arm64/configs/defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index ab1cb51319e7..a4bf54b3b50d 100644
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -464,6 +464,9 @@ CONFIG_SOUND=y
+ CONFIG_SND=y
+ CONFIG_SND_SOC=y
+ CONFIG_SND_BCM2835_SOC_I2S=m
++CONFIG_SND_SOC_MESON=m
++CONFIG_SND_SOC_MESON_I2S=m
++CONFIG_SND_SOC_MESON_SPDIF=m
+ CONFIG_SND_SOC_ROCKCHIP=m
+ CONFIG_SND_SOC_ROCKCHIP_I2S=m
+ CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0009-ARM64-dts-meson-gx-add-audio-controller-nodes.patch

@@ -0,0 +1,189 @@
+From 8615d90edac5487f8639c5e4df40312972d7b2c9 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Thu, 30 Mar 2017 15:19:04 +0200
+Subject: [PATCH 09/53] ARM64: dts: meson-gx: add audio controller nodes
+
+Add audio controller nodes for Amlogic meson gxbb and gxl.
+This includes the audio-core node, the i2s and spdif DAIs, i2s and spdif
+aiu DMAs.
+
+Audio on this SoC family is still a work in progress. More nodes are likely
+to be added later on (pcm DAIs, input DMAs, etc ...)
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gx.dtsi   | 35 ++++++++++++++++++
+ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 39 +++++++++++++++++++++
+ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi  | 38 ++++++++++++++++++++
+ 3 files changed, 112 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+index b8dc4dbb391b..6b64b63f2a68 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+@@ -203,6 +203,41 @@
+ 				#reset-cells = <1>;
+ 			};
+ 
++			audio: audio@5400 {
++				compatible = "amlogic,meson-audio-core";
++				reg = <0x0 0x5400 0x0 0x2ac>,
++				      <0x0 0xa000 0x0 0x304>;
++				reg-names = "aiu", "audin";
++				status = "disabled";
++
++				aiu_i2s_dma: aiu_i2s_dma {
++					#sound-dai-cells = <0>;
++					compatible = "amlogic,meson-aiu-i2s-dma";
++					interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
++					status = "disabled";
++				};
++
++				aiu_spdif_dma: aiu_spdif_dma {
++					#sound-dai-cells = <0>;
++					compatible = "amlogic,meson-aiu-spdif-dma";
++					interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
++					status = "disabled";
++				};
++
++				i2s_dai: i2s_dai {
++					#sound-dai-cells = <0>;
++					compatible = "amlogic,meson-i2s-dai";
++					status = "disabled";
++				};
++
++				spdif_dai: spdif_dai {
++					#sound-dai-cells = <0>;
++					compatible = "amlogic,meson-spdif-dai";
++					status = "disabled";
++				};
++
++			};
++
+ 			uart_A: serial@84c0 {
+ 				compatible = "amlogic,meson-gx-uart";
+ 				reg = <0x0 0x84c0 0x0 0x18>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+index 98cbba6809ca..79132496691f 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+@@ -659,6 +659,35 @@
+ 	};
+ };
+ 
++&audio {
++	clocks = <&clkc CLKID_AIU>,
++		 <&clkc CLKID_AIU_GLUE>,
++		 <&clkc CLKID_I2S_SPDIF>;
++	clock-names = "aiu_top", "aiu_glue", "audin";
++	resets = <&reset RESET_AIU>,
++		 <&reset RESET_AUDIN>;
++	reset-names = "aiu", "audin";
++};
++
++&aiu_i2s_dma {
++	clocks = <&clkc CLKID_I2S_OUT>;
++	clock-names = "fast";
++};
++
++&aiu_spdif_dma {
++	clocks = <&clkc CLKID_IEC958>;
++	clock-names = "fast";
++
++};
++
++&i2s_dai {
++	clocks = <&clkc CLKID_I2S_OUT>,
++		 <&clkc CLKID_MIXER_IFACE>,
++		 <&clkc CLKID_AOCLK_GATE>,
++		 <&clkc CLKID_CTS_AMCLK>;
++	clock-names = "fast", "iface", "bclks", "mclk";
++};
++
+ &pwrc_vpu {
+ 	resets = <&reset RESET_VIU>,
+ 		 <&reset RESET_VENC>,
+@@ -741,6 +770,15 @@
+ 	num-cs = <1>;
+ };
+ 
++&spdif_dai {
++	clocks = <&clkc CLKID_IEC958>,
++		 <&clkc CLKID_IEC958_GATE>,
++		 <&clkc CLKID_CTS_MCLK_I958>,
++		 <&clkc CLKID_CTS_AMCLK>,
++		 <&clkc CLKID_CTS_I958>;
++	clock-names = "fast", "iface", "mclk_i958", "mclk_i2s", "mclk";
++};
++
+ &spifc {
+ 	clocks = <&clkc CLKID_SPI>;
+ };
+@@ -774,3 +812,4 @@
+ 	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
+ 	power-domains = <&pwrc_vpu>;
+ };
++
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+index c87a80e9bcc6..20922cdc2c23 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+@@ -660,6 +660,34 @@
+ 	};
+ };
+ 
++&audio {
++	clocks = <&clkc CLKID_AIU>,
++		 <&clkc CLKID_AIU_GLUE>,
++		 <&clkc CLKID_I2S_SPDIF>;
++	clock-names = "aiu_top", "aiu_glue", "audin";
++	resets = <&reset RESET_AIU>,
++		 <&reset RESET_AUDIN>;
++	reset-names = "aiu", "audin";
++};
++
++&aiu_i2s_dma {
++	clocks = <&clkc CLKID_I2S_OUT>;
++	clock-names = "fast";
++};
++
++&aiu_spdif_dma {
++	clocks = <&clkc CLKID_IEC958>;
++	clock-names = "fast";
++};
++
++&i2s_dai {
++	clocks = <&clkc CLKID_I2S_OUT>,
++		 <&clkc CLKID_MIXER_IFACE>,
++		 <&clkc CLKID_AOCLK_GATE>,
++		 <&clkc CLKID_CTS_AMCLK>;
++	clock-names = "fast", "iface", "bclks", "mclk";
++};
++
+ &pwrc_vpu {
+ 	resets = <&reset RESET_VIU>,
+ 		 <&reset RESET_VENC>,
+@@ -742,6 +770,15 @@
+ 	num-cs = <1>;
+ };
+ 
++&spdif_dai {
++	clocks = <&clkc CLKID_IEC958>,
++		 <&clkc CLKID_IEC958_GATE>,
++		 <&clkc CLKID_CTS_MCLK_I958>,
++		 <&clkc CLKID_CTS_AMCLK>,
++		 <&clkc CLKID_CTS_I958>;
++	clock-names = "fast", "iface", "mclk_i958", "mclk_i2s", "mclk";
++};
++
+ &spifc {
+ 	clocks = <&clkc CLKID_SPI>;
+ };
+@@ -775,3 +812,4 @@
+ 	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
+ 	power-domains = <&pwrc_vpu>;
+ };
++
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0010-snd-meson-activate-HDMI-audio-path.patch

@@ -0,0 +1,55 @@
+From 5608714afb7c71054a01e4ad208b3eaa044041d4 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Fri, 7 Jul 2017 17:39:21 +0200
+Subject: [PATCH 10/53] snd: meson: activate HDMI audio path
+
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ sound/soc/meson/i2s-dai.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/sound/soc/meson/i2s-dai.c b/sound/soc/meson/i2s-dai.c
+index 1008af8d3972..63fe098ecf82 100644
+--- a/sound/soc/meson/i2s-dai.c
++++ b/sound/soc/meson/i2s-dai.c
+@@ -56,8 +56,19 @@ struct meson_i2s_dai {
+ #define AIU_CLK_CTRL_ALRCLK_RIGHT_J		(2 << 8)
+ #define AIU_CLK_CTRL_MORE_I2S_DIV_MASK		GENMASK(5, 0)
+ #define AIU_CLK_CTRL_MORE_I2S_DIV(div)		(((div) - 1) << 0)
++#define AIU_CLK_CTRL_MORE_HDMI_TX_SEL_MASK	BIT(6)
++#define AIU_CLK_CTRL_MORE_HDMI_TX_I958_CLK	(0 << 6)
++#define AIU_CLK_CTRL_MORE_HDMI_TX_INT_CLK	(1 << 6)
+ #define AIU_CODEC_DAC_LRCLK_CTRL_DIV_MASK	GENMASK(11, 0)
+ #define AIU_CODEC_DAC_LRCLK_CTRL_DIV(div)	(((div) - 1) << 0)
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_MASK	GENMASK(1, 0)
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_DISABLE	(0 << 0)
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_PCM		(1 << 0)
++#define AIU_HDMI_CLK_DATA_CTRL_CLK_I2S		(2 << 0)
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_MASK	GENMASK(5, 4)
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_MUTE	(0 << 4)
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_PCM		(1 << 4)
++#define AIU_HDMI_CLK_DATA_CTRL_DATA_I2S		(2 << 4)
+ #define AIU_I2S_DAC_CFG_PAYLOAD_SIZE_MASK	GENMASK(1, 0)
+ #define AIU_I2S_DAC_CFG_AOCLK_32		(0 << 0)
+ #define AIU_I2S_DAC_CFG_AOCLK_48		(2 << 0)
+@@ -221,6 +232,17 @@ static int meson_i2s_dai_hw_params(struct snd_pcm_substream *substream,
+ 		return ret;
+ 	}
+ 
++	/* Quick and dirty hack for HDMI */
++	regmap_update_bits(priv->core->aiu, AIU_HDMI_CLK_DATA_CTRL,
++			   AIU_HDMI_CLK_DATA_CTRL_CLK_SEL_MASK |
++			   AIU_HDMI_CLK_DATA_CTRL_DATA_SEL_MASK,
++			   AIU_HDMI_CLK_DATA_CTRL_CLK_I2S |
++			   AIU_HDMI_CLK_DATA_CTRL_DATA_I2S);
++
++	regmap_update_bits(priv->core->aiu, AIU_CLK_CTRL_MORE,
++			   AIU_CLK_CTRL_MORE_HDMI_TX_SEL_MASK,
++			   AIU_CLK_CTRL_MORE_HDMI_TX_INT_CLK);
++
+ 	return 0;
+ }
+ 
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0011-drm-meson-select-dw-hdmi-i2s-audio-for-meson-hdmi.patch

@@ -0,0 +1,22 @@
+From 5b3d41b6ad8275d53b758d6d4b95441b53cd320b Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Tue, 14 Feb 2017 19:18:04 +0100
+Subject: [PATCH 11/53] drm/meson: select dw-hdmi i2s audio for meson hdmi
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ drivers/gpu/drm/meson/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
+index 3ce51d8dfe1c..02d400b8795c 100644
+--- a/drivers/gpu/drm/meson/Kconfig
++++ b/drivers/gpu/drm/meson/Kconfig
+@@ -13,3 +13,4 @@ config DRM_MESON_DW_HDMI
+ 	depends on DRM_MESON
+ 	default y if DRM_MESON
+ 	select DRM_DW_HDMI
++	select DRM_DW_HDMI_I2S_AUDIO
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0012-ARM64-dts-meson-gx-add-sound-dai-cells-to-HDMI-node.patch

@@ -0,0 +1,38 @@
+From 461a8ba1e73d38b8cd8f8c931a8ae27676cdb085 Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Wed, 20 Sep 2017 18:01:26 +0200
+Subject: [PATCH 12/53] ARM64: dts: meson-gx: add sound-dai-cells to HDMI node
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+---
+ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 1 +
+ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi  | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+index 79132496691f..2a4d506bad4e 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+@@ -305,6 +305,7 @@
+ 		 <&clkc CLKID_CLK81>,
+ 		 <&clkc CLKID_GCLK_VENCI_INT0>;
+ 	clock-names = "isfr", "iahb", "venci";
++	#sound-dai-cells = <0>; 
+ };
+ 
+ &sysctrl {
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+index 20922cdc2c23..9f4b6185a61d 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+@@ -257,6 +257,7 @@
+ 		 <&clkc CLKID_CLK81>,
+ 		 <&clkc CLKID_GCLK_VENCI_INT0>;
+ 	clock-names = "isfr", "iahb", "venci";
++	#sound-dai-cells = <0>;
+ };
+ 
+ &sysctrl {
+-- 
+2.17.1
+

buildroot-external/board/hardkernel/patches/linux/0013-ARM64-dts-meson-activate-hdmi-audio-HDMI-enabled-boa.patch

@@ -0,0 +1,864 @@
+From dc4eb517f2800001f77bec852f8f688f0164e51b Mon Sep 17 00:00:00 2001
+From: Jerome Brunet <jbrunet@baylibre.com>
+Date: Wed, 20 Sep 2017 18:10:08 +0200
+Subject: [PATCH 13/53] ARM64: dts: meson: activate hdmi audio HDMI enabled
+ boards
+
+This patch activate audio over HDMI on selected boards
+
+Please note that this audio support is based on WIP changes
+This should be considered as preview and it does not reflect
+the audio I expect to see merged
+
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+---
+ .../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi  | 45 +++++++++++++++++++
+ .../boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 45 +++++++++++++++++++
+ .../dts/amlogic/meson-gxbb-nexbox-a95x.dts    | 45 +++++++++++++++++++
+ .../boot/dts/amlogic/meson-gxbb-odroidc2.dts  | 45 +++++++++++++++++++
+ .../boot/dts/amlogic/meson-gxbb-p20x.dtsi     | 45 +++++++++++++++++++
+ .../boot/dts/amlogic/meson-gxbb-wetek.dtsi    | 45 +++++++++++++++++++
+ .../amlogic/meson-gxl-s905x-khadas-vim.dts    | 45 +++++++++++++++++++
+ .../amlogic/meson-gxl-s905x-libretech-cc.dts  | 45 +++++++++++++++++++
+ .../amlogic/meson-gxl-s905x-nexbox-a95x.dts   | 45 +++++++++++++++++++
+ .../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 45 +++++++++++++++++++
+ .../dts/amlogic/meson-gxm-khadas-vim2.dts     | 45 +++++++++++++++++++
+ .../boot/dts/amlogic/meson-gxm-nexbox-a1.dts  | 45 +++++++++++++++++++
+ 12 files changed, 540 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+index 765247bc4f24..fb9ad6faa745 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+@@ -102,6 +102,39 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
+ };
+ 
+ &cec_AO {
+@@ -111,6 +144,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cvbs_vdac_port {
+ 	cvbs_vdac_out: endpoint {
+ 		remote-endpoint = <&cvbs_connector_in>;
+@@ -133,6 +174,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+index cbe99bd4e06d..5b10de9a0bad 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+@@ -88,6 +88,39 @@
+ 		clock-names = "ext_clock";
+ 	};
+ 
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
++
+ 	vcc1v8: regulator-vcc1v8 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "VCC1.8V";
+@@ -131,6 +164,14 @@
+ 	};
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cec_AO {
+ 	status = "okay";
+ 	pinctrl-0 = <&ao_cec_pins>;
+@@ -185,6 +226,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
+index 4cf7f6e80c6a..ff87bdc7ddbf 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
+@@ -119,6 +119,39 @@
+ 		clock-names = "ext_clock";
+ 	};
+ 
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
++
+ 	cvbs-connector {
+ 		compatible = "composite-video-connector";
+ 
+@@ -154,6 +187,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &ethmac {
+ 	status = "okay";
+ 	pinctrl-0 = <&eth_rmii_pins>;
+@@ -190,6 +231,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+index 54954b314a45..3da33090b8fe 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+@@ -110,6 +110,39 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
+ };
+ 
+ &cec_AO {
+@@ -119,6 +152,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &ethmac {
+ 	status = "okay";
+ 	pinctrl-0 = <&eth_rgmii_pins>;
+@@ -181,6 +222,10 @@
+ 	pinctrl-names = "default";
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+index ce862266b9aa..84eb93b4229f 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+@@ -113,6 +113,39 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
+ };
+ 
+ &cec_AO {
+@@ -122,6 +155,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cvbs_vdac_port {
+ 	cvbs_vdac_out: endpoint {
+ 		remote-endpoint = <&cvbs_connector_in>;
+@@ -140,6 +181,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
+index 70325b273bd2..7d1f1726f29d 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
++++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
+@@ -105,6 +105,47 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
++};
++
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
+ };
+ 
+ &cec_AO {
+@@ -159,6 +200,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+index d32cf3846370..f053595ebdc4 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+@@ -65,6 +65,39 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
+ };
+ 
+ &cec_AO {
+@@ -74,6 +107,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &hdmi_tx {
+ 	status = "okay";
+ 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+@@ -86,6 +127,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &i2c_A {
+ 	status = "okay";
+ 	pinctrl-0 = <&i2c_a_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+index f63bceb88caa..f56969efffba 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+@@ -84,6 +84,39 @@
+ 		regulator-always-on;
+ 	};
+ 
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
++
+ 	vcc_3v3: regulator-vcc_3v3 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "VCC_3V3";
+@@ -130,6 +163,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cvbs_vdac_port {
+ 	cvbs_vdac_out: endpoint {
+ 		remote-endpoint = <&cvbs_connector_in>;
+@@ -151,6 +192,10 @@
+ 	pinctrl-names = "default";
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &hdmi_tx {
+ 	status = "okay";
+ 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+index 6739697be1de..e3e777f665c0 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+@@ -102,6 +102,39 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
+ };
+ 
+ &cec_AO {
+@@ -111,6 +144,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cvbs_vdac_port {
+ 	cvbs_vdac_out: endpoint {
+ 		remote-endpoint = <&cvbs_connector_in>;
+@@ -135,6 +176,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
+index 5896e8a5d86b..f8c66a7972b3 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
+@@ -32,6 +32,39 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
+ };
+ 
+ &cec_AO {
+@@ -41,12 +74,24 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cvbs_vdac_port {
+ 	cvbs_vdac_out: endpoint {
+ 		remote-endpoint = <&cvbs_connector_in>;
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &hdmi_tx {
+ 	status = "okay";
+ 	pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+index 313f88f8759e..4fbfa5a850cc 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+@@ -85,6 +85,39 @@
+ 		};
+ 	};
+ 
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
++
+ 	pwmleds {
+ 		compatible = "pwm-leds";
+ 
+@@ -205,6 +238,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	#cooling-cells = <2>;
+ };
+@@ -279,6 +320,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &i2c_A {
+ 	status = "okay";
+ 	pinctrl-0 = <&i2c_a_pins>;
+diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+index f7a1cffab4a8..b9c5e6444daa 100644
+--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
++++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+@@ -75,6 +75,39 @@
+ 			};
+ 		};
+ 	};
++
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "meson-gx-audio";
++
++		assigned-clocks = <&clkc CLKID_MPLL2>,
++				  <&clkc CLKID_MPLL0>,
++				  <&clkc CLKID_MPLL1>;
++		assigned-clock-parents = <0>, <0>, <0>;
++		assigned-clock-rates = <294912000>,
++				       <270950400>,
++				       <393216000>;
++
++		simple-audio-card,dai-link@0 {
++			/* HDMI Output */
++			format = "i2s";
++			mclk-fs = <256>;
++			bitclock-master = <&i2s_dai>;
++			frame-master = <&i2s_dai>;
++
++			plat {
++				sound-dai = <&aiu_i2s_dma>;
++			};
++
++			cpu {
++				sound-dai = <&i2s_dai>;
++			};
++
++			codec {
++				sound-dai = <&hdmi_tx>;
++			};
++		};
++	};
+ };
+ 
+ &cec_AO {
+@@ -84,6 +117,14 @@
+ 	hdmi-phandle = <&hdmi_tx>;
+ };
+ 
++&audio {
++	status = "okay";
++};
++
++&aiu_i2s_dma {
++	status = "okay";
++};
++
+ &cvbs_vdac_port {
+ 	cvbs_vdac_out: endpoint {
+ 		remote-endpoint = <&cvbs_connector_in>;
+@@ -129,6 +170,10 @@
+ 	};
+ };
+ 
++&i2s_dai {
++	status = "okay";
++};
++
+ &ir {
+ 	status = "okay";
+ 	pinctrl-0 = <&remote_input_ao_pins>;
+-- 
+2.17.1
+